JPH03207092A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reject the trouble of a memory cell in a short time by forming a bit line load so as to obtain large dimension only at the time of a test mode. CONSTITUTION:When a test mode signal is operated at H, the characteristic of the memory cell is changed since the load of the bit line is L1+M1 and L2+M2. Even in such a state, the normal memory cell is normally operated unless some disturbance is applied, and however, latch can not be executed to the defective memory cell. Therefore, the trouble is rejected even in a normal function test. Thus, since the ON resistance of the bit line load is decreased only at the time of the test mode, the trouble of the memory cell can be rejected in a short time.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a static random access memory (
This relates to shortening the test time for SRAM.

[Conventional technology]

In FIG. 3, b1. b2 is a pair of bit lines Ll, L
2 is the load transistor AI, A attached to bl, b2
2, I 1, I2 are memory cell transistors, Rl,
R2 represents the load resistance of the memory cell. These transistors are all N-channel transistors. W indicates memory cell selection; it, CC indicates power supply voltage, and GND indicates ground potential.

al and a2 are node names.

The memory cell of SRAM is usually a flip-flop, and consists of two inverters. When W is at "L" level and the memory cell is not selected, these two inverters are an inverter consisting of R1 and ■1, It means an inverter consisting of R2 and I2, and is a resistive load type. In this case, the strength of the latch is determined by the ratio of the resistance values of R1 and R2 to the on-resistances of Il and 12Q, and there will be no problem if the resistances of Rl and R2 are made sufficiently large.

When W is at “H” level and a memory cell is selected, the inverter is a monolith consisting of Ll, AI, and II, L2,
It consists of two parts, A2 and I2. At this time, Rl and R2 can be ignored since they usually have large resistance values. Among these, think about the inperter made up of L1, AI, and I1. W is “H” (Vee)
Since it is a Repe, Re, it can be considered as an inverter with an enhancement transistor load as shown in FIG. 4, and its characteristics are as shown in FIG. When 0≦VIN≦V7, (threshold voltage of N-channel transistor), I1 is in the OFF state,
Thea 11; tVee-V7H tonal through Ll, AI. When V≦V IN≦Vee, I1 has an on-resistance according to the value of VIN, L1 and A1 each have an on-resistance, and the resistance is divided between Vce and GND by the sum of these and the on-resistance of I1. A potential is applied to a1. The solid line in FIG. 5 is a graph of this characteristic.

The characteristics of the inverters L2, A2, and I2 are similar, and since the input and output terminals are reversed, they can be overlapped as shown by the dotted line. The intersection of the solid line and the dotted line is the stable point,
The larger the area of the diagonal line, the more difficult it is for the flip-flop to flip. In other words, the larger the ON resistance of I1 when V IN is at the "H" level compared to the ON resistances of Ll and A1, the larger this area becomes. However, A1 ON
If the resistance is made small, the signals of the nodes al and a2 will be difficult to be transmitted to the bit lines bl and b2, and the operation speed will be slowed down. L
If the ON resistance of 1 is made smaller, the write characteristics deteriorate.

It is necessary to give the dimension ν of the transistor comprehensively from these.

[Problem to be solved by the invention]

Conventional SRAMs are constructed as described above, and there are no particular problems if they are designed with appropriate dimensionality rules.

However, for example, if it is an IM bit SRAM,
There are 1 million memory cells in the same chip. Furthermore, when millions to tens of millions of the same chip are produced, the characteristics of individual memory cells will vary greatly. If it doesn't work at all, try a simple function. There are also memory cells that fail in the internal test, but normally operate normally and only become defective in special cases.

For example, the finished dimensions of transistor A2 vary,
When the ON resistance of the load becomes small, the characteristics of the memory cell become as shown in FIG. 6, and it becomes easier to invert than a normal memory cell. When a1 is at “H” level and i2 is at “L” level, read another memory cell where b1 is “L” and b2 is “H”, then read this memory cell, and then read the next (again) When the operation of reading another memory cell in which b1 is at "L" level and b2 is at "H" level is performed continuously in a short cycle time, the memory cell is affected by the bit line level, and al, The level of a2 may gradually change and eventually be reversed.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to be able to reject memory cells whose characteristics deviate from the distribution without making the conditions particularly severe.

[Means to solve the problem]

The SRAM according to the present invention enters the test mode by some external signal, and has additional means for lowering the ON resistance of the bit line load only when the test mode is entered.

[Effect]

The SRAM according to the present invention is capable of rejecting a memory cell failure that occurs due to long-term disturb in a single period of time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. bl
, b2 are a pair of bit lines, Ll, L2, Ml, M2 are b
l, load transistor attached to b2, AI, A2,
II and I2 represent transistors of the memory cell, and Rl and R2 represent load resistances of the memory cell. These transistors are all N-channel transistors. W represents a memory cell selection line, Vce represents a power supply voltage, and GND represents a ground potential.

al and a2 are node names.

Since the bit line load transistors M1 and M2 in FIG. 1 are normally turned off (gates at "L" level), they do not affect the operation in any way. In other words, when used normally, it is exactly the same as a conventional circuit.

On the other hand, somehow set the test mode signal to “H”,
When operated, the load on the bit line becomes L10M1 and L20M2, so the characteristics of the memory cell change. In Fig. 2 (a), the inverter composed of L 1 (including M 1), A1, and I1 is shown as a solid line when M1 is OFF, and as a dotted line when M1 is ON and OFF. become,
In the characteristic diagram of the memory cell, the area of the shaded area is also smaller, and the stability is lower. Even in this state, normal memory cells will operate normally unless disturb is applied, but a defective memory cell will have the characteristics shown in Figure 2 (b), and the memory cell will not latch and will function normally. He will also be rejected from the funksi test.

In addition, in the above embodiment, transistors M1 and M2 of the same Dimensison were added to b1 and b2@, but M1
For cases where only M2 is added and cases where only M2 is added,
There are also methods for making the symmetry of memory cells worse.

〔Effect of the invention〕

As described above, according to the present invention, since the bit line load is configured to have a large amount of damage only in the test mode, it is possible to reject defects that previously took a long time to reject in a short time. It became.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a part of a circuit including memory cells of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2(a)
(b) is a characteristic diagram showing the characteristics of the memory cell shown in FIG. 1; Fig. 3 is a circuit diagram showing part of a circuit including memory cells of a conventional semiconductor memory device, Fig. 4 is an extracted part of the circuit in Fig. 3, and Fig. 5 is a characteristic of a normal memory cell. FIG. 6 shows a characteristic diagram of a defective memory cell. In the figure. (bl) (b2) is a bit line. (L
l) (L2J (Ml) (M2) is the load transistor, (AI) (A2) (It) (12) is the transistor, (Rl) (R2) is the load resistance. Note that the same symbols in each figure are the same. or a corresponding portion.

Claims (1)

[Claims] A semiconductor memory device includes a plurality of flip-flop memory cells, a pair of bit lines for inputting and outputting signals from these memory cells and peripheral circuits, and a load transistor for fixing these bit lines to a constant level. A semiconductor memory device characterized in that the magnitude of the load on the bit line can be changed only during a shipping test.