JPH03205728A - Latch relay drive circuit - Google Patents

Abstract

PURPOSE:To prevent the change of the latch relay state when a power source is turned on or off by using NAND drivers as relay drivers, and prohibiting a noise pulse from a pulse generating circuit generated when the power source is turned on or off with a gate signal generating circuit constituted of an integrating circuit and a discharge circuit. CONSTITUTION:Two-input NAND drivers 4, 5 are provided as drivers with a gate function, and the set signal 101a and reset signal 101b from a set/reset control signal generating circuit 1 are inputted to one input through pulse generating circuits 2, 3. The output 107 of a gate signal generating circuit 107 operated to prohibit noise pulses generated from the pulse generating circuits 2, 3 when a power source is turned on or off is connected to the other input. An integrating circuit constituted of a resistor 8 with a relatively large value and a capacitor 10 is provided, a discharge circuit is constituted of a resistor 9 with a relatively small value and another switch SW2 operated in conjunction with a power switch SW1, and a gate signal 107 is outputted. Even if noise pulses are generated in the pulse generating circuits 2, 3 when the power source is turned on or off, a latch relay is not operated erroneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an adjustment circuit for a latch relay that sets and resets by pulse-driving a set coil and a reset coil.

[Conventional technology]

The conventional latch relay drive circuit is JP-A-60-221.
As described in Publication No. 918, a monostable multivibrator is used as an example of a pulse generation circuit that generates a set pulse and a reset pulse to generate a relay control signal and apply a pulse current to each of the set coil and reset coil. This caused the latch relay to be driven.

[Problem to be solved by the invention]

The conventional technology described above limits the input trigger signal to the monostable multivibrator so that the monostable multivibrator does not malfunction when the power is turned on or off, and as a result, the latch relay is prevented from malfunctioning. However, in general, the power supply voltage is unstable when the power is turned on or off, so monostable multivibrators may malfunction even when no trigger signal is input to them, and the pulse signal (hereinafter referred to as noise) There is a problem in that a pulse (called a pulse) is generated and the state of the latch relay changes.

An object of the present invention is to prevent the state of a latch relay from changing even if a pulse generating circuit such as a monostable multivibrator malfunctions when power is turned on or off.

Another object of the present invention is to prevent malfunction of the latch relay due to unintentional power interruption due to a power outage or the like, or due to power restoration after a power outage or the like.

[Means to solve the problem]

In order to achieve the above object, a two-man NAND driver is provided as a driver having a gate function, and one input receives a set signal and a reset signal from a set/reset control signal generation circuit through a pulse generation circuit.

The other input is connected to the output of a gate signal generation circuit that operates to inhibit noise pulses generated from the pulse generation circuit when power is turned on/off. The output signal of the gate signal generation circuit, that is, the signal that turns on the gate with a predetermined delay when the power is turned on, and turns the gate off immediately when the power is turned off, is an integral signal that is made up of a relatively large value resistor and capacitor. In addition, a discharge circuit is configured with a resistor of a relatively small value and another switch that operates in conjunction with the power switch, and the gate signal is outputted.

In order to achieve the other objectives mentioned above, as an alternative to the switch that operates in conjunction with the power switch, a reference voltage and a comparator for detecting the power supply voltage, and a transistor that turns on and off depending on the output state of the comparator are used. A gate signal is output by using a power supply voltage detecting element, connecting the power supply voltage to the input of a comparator of the element, and replacing the switch of the gate signal generation circuit with a transistor.

[Effect]

The present invention uses a NAND driver as a relay driver, and uses a gate signal generation circuit composed of an integrating circuit and a discharge circuit to inhibit noise pulses from the pulse generation circuit generated when power is turned on or off. The integrating circuit is
When the power is turned on, the gate of the NAND driver is delayed by a predetermined time and the gate is turned on, thereby inhibiting noise pulses generated from the pulse generation circuit.When the power is turned off, the discharge circuit immediately turns on the gate of the NAND driver. By turning it off, it operates to inhibit noise pulses generated from the pulse generation circuit.

This prevents the latch relay from malfunctioning even if the pulse generating circuit generates noise pulses when the power is turned on or turned off.

In addition, when the power supply voltage detection element is turned on, when the power supply voltage becomes higher than the reference voltage in the element, the comparator output in the element becomes low level (false), and the transistor in the element turns off. By turning on the gate after being turned off and delayed for a predetermined time by the above-mentioned integration circuit, noise pulses from the pulse generation circuit are prohibited, and when the power is cut off, the comparator outputs when the power supply voltage becomes lower than the reference voltage. becomes high level (true) and turns on the transistor, which operates to inhibit the noise pulse by immediately turning off the gate in the aforementioned discharge circuit.

By using the latch relay drive circuit that operates as described above, the latch relay will not malfunction even if the pulse generation circuit malfunctions when the power is turned on or shut off due to non-artificial power failures such as when a power outage occurs. The state of is maintained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 shows an embodiment of the latch relay drive circuit of the present invention, and FIG. 2 is a diagram showing an operation time chart of FIG. 1.

A signal for setting or resetting the latch relay is generated by the set/reset control signal generation circuit 1 as a command from a switch or CPU, etc., as a set signal 101a,
A reset signal 10lb is generated. Set signal 101a
Since the reset signal 10lb is a pulse signal with a time width necessary for the operation of the latch relay, a monostable multivibrator (hereinafter referred to as M) is used as an example of a pulse generation circuit.
M. M2, and M. M3, generates a set signal 102 and a reset signal 103, which have a predetermined pulse width, and inputs them to one input of driver gates 4 and 5, and outputs them to set coil 6-a of latch relay 6. , drives the reset coil 6-b.

Here, M. M2 and M. When the power is turned on or turned off, M3 may generate noise pulses such as a, a, b, and b' as shown in set and reset signal waveforms 102 and 103 in FIG.

When this noise pulse is applied to the latch relay, the on/off state of the relay changes, and there is a problem that when the power is turned off and then turned on again, the state before the power is turned off is not maintained.

In order to prevent malfunctions caused by this noise pulse, as shown in FIG. The output is connected to the other input of the driver gates 4 and 5.

The switch SW2 operates so as to be turned off when the power is turned on, and operates an integrating circuit including a resistor 8 and a capacitor 10 to obtain an integrated waveform of the signal waveform 108 shown in FIG. This integral waveform is converted to TTL by Schmitt trigger gate 7.
It is converted into a level output, becomes a signal 107 that becomes high level (true) with a delay of T after the power is turned on, and is applied to the driver gates 4 and 5. The time T obtained by the integrating circuit is the time from when the power is turned on until the power supply voltage stabilizes, and M
．． M2, M. The set signal 10 shown in FIG.
Even if noise pulses a and b occur in the reset signal 103 and the gate signal 107, they will not be output to the latch relay drive signals 104 and 105, and malfunction of the latch relay will be prevented. Ru.

In addition, when the power is cut off, switch SW2 is in the on state.
The charge accumulated in the capacitor 10 is discharged via the resistor 9. By setting the resistor 9 to a small resistance value of several ohms to several tens of ohms, it is discharged at high speed, and the integral waveform 1
08 quickly becomes a low level (false), and the gate signal 10
7 becomes low level (false) almost at the same time as the power is cut off, and operates to turn off the driver gates 4 and 5. Therefore, when the power is cut off, the set signal 102 and the reset signal 1
The noise pulses a and b' generated at 03 are prohibited and are not output to the latch relay drive signals 104 and 105, thereby preventing malfunction of the latch relay.

FIG. 3 shows an embodiment in which a power supply voltage detection element capable of detecting the power supply voltage is used instead of using the switch SW2 of FIG. 1 according to the present invention. Since this element uses a method in which the comparator 12 detects the power supply voltage by comparing it with the reference voltage 13, the comparator 12 is configured to operate from a voltage lower than the reference voltage 13. The reference voltage 13 is 4.5V, and when the power supply voltage exceeds this, the output of the comparator l2 becomes low level (false), the transistor 14 is turned off, and the integration circuit operates to produce the integrated waveform shown in Figure 2. A signal similar to 108 is obtained. The integral waveform 108 is converted to a TTL level through the Schmitt trigger gate circuit 7, and becomes a signal 107 that becomes high level (true) with a delay of T after the power is turned on, and operates so that the driver gates 4 and 5 are turned on. .

On the other hand, when the power supply voltage drops below 4.5■, the transistor 14 is turned on and the driver gates 4 and 5 are immediately turned on.
It operates so that the switch is turned off.

〔Effect of the invention〕

According to the present invention, the noise pulse of a pulse generation circuit such as a monostable multivibrator, which is generated when the power is turned on or off, is prohibited by the NAND driver,
Since it is not output as a latch relay drive signal, the state of the latch relay does not change when the power is turned on or off.

[Brief explanation of drawings]

Figure 1 is a latch relay drive circuit diagram of an embodiment of the present invention.
FIG. 2 is a diagram showing a time chart of the latch relay drive circuit in FIG. 1, and FIG. 3 is a diagram showing a latch relay drive circuit when a power supply voltage detection element is used as a substitute for the switch in FIG. 1. ... Set/reset control signal generation circuit diagram, 2, 3... Pulse generation circuit (monostable multivibrator). 4, 5...driver gate,
6... Latch relay, 8... Resistor for integrating circuit, 1
0... Capacitor for integrating circuit, 11... Power supply voltage detection element, SW2... Switch.

Claims (1)

[Claims] 1. A latch relay having two windings, a set coil and a reset coil, includes two drive means for driving the coils and two drive means for applying a predetermined pulse signal to the drive means. In a latch relay drive circuit comprising a pulse generating means and a set/reset control signal generating means for applying a trigger signal to the pulse generating means, a gate means for controlling the drive means for the coil and supplying the signal to the gate means. A latch relay drive circuit characterized by adding an integrating means. 2. The latch relay drive circuit according to claim 1, wherein the integrating means includes a switch that operates synchronously when the power is turned on.