JPH03204946A - Substrate connected with ic - Google Patents

Substrate connected with ic

Info

Publication number
JPH03204946A
JPH03204946A JP34400089A JP34400089A JPH03204946A JP H03204946 A JPH03204946 A JP H03204946A JP 34400089 A JP34400089 A JP 34400089A JP 34400089 A JP34400089 A JP 34400089A JP H03204946 A JPH03204946 A JP H03204946A
Authority
JP
Japan
Prior art keywords
terminals
ics
substrate
wiring
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34400089A
Other languages
Japanese (ja)
Inventor
Akira Mase
晃 間瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP34400089A priority Critical patent/JPH03204946A/en
Publication of JPH03204946A publication Critical patent/JPH03204946A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid the grade crossing of wirings formed on a substrate by a method wherein out of the input terminals of a plurality of ICs, at least one kind of the terminals for inputting a common input signal are electrically connected in series by the wirings. CONSTITUTION:In ICs, gold bumps are respectively formed at terminal parts, input terminals 12 and 13, 14 and 16, 16 and 17 and 18 and 19 are electrically short-circuited from each other and the terminals other than the terminal 12 or terminals 20 are described as ones which are not terminals for inputting a common signal. The connection method of the ICs with a substrate is performed by a method wherein an ultraviolet curing resin is put on the ICs and after the substrate and the ICs are aligned to each other, the substrate and the ICs are subjected to pressure bonding to each other in a state that they are heated at about 100 deg.C and an ultraviolet irradiation is performed. Wirings 50 are formed and moreover, all the common signal input terminals, which are connected by means of a cascade connection excluding the terminals 20, of the ICs are electrically connected in series. Therefore, there is no need to provide the wirings 50 in a grade crossing and the yield of the formation of the wirings is also significantly risen.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は液晶表示装置やイメージセンサ−等のICが直
接搭載された基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a substrate on which an IC such as a liquid crystal display device or an image sensor is directly mounted.

〔従来の技術〕[Conventional technology]

液晶電気光学装置やイメージセンサ−等のドライバーI
Cは従来パッケージングされた状態でプリント基板の上
に搭載され、液晶パネル或いはイメージセンサ−本体部
とFPC等を用いて接続されている。だが、最近は重い
プリント基板の使用を避け、装置を軽くしかも小さくす
るために、液晶パネル或いはイメージセンサ−等を構成
する基板上にICチップの状態で直接搭載する方法(C
OG=チップオングラス、COB:チップオンボードな
どと称する)もある。
Driver I for liquid crystal electro-optical devices, image sensors, etc.
Conventionally, C is mounted on a printed circuit board in a packaged state, and connected to a liquid crystal panel or an image sensor main body using an FPC or the like. However, recently, in order to avoid the use of heavy printed circuit boards and to make devices lighter and smaller, methods have been developed in which IC chips are directly mounted on substrates that make up liquid crystal panels, image sensors, etc.
There are also other names such as OG (chip on glass) and COB (chip on board).

ICチップを基板上に直接搭載する場合の方法はICチ
ップの入出力端子が上向きになるフェイスアップボンデ
ィング、或いはICチップの入出力端子が下向きになる
フェイスダウンボンディングがある。フェイスアップボ
ンディングの場合は通常、金の細線を用いてICの端子
と基板上に形成された配線とをワイヤーボンディングに
より接続を行う。また、フェイスダウンボンディングの
場合は、基板上に形成された配線またはICの端子部に
金或いはハンダ等からなる凸状のバンブを形成し、IC
と配線との電気的接続を図っている。
Methods for directly mounting an IC chip on a substrate include face-up bonding, in which the input and output terminals of the IC chip face upward, and face-down bonding, in which the input and output terminals of the IC chip face downward. In the case of face-up bonding, the terminals of the IC and the wiring formed on the substrate are usually connected by wire bonding using thin gold wires. In addition, in the case of face-down bonding, a convex bump made of gold or solder is formed on the wiring formed on the board or the terminal part of the IC, and the IC
Electrical connection is being made between the cable and the wiring.

〔従来の技術の問題点〕[Problems with conventional technology]

しかしながら、ワイヤーボンディングによってICの入
出力端子と基板上に形成された配線とを接続する場合は
、当然のことながらICの端子と配線との接続を1本ず
つ行わなければならない。
However, when connecting the input/output terminals of the IC and the wiring formed on the substrate by wire bonding, it is obvious that the connection between the IC terminal and the wiring must be made one by one.

そのため、ICの端子数が多くなると、金のワイヤーの
本数も増すために、1個のICを接続するだめの時間が
非常に長くなり、生産コストの上昇につながる。さらに
、この方法は接続箇所が基板上の配線と金ワイヤ−、金
ワイヤーとIC端子と1本のワイヤーについて2か所存
在するため歩留りも悪くなる。
Therefore, as the number of terminals on an IC increases, the number of gold wires also increases, which takes a very long time to connect one IC, leading to an increase in production costs. Furthermore, in this method, there are two connection points for each wire: the wiring on the board and the gold wire, and the gold wire and the IC terminal, resulting in poor yield.

また、フェイスダウンボンディング法を用いた場合につ
いて述べると、1個のICの接続を1回の工程で行うこ
とができるため、ICの端子が増えても工程に要する時
間は変わらないという長所を有する。しかし、液晶電気
光学装置やイメージセンサ−等に用いられる複数のIC
を基板上に搭載する際にはカスケード接続が行われるが
、複数のICの各入力端子のうち、共通の信号を入力す
る少なくとも1種類の端子がそれぞれ電気的に並列に接
続されていた。このことを第2図を用いて説明すると、
共通の信号をICに入力するための配線(23)とI 
C(21) 、 (22)の端子(26) 、 (29
)を、同様に配線(24)と端子(27) 、 (30
)を、配線(25)と端子(28) 、 (31)とを
それぞれ接続するために配線(24)と端子(27) 
、 (30)との間の接続には配線(23)が邪魔にな
り、立体配線部分(100)が必要となる。
In addition, when using the face-down bonding method, since one IC can be connected in one process, it has the advantage that the time required for the process does not change even if the number of IC terminals increases. . However, multiple ICs used in liquid crystal electro-optical devices, image sensors, etc.
When mounted on a board, a cascade connection is performed, and among the input terminals of the plurality of ICs, at least one type of terminal that inputs a common signal is electrically connected in parallel. To explain this using Figure 2,
Wiring (23) and I for inputting common signals to IC
Terminals (26) and (29) of C(21) and (22)
), similarly wire (24) and terminal (27), (30
), the wiring (24) and the terminal (27) to connect the wiring (25) and the terminals (28) and (31), respectively.
, (30), the wiring (23) gets in the way and requires a three-dimensional wiring part (100).

また配線(25)と端子(28) 、 (31)の接続
には配線(23) 、 (24)が邪魔になり立体配線
が必要となる。また、立体配線を行った結果、共通の信
号を人力するための端子(26)と(29)、(27)
と(30)、(2日)と(31)はそれぞれ電気的に並
列に接続されている。
Furthermore, the wiring (23) and (24) get in the way of connecting the wiring (25) and the terminals (28) and (31), requiring three-dimensional wiring. In addition, as a result of three-dimensional wiring, terminals (26), (29), and (27) for manually inputting common signals were installed.
(30), (2nd), and (31) are electrically connected in parallel.

そして、配線の形成には通常フォトリソ法、或いは印刷
法などが用いられているため、立体配線を作製しようと
すると歩留りの低下がひどく、全体の装置としても高価
なものになってしまっていた。また、立体配線のために
は必ず絶縁層が必要であり、その絶縁層の一部をエツチ
ングしてコンタクトホールを設ける必要がある。このた
め、高度な技術と複雑な作製工程が必要であった。
Furthermore, since photolithography or printing methods are usually used to form wiring, the yield is severely reduced when three-dimensional wiring is produced, and the overall device becomes expensive. In addition, an insulating layer is always required for three-dimensional wiring, and a contact hole must be provided by etching a portion of the insulating layer. For this reason, advanced technology and complicated manufacturing processes were required.

〔発明の目的〕[Purpose of the invention]

上記問題点を解決するため本発明は、複数のICを基板
上に形成された配線に対しカスケード接続を行う場合に
、基板上に形成された配線の立体交差を回避することを
目的とする。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to avoid three-dimensional intersections of wiring formed on a substrate when a plurality of ICs are connected in cascade to the wiring formed on the substrate.

〔発明の構成〕[Structure of the invention]

上記目的を達成するため本発明は、複数の配線が形成さ
れ、かつ該配線に複数のICがカスケード接続された基
板であって、前記複数のICの入力端子のうち、共通の
入力信号を入力する少なくとも一種類の端子が前記配線
によって電気的に直列に接続されていることを特徴とす
る。
In order to achieve the above object, the present invention provides a substrate on which a plurality of wirings are formed and a plurality of ICs are cascade-connected to the wirings, wherein a common input signal is input from input terminals of the plurality of ICs. At least one type of terminal is electrically connected in series by the wiring.

本発明の構成を実現するためには、例えば共通の信号を
入力する端子を2つ有し、該2つの端子は電気的に短絡
した状態であるICを用いる方法や、または入力端子が
基板に形成された配線とある角度を有して配列したIC
を用いる方法や、ICの周辺部のうち、少なくとも一部
に入出力端子のない部分を有するICを用いる方法や、
或いは基板に形成された配線の幅より大きい端子間隔を
有するICを用いる方法など数多く存在する。以下、実
施例により本発明の詳細な説明する。
In order to realize the configuration of the present invention, for example, there is a method using an IC that has two terminals for inputting a common signal and the two terminals are electrically short-circuited, or a method in which the input terminal is connected to the board. IC arranged at a certain angle with the formed wiring
A method using an IC that has at least a part of the peripheral part of the IC without input/output terminals,
Alternatively, there are many methods such as using an IC having a terminal interval larger than the width of the wiring formed on the substrate. Hereinafter, the present invention will be explained in detail with reference to Examples.

〔実施例1〕 本実施例は基板上にICを搭載した液晶電気光学装置を
作製した場合について第1図を用いて説明する。まず、
一対のソーダガラス基板(1)、 (2)上に透明導電
膜であるITOを1500人成膜し、フォトリソ法によ
って電極(3)を形成する。そして、基板の周囲部分の
ITO電極上のみには金メツキ(4)を行った。そして
、オフセット印刷法によって液晶配向膜としてポリイミ
ド膜(5)を形成する。この配向膜の形成方法としては
、ポリアミック酸のNMP溶液を基板上に塗布した後、
250°Cで3時間熱処理を行うことによって得た。
[Example 1] In this example, a case where a liquid crystal electro-optical device having an IC mounted on a substrate is manufactured will be explained using FIG. 1. first,
1,500 ITO films, which are transparent conductive films, are deposited on a pair of soda glass substrates (1) and (2), and electrodes (3) are formed by photolithography. Then, gold plating (4) was performed only on the ITO electrodes around the substrate. Then, a polyimide film (5) is formed as a liquid crystal alignment film by an offset printing method. The method for forming this alignment film is to apply an NMP solution of polyamic acid onto the substrate, and then
It was obtained by heat treatment at 250°C for 3 hours.

次に、一対の基板の配向膜形成面をラビング処理を行う
。そして、一方の基板上に直径5.5μmののポリスチ
レン粒子(6)を散布した。この散布方法は、ポリスチ
レン粒子30mgをIPA(イソプロピルアルコール)
0.51!、中に混合し、超音波を印加して良く攪拌さ
せた後ノズルを用いて散布を行った。また、他方の基板
にはエポキシ系の接着材(7)をスクリーン印刷法によ
り印刷し、一対の基板の貼り合わせを行った。
Next, a rubbing process is performed on the alignment film forming surfaces of the pair of substrates. Then, polystyrene particles (6) having a diameter of 5.5 μm were scattered on one of the substrates. This spraying method uses 30 mg of polystyrene particles with IPA (isopropyl alcohol).
0.51! , and after applying ultrasonic waves and stirring well, spraying was performed using a nozzle. Furthermore, an epoxy adhesive (7) was printed on the other substrate by a screen printing method, and the pair of substrates were bonded together.

こうして組み合わされたパネル内に公知の真空注入法を
用いてカイラル成分の添加されたネマティック液晶(8
)を注入し、注入口を紫外線硬化樹脂を用いて封止した
A nematic liquid crystal (80%
) was injected, and the injection port was sealed using ultraviolet curing resin.

そして基板の外側に偏光板(9)、 (10)を貼付し
た。
Then, polarizing plates (9) and (10) were attached to the outside of the substrate.

その後、基板の周囲部に形成された金メツキをされた配
線上に走査電極側に6個、信号電極側に8個のIC0I
)のカスケード接続を行った。金メツキの施された配線
部の様子は第3図のようになっていて、さらにICは端
子部に金バンブが形成されたものを用い、また第3図に
おいて入力端子02)と(13)、 (lJト(15)
、 QE)トQ7)、 08)ト09)ハ?!気的に短
絡シたICを用いている。また第3図は、図に示す端子
のうち021ないしQΦ基以外端子は共通信号を入力す
るための端子ではないものとして記載した。
After that, on the gold-plated wiring formed around the substrate, 6 IC0Is are placed on the scanning electrode side and 8 IC0Is are placed on the signal electrode side.
) was cascaded. The appearance of the gold-plated wiring section is as shown in Fig. 3. Furthermore, the IC uses an IC with gold bumps formed on the terminal section, and input terminals 02) and (13) in Fig. 3 are used. , (lJ (15)
, QE) GQ7), 08) G09) Ha? ! An IC that is mechanically shorted is used. Furthermore, in FIG. 3, among the terminals shown in the figure, the terminals other than the terminals 021 to QΦ are not terminals for inputting common signals.

また接続の方法は、IC上(端子の存在する面)に紫外
線硬化樹脂をのせ、基板とICの位置合わせ後、約10
0℃に加熱した状態で基板とICを圧着し、紫外線照射
を行う方法を用いた。すべてのICの接続終了後、駆動
回路との接続を行い、液晶電気光学装置が完成した。
In addition, the connection method is to place ultraviolet curing resin on the IC (the surface where the terminal is present), and after aligning the board and IC,
A method was used in which the substrate and IC were pressed together while heated to 0° C., and then irradiated with ultraviolet rays. After all the ICs were connected, they were connected to the drive circuit, and the liquid crystal electro-optical device was completed.

本実施例においては、第3図に示すように配線(50)
を形成し、さらに前に述べたように入力端子021と0
3)、 04)と面、・・・が電気的に短絡しているた
め、C’l)を除くカスケード接続されたすべてのIC
の共通信号入力端子は電気的に直列に接続されている。
In this embodiment, as shown in FIG.
, and as mentioned earlier input terminals 021 and 0
3), 04) and planes are electrically shorted, so all cascade-connected ICs except C'l)
The common signal input terminals of are electrically connected in series.

そのため第3図に示された配線は立体交差をする必要が
なく、そのため歩留りも大幅に上昇する。
Therefore, the wiring shown in FIG. 3 does not need to have three-dimensional intersections, which greatly increases the yield.

〔実施例2〕 本実施例においては、本発明をイメージセンサ−に応用
した場合について説明する。
[Embodiment 2] In this embodiment, a case where the present invention is applied to an image sensor will be described.

ガラス基板上に遮光層、光電変換層、電極を形成するこ
とにより、センサ一部を作製する。この時、電極はセン
サ一部のみではなくICを接続するための配線としても
同時に形成する。
A part of the sensor is manufactured by forming a light shielding layer, a photoelectric conversion layer, and an electrode on a glass substrate. At this time, the electrode is formed not only as a part of the sensor but also as a wiring for connecting the IC.

ICが接続される部分の配線はすべて前記電極の構成物
質によって形成されている。
All the wiring in the portion to which the IC is connected is formed of the constituent material of the electrode.

この後、金バンブを端子部に有するICを用い、実施例
1と同様な方法でICと配線とを接続した。ただし、本
実施例ではIC接続時の加熱温度は150°Cである。
Thereafter, the IC and wiring were connected in the same manner as in Example 1 using an IC having gold bumps in the terminal portion. However, in this embodiment, the heating temperature when connecting the IC is 150°C.

この状態において、ICが接続された部分の様子を第4
図に示す。本実施例に用いたICは端子(32)、(3
3)、(34)の配列方向が、基板上の配線(35)の
方向とは角度がθだけずれているために、(32)、(
33)、(34)はそれぞれすべてのICについて電気
的に直列に接続され、基板上に形成する配線(35)を
立体交差させる必要がなくなった。ただし第4図におい
て図に示された端子のうち(32) 、 (33)、(
34)以外の端子は共通信号を入力するための端子では
ないものとする。
In this state, the state of the part where the IC is connected is shown in the fourth section.
As shown in the figure. The IC used in this example has terminals (32) and (3).
Since the arrangement direction of (3) and (34) is deviated by an angle of θ from the direction of the wiring (35) on the board, (32), (
33) and (34) are electrically connected in series for all ICs, eliminating the need for three-dimensional crossing of the wiring (35) formed on the substrate. However, among the terminals shown in Fig. 4, (32), (33), (
It is assumed that terminals other than 34) are not terminals for inputting common signals.

〔実施例3〕 第5図に示すような端子配置((36) 、 (37)
 、 (38)は共通信号の入力端子)を有するICを
実施例2のイメージセンサ−に用いた。この場合、IC
の端子と基板上に形成された共通信号の入力配線(40
)との接続の位置関係は第5図に示すようになり、(3
6)、(37)、(38)はすべてのICについて電気
的に直列に接続されているため、配線の立体交差を回避
することができた。
[Example 3] Terminal arrangement as shown in Fig. 5 ((36), (37)
, (38) is a common signal input terminal) was used in the image sensor of Example 2. In this case, I.C.
common signal input wiring (40
) is shown in Figure 5, and (3
6), (37), and (38) are electrically connected in series for all ICs, so it was possible to avoid three-dimensional crossing of wiring.

(効果〕 以上述べたように、本発明を用いることにより基板上に
形成された配線上に複数のICをカスケード接続する場
合に、複数のICに入力する共通の信号を供給するため
の配線を立体交差させる必要がなくなり、COO或いは
COB法の歩留りを大幅に向上させることができ、コス
トダウンを実現できた。
(Effects) As described above, when multiple ICs are cascade-connected on wiring formed on a substrate by using the present invention, wiring for supplying common signals input to multiple ICs is There is no need for three-dimensional intersection, the yield of the COO or COB method can be significantly improved, and costs can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、液晶電気光学装置の断面の概略を示す。 第2図は、基板上に形成された配線とICの端子の従来
の接続の様子を示す。 第3図、第4図、第5図は、本発明による、基板上に形
成された配線とICの端子の接続の様子を示す。
FIG. 1 schematically shows a cross section of a liquid crystal electro-optical device. FIG. 2 shows a conventional connection between wiring formed on a substrate and terminals of an IC. FIGS. 3, 4, and 5 show how wiring formed on a substrate and terminals of an IC are connected according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 1、複数の配線が形成され、かつ該配線に複数のICが
カスケード接続された基板であって、前記複数のICの
入力端子のうち、共通の入力信号を入力する少なくとも
一種類の端子が前記配線によって電気的に直列に接続さ
れていることを特徴とするICが接続された基板
1. A board on which a plurality of wirings are formed and a plurality of ICs are cascade-connected to the wirings, and among the input terminals of the plurality of ICs, at least one type of terminal inputting a common input signal is A board to which an IC is connected, characterized by being electrically connected in series by wiring.
JP34400089A 1989-12-29 1989-12-29 Substrate connected with ic Pending JPH03204946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34400089A JPH03204946A (en) 1989-12-29 1989-12-29 Substrate connected with ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34400089A JPH03204946A (en) 1989-12-29 1989-12-29 Substrate connected with ic

Publications (1)

Publication Number Publication Date
JPH03204946A true JPH03204946A (en) 1991-09-06

Family

ID=18365885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34400089A Pending JPH03204946A (en) 1989-12-29 1989-12-29 Substrate connected with ic

Country Status (1)

Country Link
JP (1) JPH03204946A (en)

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