JPH03203718A - Display controller for ferroelectric liquid crystal panel - Google Patents

Abstract

PURPOSE:To shorten response time and to obtain stable images by selecting only the predetermined scanning electrodes of the scanning electrodes which are the same in display data of the next frame in the next frame and setting the memory state of a ferroelectric liquid crystal panel in such a manner that the stabler memory state is the 'bright' display state of picture elements. CONSTITUTION:The above-mentioned controller is so constituted that selection voltages are impressed only to the predetermined number (p) of the scanning electrodes per frame among the remaining (m-q)-pieces of the scanning electrodes having no difference in the display data if the number of the scanning electrodes having a difference between the display data currently displayed by the picture elements on m-pieces of the scanning electrodes and the display data to be displayed in the next frame. Rewriting dark voltages are impressed as signal voltages to the picture elements having the continued dark display state which is unstable writing state among the picture elements on the selected scanning electrodes and non-rewriting voltages are impressed as signal voltages to the picture elements of the continued bright state which is a stable writing state. The frame period is shortened in this way and the stable images free from flickering are obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display control device for a ferroelectric liquid crystal panel (hereinafter also abbreviated as FLCD).

BACKGROUND ART FIG. 16 is a block diagram schematically showing a typical conventional configuration of a display system using FLCD1. This display system uses digital signals output from the personal computer 2 to the cathode ray tube 3 that performs pixel display as signals necessary for image display. The digital signal output from the personal computer 2 is converted by another control circuit 4, and an image is displayed on the FLCD 1 based on the converted signal.

FIG. 17 is a sectional view showing a schematic configuration of the FLCDI. Two glass substrates 5a and 5b are arranged to face each other, and a plurality of signal electrodes S made of indium tin oxide (hereinafter abbreviated as ITO) are arranged in parallel to each other on the surface of one of the glass substrates 5a. The top thereof is covered with a transparent insulating film 6a made of 5102.

On the surface of the other glass substrate 5b facing the signal electrodes S, a plurality of scanning electrodes made of ITO are arranged in parallel to each other in a direction perpendicular to the signal electrodes S.
It is covered with an insulating film 6b made of iO□. On each insulating film 6a, 6b, alignment films 7a, 7b made of polyvinyl alcohol, which have been subjected to a rubbing treatment, are formed, respectively. These two glass substrates 5a and 5b are bonded together with a sealant 8, leaving an injection port in a part, and a ferroelectric liquid crystal 9 is injected from the injection port into the space sandwiched between the alignment films 7a and 7b by vacuum injection. After being introduced, the inlet is filled with sealant 8.
is sealed. The two glass substrates 5a and 5b bonded together in this manner are sandwiched between two deflection plates 10a10b whose deflection axes are orthogonal to each other.

Figure 18 shows the above-mentioned FLCDI with simple matrix configuration.
FIG. 2 is a plan view showing a configuration in which a scanning side drive circuit 11 is connected to the scanning electrode and a signal side drive port B 12 is connected to the signal electrode S. The scanning side drive circuit 11 is a circuit for applying a voltage to the scanning electrodes, and the signal side drive circuit 12 is a circuit for applying a voltage to the signal electrodes S. In order to simplify the explanation, the case where there are 32 scanning electrodes IL and 16 signal electrodes S, that is, an FLCDI consisting of 32×16 pixels, is shown here, and each scanning electrode has a code. Each signal electrode S is distinguished by adding a subscript i (i=1 to 32) to the signal electrode S.
(j=1 to 16) is added for distinction. In the following explanation, any scan electrode Li and any signal electrode Sj
Let Aij represent the pixels at the intersection.

FIG. 19 is a waveform diagram showing each signal output from the personal computer 2 described above, of which FIG. 19 (1) is a horizontal synchronizing signal HD that gives the timing of one scanning section of the screen of the cathode ray tube 3; FIG. 19 (2) is the vertical synchronizing signal VD showing the period for one screen, and the first
FIG. 9 (3) shows image display data Data. 19th
Figure (4) is a waveform diagram showing an enlarged view of one scanning section of the horizontal synchronization signal HD, and Figure 19 (5) is a waveform diagram showing the above display data Da.
1 is a waveform diagram showing an enlarged view of one scanning section of ta;
FIG. 9 (6) is a waveform diagram showing the data transfer lock CLK of one pixel worth of display data Data.

FIG. 20 is a waveform diagram showing each signal output from the control circuit 4 described above, of which FIG. 20 (1)
20(2) is a waveform diagram showing a clock YCLK for sequentially transferring a selection signal Yl for selecting a scanning electrode in a shift register (not shown) included in the scanning side drive circuit 11, and FIG. FIG. 20 (3) shows display data DATA corresponding to each pixel of FLCDI. FIG. 20 (4) is a waveform diagram showing an enlarged view of one cycle of the clock YCLK,
FIG. 20 (5) shows the clock YCLK of the selection signal YI.
FIG. 20 is a waveform diagram showing an enlarged waveform corresponding to I period (
6) is a waveform diagram showing an enlarged waveform corresponding to the clock YCLKI cycle of the display data DATA, and FIG.
is a waveform diagram showing a display data transfer lock XCLK for sequentially transferring the display data DATA in a shift register (not shown) included in the signal side drive circuit 12, and FIG. FIG. 20 (9) is an enlarged waveform diagram of the latch pulse LP that provides the timing to take in and hold the display data DATA in the shift register in another register (not shown) included in the same signal side drive circuit 12, and FIG. FIG. 20 is a waveform diagram showing a signal VC specifying the type of voltage applied to the chamber ML, and FIG. 20 (10) is a waveform diagram showing a signal VS specifying the type of voltage applied to the signal electrode S.

In this way, the control circuit 4 receives four types of signals shown in FIG. 19, namely, horizontal synchronization signal HD, vertical synchronization signal VD, display data Data, and data transfer lock CLK.
The seven types of signals shown in FIG. 20, that is, the clock YCL
K, selection signal Y■, display data DATA, display data transfer lock XcLK, latch pulse LP, signals vc, v
A function is provided to convert it to s.

FIG. 21 is a waveform diagram showing voltage waveforms applied to the scanning electrode and signal electrode S used in the FLCDI driving method proposed in Japanese Patent Application Laid-Open No. 64-59389. Among them, the waveform shown in FIG. 21 (1) is the waveform of the selection voltage A that is applied to the scanning electrode and can specify rewriting of the memory state of the pixel on the scanning electrode, that is, the displayed brightness state. The waveform shown in FIG. 21 (2) is a waveform of a non-selection voltage B that is applied to the scanning electrode, but cannot specify rewriting of the display state of the pixel on the scanning electrode. The waveform shown in FIG. 21 (3) is the waveform of the rewriting bright voltage C applied to the signal electrode S when rewriting the pixel to the "bright" luminance state, and the waveform shown in FIG. 21 (4) is This is the waveform of the rewriting dark voltage applied to the signal electrode S when rewriting the pixel to the "dark" luminance state, and the waveform shown in FIG. 21 (5) is the waveform of the signal electrode S when the pixel display state is not rewritten. S
This is the waveform of the non-rewriting voltage G applied to. Figure 21 (
6) to (11) show the waveforms of the effective voltage applied to the pixel Aij, among which waveforms A to C in FIG. Figure 21 (7) shows the waveform when C is applied.
) shows the waveform when the selection voltage A is applied to the scanning chamber 8iLi and the rewrite dark voltage is applied to the signal electrode Sj, and the waveforms A-G in FIG.
The waveform shown is when the selection voltage A is applied to the scanning electrode Li, and the non-rewriting voltage G is applied to the signal electrode Sj, and the waveform B-C in FIG. The waveforms A-D in FIG. 21 (10) show the waveforms when the rewriting bright voltage C is applied to the signal electrode Sj, and the waveforms A-D in FIG. Figure 21 (11) shows the waveform when - is applied.
The waveform B-G shows the waveform when the non-selection voltage B is applied to the scanning electrode Li and the non-rewriting voltage G is applied to the signal electrode Sj.

By the above driving method, pixel A1 of FLCDI in FIG.
When the display state of j is rewritten, the selection voltage A shown in FIG. 21(1) is applied to the scan electrode Li, and the selection voltage A shown in FIG. figure(
When the non-selection voltage B shown in 2) is applied and the pixel Aij is rewritten to the "bright" display state, the rewriting bright voltage C shown in FIG. 21 (3) is applied to the signal electrode Sj, and the pixel A
When pixel Alj is rewritten to the "dark" display state, a rewriting dark voltage shown in FIG. 21 (5) is applied to the signal electrode Sj.

For example, in the FLCDI shown in FIG. 18, the state in which the word "extortion" is displayed on the screen by each pixel Aij in the "dark" display state indicated by diagonal lines is called "extortion" as shown in FIG. When rewriting the state in which characters are displayed, the pixel Aij that is rewritten from the "dark" display state to the "bright" display state is associated with the rewriting bright voltage C and is represented by the symbol C, and the "bright" display is The pixel A1j that is rewritten from the state to the "dark" display state is represented by a code in association with the rewritten dark voltage, and the pixel Aij that remains in the "dark" display state is represented by the code F, and the pixel Aij that remains in the "dark" display state is represented by the code F, and the pixel Aij that remains in the "dark" display state is represented by the code F. Pixel Ai that remains in the state
When is expressed without a symbol, the entire screen is displayed as shown in FIG. In this case, the pixel Aij with symbol F and the pixel Aij with no symbol correspond to the non-rewriting voltage G.

FIG. 24 shows the scanning electrodes Ll, L2 . L3, signal electrode S5. S6 and pixel A15. A16, A25. A
26 shows respective voltage waveforms applied thereto. For reference, FIG. 24 (1) shows the scanning side drive circuit 11.
24(2) shows the waveform of the transfer clock YCLK of the selection signal YI in the shift register, and FIG. 24(2) shows the waveform of the selection signal Y■. FIG. 24(3) shows the scanning electrode L1
FIG. 24 (4) shows the voltage waveform applied to the scanning electrode L.
24 (5) shows the voltage waveform applied to the scanning electrode L3, FIG. 24 (6) shows the voltage waveform applied to the signal electrode S5, and FIG. ) shows the voltage waveform applied to the signal electrode S6, FIG. 24(8) shows the effective voltage waveform applied to the pixel A15, and FIG.
9) shows the effective voltage waveform applied to pixel A16, FIG. 24 (10) shows the effective voltage waveform applied to pixels A and 25, and FIG. 24 (11) shows the effective voltage waveform applied to pixel A26. Shows voltage waveform.

In the above driving method, the pixel A shown in FIG. 24 (9)
16 effective voltage and pixel A2 shown in FIG. 24 (11)
As can be seen from the effective voltage No. 6, the voltage applied to the pixel Aij is almost the same whether or not the scanning electrode Li is selected unless its display state is rewritten. From this, the time from when the selection voltage A is applied to a certain scan electrode Li until the selection voltage A is applied to the same scan electrode 8iLi, that is, the period of one frame is 33.3ms (30
Even in the case of low-speed driving longer than Hz (equivalent to Hz), display without flickering is possible.

Problems to be Solved by the Invention By the way, in the case of the ferroelectric liquid crystal that is currently commonly used in FLCDI, if one with a breakdown voltage of 24V is used as the scanning side drive circuit 11 and the signal side drive circuit 12, for example, It is necessary to set the unit pulse width 10 of each applied voltage shown in FIG. 21 to about 50 μs, and when the above-described driving method is adopted, it is necessary to allocate about 300 μs as one selection time (6 tO). Therefore,
Under these conditions, an FLC with 1000 scanning electrodes
If DI is driven, one frame period in this case is 0.3 ms.

However, this means that it takes 0.3 seconds after the user inputs something from the keyboard until the screen display is rewritten.
This means that it takes more than ms, and even though flicker-free display can be achieved as mentioned above, the problem is that the number of scanning electrodes must be limited due to the limit of response speed. Has a point.

In addition, it is extremely difficult to obtain a completely bistable memory state in FLCDs, and one memory state tends to be more stable than the other, so if a bias voltage is continuously applied, all pixels attempts to reach the stable memory state. Because of this tendency of FLCD, as mentioned above, in order to keep a pixel in a "bright" or "dark" display state in a "bright" or "dark" display state, it is necessary to use a non-signal voltage as described above. If the rewrite voltage G is continuously applied, there is also a problem that pixels in an unstable display state in a memory state change to a display state in a stable memory state.

Therefore, an object of the present invention is to provide a display control device for a ferroelectric liquid crystal panel that can shorten the frame period regardless of the number of scanning electrodes and can obtain stable images without flicker. be.

Means for Solving the Problems The present invention provides a method in which a ferroelectric liquid crystal is interposed between a plurality of scanning electrodes and a plurality of signal electrodes arranged in directions crossing each other,
The ferroelectric liquid crystal at the intersection of the scanning electrode and the signal electrode is used as a pixel, and the signal electrode has a rewriting bright voltage for rewriting the pixel from a dark display state to a bright display state as a signal voltage corresponding to display data. Then, either a rewriting dark voltage for rewriting the bright display state to a dark display state or a non-rewriting voltage for not rewriting the display state is applied to the scanning electrode, and the display of the pixel on that electrode is applied to the scanning electrode. A selection voltage for specifying state rewriting is applied line-sequentially, and until the selection voltage is applied again to the same scan electrode one frame later, the pixel is changed at the timing when the selection voltage is applied to other scan electrodes. In a display control device for a ferroelectric liquid crystal panel that repeatedly applies a non-selection voltage that does not specify rewriting of the display state and is set so that the bright display writing state of the pixel display state is stable, the following is applied. A display data frame memory for storing display data for one screen to be displayed in each pixel in a frame, and a difference between the currently displayed display data and the display data stored in the frame memory. A same/different reference frame memory that stores same/different identification data for one screen; and same/different reference frame memory that is associated with each of the scanning electrodes and corresponds to a pixel on the scanning electrode. a line memory that stores line identity identification data indicating whether or not there is data indicating that there is even one difference between the lines; The line identity identification data of the corresponding line memory is checked line by line, and if the data indicates that the line identity identity data is different, it is decided to apply a selection voltage to the corresponding scanning electrode, and the line identity identification data is determined to be applied to the corresponding scanning electrode. A scan electrode selection means that decides to apply a selection voltage to a predetermined scan electrode for each frame if no data indicating that the data is different is found; Among them, a rewriting dark voltage is applied to pixels whose current display state is a bright display state and will be a dark display state in the next frame, and a rewrite dark voltage is applied to pixels whose current display state is a dark display state and will be a bright display state in the next frame. is the rewriting bright voltage, and the rewriting dark voltage is applied to pixels whose current display state is a dark display state and will be in a dark display state in the next frame. Scanning electrodes are selected based on the display data in the frame memory for display data and the same/different identification data in the same/different reference frame memory. 1. A display control device for a ferroelectric liquid crystal panel, comprising display data output means for providing display data to a signal electrode side of a ferroelectric liquid crystal panel in synchronization with the ferroelectric liquid crystal panel.

According to the present invention, in the case of a ferroelectric liquid crystal panel having m scanning electrodes, there is a difference between the display data currently displayed by the pixels on the scanning electrodes and the display data to be displayed in the next frame. Assuming that the number of scanning electrodes is q, the selection voltage is applied only to a predetermined number of scanning electrodes for each frame for the remaining m-q> scanning electrodes that have no difference in display data. Therefore, if the remaining number of scan electrodes to be selected is p, then (mq-p
) The application of a selection voltage to the main scanning electrodes can be omitted, and the frame period can be significantly shortened.

In addition, for pixels on the selected scanning electrode that continue to display a dark state with poor write state stability, the rewrite dark voltage is applied as a signal voltage and is refreshed, thereby stabilizing the screen and stabilizing the write state. For pixels that remain in a bright display state, a non-rewriting voltage is applied as a signal voltage, so flicker is reduced.

Embodiment FIG. 1 is a block diagram showing the configuration of a display system to which a display control device for a ferroelectric liquid crystal panel, which is an embodiment of the present invention, is applied. The configuration of this display system is roughly the same as that of the conventional display system described above, and the signals necessary for image display are output as digital signals from the personal computer 22 to the cathode ray tube 23 that performs pixel display. use. A digital signal outputted from the personal computer 22 is converted by a control circuit 24 which is a display control device of this embodiment, and an image is displayed on the FLCD 21 based on the converted signal.

In the above FLCD 21, the polarization axis of the polarizing plate is set so that the pixels are in a bright display state in a more stable memory state of the ferroelectric liquid crystal panel. Other specific configurations are the same as those of the conventional FLCD1 shown in FIG. 17, so a description thereof will be omitted here. In this example, ZLI-42371 manufactured by Merck & Co., Ltd. was used as the ferroelectric liquid crystal of FLCD21.
000 is used, and polyimide is used as the alignment film.

FIG. 2 is a block diagram schematically showing the configuration of the control circuit 24. As shown in FIG. Display data frame memory 2
5 is 1 sent from the personal computer 22.
This is a memory for holding display data Data for a screen. From this display data frame memory 25, the display data currently displayed on the screen of the FLCD 21,
Converted data Rx indicating the same or different from the display data to be displayed in the next frame is output.

Based on the conversion data Rx output from the display data frame memory 25, the line memory 26 converts the FLCD
For each pixel on each of the 21 scanning electrodes, line identity identification data SAME indicating whether or not there is even one pixel in which there is a difference between display data currently displayed and display data displayed in the next frame is transmitted to each pixel. This is a memory for holding on the scanning electrode side. In this line memory 26, a storage area of 1 bit is allocated to each scanning electrode to hold line identification data SAME for each scanning electrode.

The reference frame memory 27 stores conversion data Rx for one screen output from the display data frame memory 25.
It is a memory for holding.

The input control circuit 28 controls the display data frame memory 25 based on the horizontal synchronization signal HD, vertical synchronization signal VD, and clock CLK sent from the personal computer 22 and the signals OW, OAc, and OAs sent from the two output control circuits. , a circuit for controlling data writing to the line memory 26 and the reference frame memory 27.

The two output control circuits are frame memories 25 for display data.
, a circuit for reading held data from the line memory 26 and the reference frame memory 27 and controlling the output of the drive control circuit 30.

The drive control circuit 30 includes a frame memory 25 for display data.
The data DO given from the reference frame memory 2
Based on the data DRE given from 7, FLCD2
This is a circuit for outputting a signal for controlling the display drive of No. 1.

FIG. 3 shows the FLCD 21 with the above-mentioned simple matrix configuration.
3 is a diagram showing a configuration in which a scanning side drive circuit 31 is connected to the scanning electrode and a signal side drive circuit 32 is connected to the signal electrode S. FIG. The scanning side drive circuit 31 is a circuit for applying voltage to the scanning electrodes, and the signal side drive circuit 32 is a circuit for applying voltage to the scanning electrodes S.
This is a circuit for applying voltage to. Here, as in the case of the conventional example, for the sake of simplicity, the number of scanning electrodes is 3.
The case where there are two signal electrodes S and 16 signal electrodes S is shown for the FLCD 21 which is composed of exactly 32 x 16 pixels, and each scanning type IL has a subscript i (i
= l to 32) to distinguish them, and each of the signal electrodes S is distinguished by adding a subscript j (j = 1 to 16) to the code S. Also, in the following description, as in the case of the description of the conventional example, a pixel at a portion where an arbitrary scanning electrode L1 and an arbitrary signal electric field isj intersect will be represented by the symbol Aij.

FIG. 4 shows a state in which the word "extortion" is displayed as shown in FIG. 17 in the explanation of the conventional example, but as shown in FIG. ” is a diagram schematically showing one screen worth of conversion data Rx held in the reference frame memory 27 displayed on the screen of the FLCD 21 when the screen of the FLCD 21 is switched to a state where the characters “” are displayed. It is. A shaded pixel indicates that the conversion data Rx of that pixel is data that indicates that there is a difference between the currently displayed display data and the display data that will be displayed in the next frame. ing.

5 and 6 are waveform diagrams showing each output signal sent from the control circuit 24 to the FLCD 21 during the screen switching operation, of which FIG. 5 (1) and FIG. 6 (1) are for scanning. 5(2) and FIG. 6(2); FIG. is a waveform chart showing the selection signal YI, and FIGS. 5(3) and 6(3) show display data DATA corresponding to each pixel of the FLCD 21, and FIGS. 5(4) and 6( 4
) is the scan side drive circuit 31 for each selection time of the scan electrode.
FIG. 2 is a waveform diagram showing a clock signal CLK given to FIG. FIG. 5 (5) is an enlarged waveform diagram showing one cycle of the clock YCLK, and FIG. 5 (6) is a waveform diagram showing the selection signal YI
FIG. 5(7) is an enlarged waveform diagram showing the clock YCLKI period equivalent of the display data DATA, and FIG. 5(8) is a waveform diagram showing the clock YCLKI period equivalent of the display data DATA. 5(9) is a waveform diagram showing a data transfer lock XCLK for sequentially transferring the display data DATA in a shift register (not shown) included in the signal side drive circuit 32; FIG.
A latch pulse L that provides timing for taking in and holding the display data DATA in the shift register in another register (not shown) included in the same signal side drive circuit 32.
FIG. 5 (10) is a waveform diagram showing the signal VC specifying the type of voltage applied to the scanning electrode S, and FIG. 5 (11) is a waveform diagram showing the voltage applied to the signal electrode S. FIG. 3 is a waveform diagram showing a signal VS specifying the type of the signal VS. In addition, the 6th
Figures (1) to (4) show waveforms following the waveforms in Figures 5 (1) to (4).

FIG. 7 is a waveform diagram showing each signal output from the input control circuit 28 during the above operation. Among them, FIG. 7(1) shows the waveform of the input side clock l5CP, which is obtained by delaying the data transfer lock CLK output from the personal computer 22 by a certain period of time, and FIG.
Timing pulse RE for converting ata into parallel
FIG. 7(3) shows the waveform of the display data frame memory 25. which is associated with the scanning electrode. line memory 2
6 and the row address Ac of the reference frame memory 27, and FIG. 7(4) shows the data of the column address As of the display data frame memory 25 and reference frame memory 27 associated with the signal electrode S , 7th
Figure (5) shows the waveform of the timing pulse IOE for reading data from the display data frame memory 25, line memory 26, and reference frame memory 27 on the input side in synchronization with the clock l5CP. )
shows the waveform of the timing pulse IWE for writing data to the display data frame memory 25, line memory 26, and reference frame memory 27 on the input side in synchronization with the clock l5CP, and FIG. reference frame memory 25 and reference frame memory 2
7 (8) shows the waveform of the timing pulse OOE for reading data from the output side of the clock l.
7(9) also shows the waveform of a timing pulse RWE sent out to the line memory 26 in synchronization with clock l5CP.

Further, FIG. 8 is a waveform diagram showing each signal output from the output control circuit 29 during the above operation. Of these, FIG. 8 (1) shows a waveform diagram of the clock CP on the output side, and FIG. The waveform of the timing pulse LO for serially converting these transmitted data is shown in Figure 8 (3).
) is the line identity identification data SAME given to the two output control circuits from the line memory 26 shown for reference, and (4) in FIG. 8 shows the timing pulse OW synchronized with the clock CP. 5) shows the output side row address OAc of the display data frame memory 25, line memory 26 and reference frame memory 27, and FIG. 8(6) shows the display data frame memory 25 and the reference frame memory 27. The output side column addresses OAs of these memories given to the frame memory 27 are shown, and FIG. 8 (7) shows the clock YC given to the scanning side drive circuit 31.
FIG. 8 (8) is a waveform diagram showing the timing pulse HCE for generating LK in the drive control circuit 30, and FIG. Timing pulse HP for generating applied voltage in drive control circuit 30
FIG. 8 (9) is a waveform diagram showing the scanning side drive circuit 3.
1 is a waveform diagram showing a timing pulse VP for causing the drive control circuit 30 to generate a selection signal YI to be applied to the drive control circuit 30. FIG.

FIG. 9 shows that scanning electrode L1. L2. L3, signal electrode S5. S6 and pixel A15. A16A25. A26
The voltage waveforms applied to each are shown. One of these days,
For reference, FIG. 9(1) shows the transfer lock YC of the selection signal YI in the shift register in the scanning side drive circuit 31.
9(2) shows the waveform of the selection signal YI, and FIG. 9(3) shows the waveform of the clock LCLK which provides the timing of one selection time. FIG. 9(4) shows the voltage waveform applied to the scanning electrode L1, FIG. 9(5) shows the voltage waveform applied to the scanning electrode L2, and FIG. 9(6) shows the voltage applied to the scanning electrode L3. FIG. 9 (7) shows the voltage waveform applied to the signal electrode S5, FIG. 9 (8) shows the voltage waveform applied to the signal electrode S6, and FIG. 9 (9) shows the voltage waveform applied to the signal electrode S6. The applied effective voltage waveform is shown in Figure 9 (
10) shows the effective voltage waveform applied to pixel A16,
FIG. 9 (11) shows the effective voltage waveform applied to the pixel A25, and FIG. 9 (12) shows the effective voltage waveform applied to the pixel A26.
is currently displayed in "dark" state and will be displayed in the same "dark" state in the next frame.
The symbol G (E) is the signal voltage applied to the pixel that is currently in the "bright" display state and will be displayed in the same "bright" state in the next frame. The non-rewriting voltage G applied as
Other symbols indicate the respective applied voltages in FIG. 20 shown in the description of the conventional example.

Next, when the FLCD 21 in the above display system is driven by the driving method using the applied voltage shown in FIG. The operation when the display is switched to the state in which the characters ``are displayed'' will be explained with reference to FIGS. However, one selection time (6tO) in this case is approximately 600 μs.

In the frame in which the word "extortion" is displayed on the screen of the FLCD 21, the display data Data held in the display data frame memory 25 is in the state shown in FIG. 18 in the description of the conventional example.

Under this condition, from the personal computer 22,
Display data Data for displaying the characters ``Regular invitation'' is transmitted to the display data frame memory 25. Then, from the display data frame memory 25, one screen worth of conversion data Rx, as schematically shown in FIG. sent to. The conversion data Rx is retained as it is in the reference frame memory 27, but
In the line memory 26, the converted data Rx for one scanning electrode is collected and held as one. In other words, if we explain according to Fig. 4, if even one pixel on one scanning electrode is displayed as "dark", that is, there is a pixel with different display data in the previous and subsequent frames, then the line is the same. “1” is retained as the identification data SAME, and even one pixel is “dark”.
If there is no pixel represented by the display, "0" is held.

The above operations are controlled by the input control circuit 28.

That is, the input control circuit 28 is initialized by the horizontal synchronization signal HD and vertical synchronization signal VD sent from the personal computer 22, and generates a clock l5CP that is delayed by a certain period of time from the data transfer lock CLK also sent from the personal computer 22. This clock l5CP as a clock and a timing pulse RE for parallel converting the display data Data are sent to the display data frame memory 25. In addition, in synchronization with the clock l5CP, a timing pulse IOE for reading data from the memory 2526.27, a timing pulse IWE for writing data to the memory 25.26°27, and access to each memory 25, 26.27. Address data obtained by switching the output-side row address OAc and the input-side row address OAc of these memories is outputted from the input control circuit 28 as the row address Ac. Furthermore, the input control circuit 28 outputs a timing pulse OOE for reading data from each memory 25, 27 in synchronization with the clock CP output from the output control circuit 29, and a column address A for accessing these memories.
Address data obtained by switching the column address OAs for the output side and the column address OAs for the input side of each memory is also output as s.

Next, the data Do held in the display data frame memory 25 and the data DRE held in the reference frame memory 27 are sent to the drive control circuit 30.

At this time, the data transfer time T1 required to actually output the data DO and DRE is set sufficiently smaller than one selection time (6tO), and before entering the data transfer time T1, the two output control circuits The line identity identification data SAME in the line memory 26 corresponding to the electrode is confirmed. At this time, the line identity identification data 5AVE is “
If the state "O" continues, the operation of checking the line identity identification data SAME corresponding to the next scanning electrode is repeated many times, and the line corresponding to the scanning electrode determined in advance for each frame is checked. When it is your turn to confirm the same/different identification data SAME, the line same/different identification data SAME
When E is r□, data Do and DRE corresponding to the scanning electrode are sent from the display data frame memory 25 and the reference frame memory 27 to the drive control circuit 30 regardless of whether it is "1" or not. . If the line identity identification data SAME becomes "1" before the designated scan electrode is checked, the data Do corresponding to that scan electrode
, DRE are sent to the drive control circuit 30. Further, in the line memory 26, after the line same/different identification data SAME is output, the contents of the line same/different identification data SAME corresponding to the scanning electrode are reset to "0". In this way, when the line identity identification data SAME corresponding to the last scan electrode L32 of one screen has been confirmed, the scan electrode to be selected in the next frame is determined at this point. The scan electrodes that are determined to be selected in advance are determined so as to cover all the scan electrodes of one screen over a plurality of frames.

The series of operations described above is controlled by the timing pulse OW output from the output control circuit 29 and the timing pulses ROE and RWE sent from the input control circuit 28 to the line memory 26 and the frame memory for display data from the output control circuit 29. 25, timing pulse L○ sent to line memory 26 and reference frame memory 27
This is done by

Thereafter, when the personal computer 22 continues to send the display data Data of the regular visitor J to the display data frame memory 25, the display data frame memory 25
will continue to hold the data for displaying the characters ``commonly attracted'', but all of the conversion data RX output from the display data frame memory 25 will be ``0'' and ``0'' corresponding to the pixels that are not shaded in FIG. Become. The conversion data Rx is sent to the line memory 26 and reference frame memory 27, but regarding the data held in the reference frame memory 27, the line identity identification data SA of the line memory 26
Unless ME becomes "O", the data on the corresponding scanning electrode is not rewritten to "0".

Further, the output control circuit 29 supplies a timing pulse VP to the drive control circuit 30 for generating a selection signal YI to be input to the scanning drive circuit 31.
1, the clock LCLK input to the scanning side drive circuit 31, the latch pulse LP given to the signal side drive circuit 32, and the timing pulse HP for generating each applied voltage, respectively. Output.

As a result of the above operations, the FLCD from the control circuit 24
21, each signal shown in FIGS. 5 and 6 is output. That is, if scan electrodes Ll, L5 to L29 are scan electrodes that have been determined to be selected in advance in the currently displayed frame, scan electrodes L17 to L29
is selected, the display data frame memory 25
The display data held in the display changes from the character display of "Extortion" to the character display of "Perpetual invitation", and the data in the reference frame memory 27 becomes as schematically shown in FIG. Also, the line identity identification data SA in the line memory 26
ME is "1" for scan electrodes L1 to L16, and "0" for scan electrodes L17 to L32.

Now, in the next frame, scan electrode L4. Assuming that L8 to L32 are scan electrodes determined to be selected in advance, display starts from the scan electrode ILL, and first the output control circuit 29
, the row address 0Ac=1 is input to each memory 25.2627 via the input control circuit 28, and at this time, the line identity identification data SAME of the line memory 26 becomes "1", and the display data frame corresponding to the scanning electrode L1 Data DO in memory 25 and data DRE in reference frame memory 27 are transferred to drive control circuit 30.

The above operation is repeated for scanning electrodes L2 to L16.

Next, the row address ○Ac=17 is sent from the output control circuit 29.
is sent to each memory 25, 26, and 27, the line identity identification data SAME of the line memory 26 becomes "0", and the row address OAc output from the output control circuit 29 is increased by 1 and switched to 18. . The line same/different identification data SAME continues with “0”, but the address OA
When C reaches 20, that is, when the scan electrodes L20 are selected in the predetermined order, the data Do of the display data frame memory 25 and the data DRE of the reference frame memory 27 corresponding to the scan electrodes 1i:L20 are transferred to the drive control circuit. Transferred to 3o. Thereafter, similar operations are repeated, and when the last scan electrode L32 is selected, in the next frame, scan electrode L3. L7 to L31 are determined as scan electrodes to be selected in advance.

At this time, scanning electrodes Ll, L2. L3, signal electrode S5.
S6 and pixel A15. A16. The voltages applied to A25A26 are as shown in FIG.

In this case, for example, pixel A2 on scan electrode L2 to be selected
6 has a "dark" display in the previous frame and the same "dark" display in the subsequent frame, but the signal voltage applied to this pixel A26 in the subsequent frame is the rewriting dark voltage. In other words, "dark" display pixels whose memory state is less stable are always refreshed. On the other hand, the signal voltage of the non-rewriting voltage G is applied in the subsequent frame to pixels that continue to display "bright" in the previous and subsequent frames, as in the case of the conventional example. As mentioned at the beginning, in this case FLCD2
In 1, the memory state of the pixels in the "bright" display is set to be more stable, so the pixels in the "bright" display, which are not refreshed in this way, are displayed in the "dark" state while the same display continues. There is no such thing as changing to. Therefore, for pixels that continue to display "bright", flicker is reduced by the amount that is not rewritten.

Also, in the case of a pixel that continues to be rewritten as a "dark" display, for example, in a display such as a word processor that displays black characters on a white background, the pixel that is in the "dark" display will receive light for a moment during rewriting. Even if the light leaks out, the light is obscured by the many bright pixels around it, so the human eye does not notice much of this optical change, and even if the pixels in the "dark" display state are refreshed, flickering will occur. It doesn't matter.

Furthermore, in this embodiment, for scan electrodes in which there is no pixel in which there is a difference between the currently displayed display data and the display data to be displayed in the next frame, even if these scan electrodes continue, the next frame Since only predetermined scan electrodes are selected from among those scan electrodes,
The apparent period of the frame is shortened by the number of scan electrodes whose selection is omitted.

However, for example, on the display screen of a personal computer, it is rare that the entire screen is rewritten at once, and depending on the ingenuity of the program, the number of scan electrodes on which display data changes can be considerably reduced. In particular, in the case of a word processor, display data is input for each character, so it is rare for several lines of characters to be rewritten at once.If one screen corresponds to one page, the display data per screen is The number of scanning electrodes that need to be rewritten is very small, about one line of characters.Therefore, when the above display control device is used to control the display of such personal computers and word processors, the frame period is significantly reduced. This shortens the time and speeds up the response time until the screen is rewritten in response to input.

In the above embodiment, in order to simplify the explanation, the display was performed on the FLCD 21 with 16×32 pixels.
When the above embodiment was actually applied to an FLCD with 1024 x t024 pixels, it was confirmed that flicker was not noticeable and a display with a fast response speed could be obtained.

By the way, in the display method applied to the above embodiment, that is, the display method using the applied voltages of each waveform in FIG. 21 shown in the explanation of the conventional example, as is clear from the waveform diagram shown in FIG. 32 requires three types of applied voltages: rewriting bright voltage C, rewriting dark voltage D, and non-rewriting voltage G, so the manufacturing process is easier compared to the signal side drive circuit which requires only two types of applied voltage. This will result in high costs.

However, if you look closely at the waveforms in Figure 21, the first half of the non-rewriting voltage G corresponds to the first half of the rewriting dark voltage, and the second half of the non-rewriting voltage G corresponds to the second half of the rewriting bright voltage C. It turns out that they are equal. Therefore, focusing on this point, the signal value for specifying the applied voltage given to the signal side drive circuit 32 is such that the first half of the signal value has the same value as the rewrite dark voltage G and the non-rewrite voltage G, and the second half has the same value as the rewrite dark voltage G. If the voltage C and the non-rewriting voltage G are determined to have the same value, the cost required for the signal side drive circuit 32 can be reduced.

Specific examples of circuits constituting each part of the control circuit 24, which are constructed in consideration of such points, are shown in FIGS. 10 to 13, respectively. Of these, FIG. 10 shows the output control circuit 29, which includes six counters 33a to 33.
f, three D flip-flops 34a to 34c, and 6
one NAND gate 35a-35f, two AND gates 36a, 36b, and four NOR gates 37a-3
7d, three OR gates 38a to 38C, and five D
It is composed of IR switches 39a to 39e.

FIG. 11 also shows the display data frame memory 25, which includes eight NOTOR gates 41a to 41h, eight EX-OR gates 41a to 41h, and two latch-equipped shift registers 42a.

42b, one 3-state output buffer 43, one shift register 44, and one static RAM (
Random Access Memory>45
, two D flip rollers 146a and 46b, five NAND gates 47a to 47e, four AND gates 48a to 48d, and one four switches.

FIG. 12 also shows the line memory 26, which includes one static RAM 50 and four NOT gates 51.
a to 51d, two 3-state output buffers 52a,
52b, four D flip-flops 53a to 53d, two NAND gates 54a and 54b, and ten A
It is composed of ND gates 55a to 55j.

Further, FIG. 13 shows a reference frame memory 27,
NOT gates 56a to 56g, one static RAM 57, and two D crimp flops 58a, 5
8b, one five 3-state output buffers, one shift register 60, and eleven NAND gates 61a.
to 61, four AND gates 62a to 62d, and 8
OR gates 63a to 63h.

FIG. 14 is a block diagram showing a schematic configuration of a display control device for a ferroelectric liquid crystal panel according to another embodiment of the present invention. That is, the control circuit 74 shown as a display control device in this embodiment is the same as the control circuit 24 in the above embodiment, but the reference frame memory 27 is omitted.

The other configurations are the same as in the previous embodiment. However, the actual circuit configuration is the same as that of the previous embodiment, and the present invention is realized by simply setting the data DRE read from the reference frame memory 27 to be data indicating that there is a change.

FIG. 15 shows scan electrode L1. L2. L3. Signal electrode S5゜S6 and pixel A1
5. A16. A25. The respective voltage waveforms applied to A26 are shown. In addition, in FIG. 15, symbols A to BD
21 respectively show the applied voltages shown in FIG. 21 in the explanation of the conventional example.

In the case of this embodiment, as mentioned above, the data DRE always corresponds to the fact that the display states of pixels are different in the previous and subsequent frames, so not only the pixels that remain in the "dark" display state but also the "bright" display state are used. Refreshing will also be performed for pixels that continue to be displayed. However, the human eye cannot sense the instantaneous interruption of light when a pixel in a "bright" display state that is shining at a high frequency is rewritten using a low frequency, so flicker can be reduced considerably even in this case.

Effects of the Invention As described above, according to the display control device for a ferroelectric liquid crystal panel of the present invention, the display data of the pixels on the scanning electrode currently being displayed is the same as the display data in the next frame. Regarding the scan electrodes, the configuration is such that only the scan electrodes predetermined for each frame are selected in the next frame, so even in the case of a ferroelectric liquid crystal panel with a large number of scan electrodes, the scan electrodes selected in one frame are The frame period can be shortened by the reduction in the number of electrodes, and the response time from input to display on the screen can be correspondingly faster.

In addition, the more stable memory state of the ferroelectric liquid crystal panel is set so that the pixel is in the "bright" display state, and among the pixels that remain in the same display state over the previous and subsequent frames, the "dark" display continues. The pixel is refreshed by applying a rewriting dark voltage in the next frame, and the non-rewriting voltage is applied to pixels that continue to display "bright" in the subsequent frame, so the display is stable and flicker-free. Images can be displayed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a display system to which a display control device for a ferroelectric liquid crystal panel, which is an embodiment of the present invention, is applied, and FIG. 2 is a schematic diagram of a control circuit that is the display control device. Fig. 3 is a block diagram showing the ferroelectric liquid crystal panel that uses the control circuit to display the characters ``regular'', and Fig. 4 shows the conversion stored in the reference frame memory. A diagram schematically showing an example of data, FIGS. 5 and 6 are waveform diagrams showing the output signals of the control circuit, respectively, FIG. 7 is a waveform diagram showing the output signals of the input control circuit in the control circuit, and FIG. is a waveform diagram showing the output signal of the output control circuit in the control circuit, FIG. 9 is a waveform diagram showing each voltage applied to some scanning electrodes, signal electrodes, and pixels of the ferroelectric liquid crystal panel, and FIG. FIG. 11 is a circuit diagram showing an example of a specific configuration of the output control circuit, FIG. 11 is a circuit diagram showing an example of a specific configuration of the frame memory for display data in the control circuit, and FIG. 12 is a circuit diagram of the line memory in the control circuit. FIG. 13 is a circuit diagram showing an example of a specific configuration of the reference frame memory in the control circuit, and FIG. 14 is a schematic configuration of a control circuit according to another embodiment of the present invention. Fig. 15 is a waveform diagram showing the voltages applied to several scanning electrodes, signal electrodes, and pixels of a ferroelectric liquid crystal panel when the control circuit is used, and Fig. 16 is a conventional display. A block diagram showing a schematic configuration of a display system using a control device, FIG. 17 is a cross-sectional view showing the configuration of a ferroelectric liquid crystal panel used in the display system, and FIG. 18 is a cross-sectional view showing the configuration of a ferroelectric liquid crystal panel used in the display system. FIG. 19 is a waveform diagram showing the output signal from the personal computer in the display system; FIG.
Figure 0 is a waveform diagram showing the output signal from the control circuit in the display system, Figure 21 is a waveform diagram showing each applied voltage used in the orbit of the ferroelectric liquid crystal panel in the display system, and Figure 22 is the waveform diagram showing the voltage applied to the trajectory of the ferroelectric liquid crystal panel in the display system. A diagram showing the state in which the word "parallel dielectric" is displayed on a dielectric liquid crystal panel, FIG. 23 is a diagram showing the correspondence between the display state of the ferroelectric liquid crystal panel and the type of applied voltage, and FIG. FIG. 3 is a waveform diagram showing voltages applied to some scanning electrodes, signal electrodes, and pixels of a ferroelectric liquid crystal panel. 21... FLCD, 22... Personal computer, 24... Control circuit, 25... Frame memory for display data, 26... Line memory, 27...
...Reference frame memory, 28...Input control circuit,
29... Output control circuit, 30... Drive control circuit, 3
1... Scanning side drive circuit, 32... Signal side drive circuit,
L...scanning electrode, S...signal electrode Engraving of drawings (no changes in content) Fig. 1 Fig. 2 Fig. 14 Fig. 16 Fig. 17 (1) To YCL (2) 1 15 Fig. 1 21 Figure (1) How to write the procedure amendment in Figure 24 on YCL) % formula % 1. Indication of the case Patent application No. 1-342514 2. Name of the invention Display control device for ferroelectric liquid crystal panel 3. Case of the person making the amendment Relationship with Applicant Address 22-22 Nagaike-cho, Abeno-ku, Osaka Name (50
4) Sharp Corporation Representative: Haruo Tsuji 4, Agent address: 1-13-38 Nishihonmachi, Nishi-ku, Osaka Shinko Sangyo Building Country Equipment EX 0525-5985 INTAPT
J International FAX (06)538-0247 (Representative)
6. Drawings subject to amendment 7. Contents of amendment: Engraving of drawings (no change in content).

Claims (1)

[Claims] A ferroelectric liquid crystal is interposed between a plurality of scanning electrodes and a plurality of signal electrodes arranged in a direction crossing each other, and the ferroelectric liquid crystal is disposed at a portion where the scanning electrode and the signal electrode intersect. The signal electrode has a rewriting bright voltage for rewriting the pixel from a dark display state to a bright display state as a signal voltage corresponding to display data, and a rewriting bright voltage for rewriting the pixel from a bright display state to a dark display state. Either a rewriting dark voltage or a non-rewriting voltage for not rewriting the display state is applied, and a selection voltage for specifying rewriting of the display state of the pixel on that electrode is applied line sequentially to the scanning electrode. At the same time, until the selection voltage is applied again to the same scan electrode one frame later, a non-selection voltage that does not designate rewriting of the display state of the pixel is repeatedly applied at the timing when the selection voltage is applied to other scan electrodes. , and in a display control device for a ferroelectric liquid crystal panel that is set so that the writing state of bright display among the pixel display states is stable, one screen worth of display data to be displayed on each pixel in the next frame is stored. a display data frame memory for displaying data; and a same/difference reference frame for storing one screen's worth of same/difference identification data indicating the same/difference between the currently displayed display data and the display data stored in the frame memory. Indicates whether or not there is data indicating that there is at least one difference among the same/different identification data of the memory and the same/different reference frame memory that is associated with each of the scanning electrodes and corresponds to the pixel on the scanning electrode. While a selection voltage is being applied to the scan electrode, the line memory stores the line identity identification data, and while the selection voltage is applied to the scan electrode, the line identity identification data of the line memory corresponding to each scan electrode following the scan electrode is checked line by line; If the data indicates that the line identity discrimination data is different, it is decided to apply a selection voltage to the corresponding scanning electrode, and if no data indicating that the line identity discrimination data is different is found, it is determined in advance for each frame Among the pixels on the scan electrodes selected by the scan electrode selection means, the current display state is bright display state and the next frame is dark display state. A rewriting dark voltage is applied to pixels that will be in the display state of , a rewriting bright voltage is applied to pixels that are currently in a dark display state and will be in a bright display state in the next frame, and a rewriting bright voltage is applied to pixels that are in a dark display state and the next frame is in a bright display state. A rewrite dark voltage is applied as a signal voltage to pixels that are in a dark display state even in the next frame, and a non-rewrite voltage is applied as a signal voltage to pixels that are currently in a bright display state and will be in a bright display state in the next frame. Display control data that can be applied to the signal electrode side of the ferroelectric liquid crystal panel in synchronization with the selection of the scanning electrode based on the display data in the display data frame memory and the same/different identification data in the same/different reference frame memory. 1. A display control device for a ferroelectric liquid crystal panel, comprising: data output means.