JPH03201897A - Multi-junction system - Google Patents

Abstract

PURPOSE:To relieve the load of a time switch by using a communication of a transmission line interface so as to judge a connection request and its priority thereby connecting the transmission line. CONSTITUTION:Control means 211-2n1 of transmission line interfaces 21-2n extract an S bit sent from transmission lines 1-n. When a connection request to a data interface 10 is generated from one transmission line only, the transmission line is connected and when a connection requests comes from plural transmission lines, the priority of the transmission lines 1-n is judged and the transmission line with the highest priority is selected and connected.

Description

[Detailed Description of the Invention] [Summary] In a digital multiplex terminal device that multiplexes digital signals and communicates, regarding the multi-junction method in which communication is performed simultaneously with multiple parties, connection requests and priority are The purpose is to provide a multi-junction method that has a simple configuration, is economically inexpensive, and can reduce the load on time switches by determining the order of connections. In a digital multiplex terminal device consisting of an interface and a time switch having a branch section, a control means for extracting control bit information sent from a transmission line to a transmission line interface and controlling connection based on the control bit information. A control bit information bus for transmitting control bit information is provided, and the control means extracts the control bit information sent from its own transmission path, sends it to the control bit information bus, and extracts the control bit information sent from the other transmission path. The incoming control bit information is received from the control bit information bus, and when a connection request to the data interface is generated from only one transmission path, that transmission path is connected, and connection requests from multiple transmission paths are If there is one, the priority order of the transmission paths is determined, and the transmission path with the highest priority is selected and connected.

[Industrial application field]

The present invention relates to a multi-junction system that simultaneously communicates with a plurality of parties in a digital multiplex terminal device that multiplexes and communicates digital signals.

A digital multiplexing terminal device that performs communication by multiplexing digital signals, transmits the same data to multiple parties, and when receiving data from multiple parties, selects and connects one of them to perform communication. A multi-junction method is required.

There is a need for a multi-junction system that has a simple multi-junction configuration, is economically inexpensive, and can reduce the load on the time switch.

[Conventional technology]

FIG. 5 shows a block diagram illustrating a conventional example.

The conventional example in FIG. 5 includes a data interface 10 that interfaces with data terminal A, and transmission line interfaces 210 to 2n that interface to transmission lines 1 to n.
O and a time switch (
30A (hereinafter referred to as TSW), a branch circuit 50A that branches and transmits input data to a designated transmission path, and monitors a control bit (hereinafter referred to as S bit) input from the transmission path,
The multi-junction unit 50 is comprised of a selection switch (hereinafter referred to as SW) 50B that connects S=1 transmission line.

In the above configuration, data from data terminal A is input to TSW 30A via data interface 10, and in order to branch the data to a specified communication destination, TSW 30A
It is input to the multi-junction section 50 from 0A.

The branch circuit 50A of the multi-junction unit 50 performs a specified number of branches and transfers the branched data to the TSW 30A corresponding to each transmission line interface 210 to 2nO.
The data is sent to transmission lines 1 to n via time slots.

The data manually input from the transmission lines 1 to n is input to the selection SW 50B of the multi-junction section 50 via the transmission line interfaces 210 to 2 n O, TSW 30A, and the S bit in the data is monitored there to determine whether S=1. A transmission line is connected to the data interface 10 to perform communication.

[Problem to be solved by the invention]

In the conventional example described above, branching to multiple transmission lines and selective connection of data from multiple transmission lines are performed by hardware, which requires a dedicated panel for multi-junction, which increases the scale of the hardware. , the cost will be higher. In addition, in order to perform a branch, the branch data is TS
Since input/output is performed via W30A, the processing amount of TSW30A increases.

The present invention has a simple configuration, is economically inexpensive, and is capable of reducing the load on a time switch. The purpose is to provide a junction method.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, l to n are transmission lines, 10 is a data interface that interfaces with data terminal A, and 21 to 2n are lines that interface with transmission lines 1 to n. 30 is a transmission line interface that interfaces with the specified transmission line 1.
~n is a TSW that sets a time slot for data terminal A to communicate with a specified partner, and 31 is a TS that sends the same data to multiple transmission paths 1 to n.
211 to 2nl are control means for monitoring the S bit provided in the transmission line interfaces 21 to 2n and controlling the connection according to instructions from the S bit; 40 is for transmitting S bit information; This is an S-bit information bus, and providing such a means is a means to solve this problem.

[For production]

The control means 211 to 2nl extract the S bits sent from the transmission lines 1 to n, and when a connection request to the data interface IO is generated from only one transmission line, connect that transmission line, When connection requests are made from multiple transmission lines, the priority order of the transmission lines is determined, and the transmission line with the highest priority is selected and connected, which is simple, economical, and inexpensive. Moreover, it becomes possible to realize a multi-junction system that can reduce the load on the TSW.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a diagram for explaining the gate circuit of the embodiment of the present invention, FIG. 3 is a diagram for explaining the data on the S bit bus of the embodiment of the present invention, and FIG. 4 is the logic circuit of the embodiment of the present invention. Flowcharts explaining the operations are shown respectively. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 is a diagram illustrating the configuration of the control means 2nl shown in FIG. 1. (In the following embodiments, the control means 2nl will be referred to as a gate circuit.) The configuration of the gate circuit shown in FIG. 2 will be explained using the transmission line 1 as an example.

S-bit bus interface (hereinafter referred to as S-bit bus INF) that interfaces with the S-bit bus 40
21a, a logic circuit 21b that determines the priority of S bits from transmission paths 1 to n and generates a connection control signal, an S bit extraction circuit 21c that extracts S bits from transmission path 1, and a logic circuit 21b. 5W2 which is opened and closed by the connection control signal of
It consists of 1d.

The operation of the circuit having the above configuration is as follows: gate circuits 211 to 2nl
are connected to each other by an S bit bus 40, and S bit information from other transmission lines 2 to n is connected to the S bit bus 40.
and the logic circuit 21 via the S bit bus lNF21a.
b.

On the other hand, the S bit information from its own transmission line l is extracted by the S bit extracting circuit 21c, inputted to the logic circuit 21b, and simultaneously sent to the S bit bus 40 via the S bit bus lNF21a.

When the S bit of its own transmission line l is 1, the logic circuit 21b determines the priority order with other transmission lines 2 to n, determines whether connection is possible, and sends a connection control signal to 5W21.
d and controls the opening/closing of 5W21d.

FIG. 3 is a diagram explaining an example of data on the S-bit bus. It is assumed that the data input from transmission lines 1 to n have a frame bit F added to the beginning and an S bit added to the end. do.

The S bits from transmission lines 1 to n are extracted by respective S bit extraction circuits 21c to 2nc, and connected to the S bit bus lN.
It is sent to the S bit bus 40 via F21a to F2na.

On the S bit bus, only the S bits of transmission lines 1 to n are
They are arranged in a specified order, and here is an example in which the transmission lines are arranged starting from the smallest number.

FIG. 4 is a flowchart illustrating the operation of the logic circuit.

(2) Determine whether S=1 or 0 for your own transmission path.

■ When the value is 0, the gate circuit is turned off.

(2) When 1, it is determined whether S=1 exists in another transmission path.

■ When other transmission lines do not have S=1, only your own transmission line has 5===,I, so the gate circuit is
"On".

(2) When S=1 exists in another transmission path, it is determined whether the own transmission path has a high priority.

■ Turn on the gate circuit when your priority is high.

■ Turn off the gate circuit when your priority is low.

Here, when your priority is low, there is naturally a transmission line with a high priority that has S = 1, so
The gate circuit of that transmission line is turned on.

In the above description, the S bit is specified depending on the transmission path, but it is of course possible to specify it for each terminal accommodated on the same transmission path.

In addition, regarding the priority order, the transmission line with the smallest number has a higher priority, but since priority processing is given from the earliest time slot on the S bit bus 40, the S bit of the S bit of each transmission line is processed first. The priority order can be freely set by assigning the buses 40 in descending order of priority.

By configuring as described above, it is possible to realize a multi-junction system that is simple and economically inexpensive and can also reduce the load on the TSW.

[Effects of the Invention] According to the present invention as described above, it is possible to provide a multi-junction system that has a simple configuration, is economically inexpensive, reduces the load on the TSW, and has no limit on the number of branches. .

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a diagram explaining the gate circuit of the embodiment of the present invention, and FIG. 3 is a diagram explaining the data on the S bit bus of the embodiment of the present invention. 4 shows a flowchart explaining the operation of the logic circuit according to the embodiment of the present invention, and FIG. 5 shows a block diagram explaining the conventional example. In the figure, 1=n is a transmission line, IO is a data interface, 21 to 2n, 210 to 2nO are transmission line interfaces, 211 to 2n1 are control means, 21a is an S bit bus INF, 2b is a logic circuit, 2c is a S bit extraction circuit, 2d is SW, 30.30A is TSW, 31 is branch section, 40 is control bit information bus, 50 is multi-junction section, 50A is branch circuit, 50B is selection SW, 100.100A is digital multiplexing The terminal equipment is shown respectively. Detailed block diagram explaining the present invention FIG. 4 Flowchart explaining the operation of the logic circuit according to the embodiment of the present invention FIG. 2 Diagram explaining the circuit according to the embodiment of the present invention Diagram explaining data on the bus ff1q circle Block diagram explaining the conventional example Fig. 5

Claims (1)

[Claims] A digital multiplex terminal device (10) consisting of a data interface (10), a transmission line interface (21 to 2n), and a time switch (30) having a branching section (31).
0), the transmission line interface (21 to 2n) is connected to the transmission line (
The control means (21) extracts the control bit information sent from
1 to 2n1), and a control bit information bus (40) that transmits control bit information.
The control means (211 to 2n1) extracts the control bit information sent from its own transmission line, sends it to the control bit information bus (40), and extracts the control bit information sent from the other transmission line. The control bit information is transmitted through the control bit information bus (40
), and when a connection request to the data interface (10) is generated from only one transmission path, that transmission path is connected, and when there are connection requests from multiple transmission paths, the transmission is A multi-junction method that is characterized by determining the priority of the routes and selecting and connecting the transmission route with the highest priority.