JPH03201483A - Resonant tunneling semiconductor device - Google Patents

Abstract

PURPOSE:To enable a resonant tunneling semiconductor device to operate well even if it is low in breakdown strength between a base and a drain by a method wherein a part of semiconductor layers laminated for constituting a resonant tunneling semiconductor device possessed of a negative conductance is isolated into a separate island by insulating, and the isolated island is constituted as a resistive layer which acts as a resistor taking advantage of that carriers travelling through a semiconductor are speed-saturated. CONSTITUTION:A load resistor RL' is composed of a resistive layer 11 and a resistor lead-out electrode 12 in contact with the layer 11, where a part of an N-type InGaAs base layer 4 in an RHET is air-isolated to serve as the separate resistive layer 11. As the load resistor RL' is determined in resistivity basing on the thickness of the resistive layer 11 and the dose of the doped impurity (silicon), to obtain the load resistor RL' of required resistance, a resistive pattern may be controlled in size. In this case, as a resistor takes advantage of the speed saturation of carriers occurred in a semiconductor, it has such characteristics that it sharply increases in resistance at a certain potential and saturated. Therefore, a resonant tunneling semiconductor device of this design can be made to operate even if it is small in breakdown strength between a collector and a base as compared with a case that a conventional load resistor of linear characteristic is used by setting a condition under which an EXNOR gate functions well.

Description

[Detailed Description of the Invention] (Summary) This invention relates to a resonant tunneling semiconductor device such as a resonant tunneling hot electron transistor or a resonant tunneling bipolar transistor with improved characteristics of a load resistor formed in a substrate, such as a RHET or an RBT. The purpose is to simply and easily obtain a well-operating EXNOR gate by simply modifying the load resistance combined with a resonant tunneling semiconductor element, and to construct a resonant tunneling semiconductor device having negative conductance. By insulating and separating parts of the various semiconductor layers stacked on top of each other, the semiconductor layers become independent like islands.
In addition, the semiconductor device is configured to include a load resistor including a resistive layer that acts as a resistor when carriers traveling in the semiconductor reach velocity saturation, and a resistive extraction electrode formed on the resistive layer.

[Industrial application field]

The present invention provides a resonant tunneling hot electron transistor with improved characteristics of a load resistor formed in a substrate.
ot electron trans 1stor
:R1 (ET) or resonant tunneling bipolar transistor
ng bipolar transistor: RBT
) and other resonant tunneling semiconductor devices.

RHETs and RBTs are expected to become basic elements for computers in the future because circuits can be realized with a small number of elements.

In particular, when these elements are used, state retention functions and exclusive
:EXNOR) function can be easily realized.

However, in order for these elements to exhibit sufficient functionality, characteristics such as the load resistance used together are important, and improvements in this regard are also necessary.

(Prior Art) FIG. 5 shows a circuit diagram of a main part for explaining an EXNOR gate using RHET.

In the figure, Q is a RHET transistor (the same applies hereinafter), R1, R2, and R3 are resistors, RL is a load resistance, A and B are input terminals, and C is an output terminal.

FIG. 6 is a diagram for explaining the operation of the EXNOR gate shown in FIG. 5, and the vertical axis represents the base current III.
The horizontal axis represents the base-emitter voltage (2).

In the figure, LL, L2. L3 is the load line, CPl, CF
2. CF2 is the intersection of the multi-load lines L1 to L3 and the characteristic line;
P indicates the peak of the characteristic line, and ■ indicates the valley of the characteristic. Note that similar characteristics can be obtained by taking the collector current IC instead of the base current Ill on the vertical axis.

In this EXNOR gate, (1) When input terminal A = 0 and input terminal B = 0, the collector current of transistor Q does not flow and output terminal C
= High level (“H” level) (2) When input terminal A=0 input terminal B=1 or input terminal A=1 input terminal B=0, the collector current of transistor Q flows and output terminal C=
Crow level (°"L I+ level) (3) When input terminal A = 1 input terminal B = 1, the collector current of transistor Q does not flow and output terminal c
='“Hu level, in the case of (1) above, corresponds to the intersection point CPI in Fig. 6, in the case of (2) above, it also corresponds to the intersection point CP2, and in the case of (3) above, it also corresponds to the intersection point CPI. Each corresponds to the intersection CP3.

[Problem to be solved by the invention]

In the integrated circuit in which EXNOR gates are connected in multiple stages as explained in FIGS. 5 and 6, the load line related to the EXNOR gate shown in FIG. ,
As is clear from FIG. 6, it has a straight line shape. Therefore, in order to operate this EXNOR gate, the base current IB flowing through the transistor Q must be three times the base-emitter voltage VBt when the collector current IC reaches its peak, as judged from the load line L3. As described above, a collector-base breakdown voltage of about 4 to 5 times is usually required.

Usually, InGaAs/In (Aj2Ga)As-based RH
In the case of ET, the base-emitter voltage at the peak ■
1 is the ``separation of the valley and L valley'' of InGaAs.
0, which is slightly lower than the energy 0.55 [eV]
．． It is necessary to set it to about 45 to 0.5 (eV).

Considering only this valley separation energy, it is better to set the base-emitter voltage 1 as low as possible, but if it is set too low, carriers will be blocked by the barrier and the current gain will disappear. It has to be reasonably high because it will be stored away. In addition, in order to increase the collector-base breakdown voltage, the collector-barrier should be made thicker.
In other words, it would be fine to make it longer, but if you do that,
The carrier travels to the collector for a long time. To avoid this, if the collector barrier is made thinner or shorter, the collector
The barrier must be made high, which reduces the current gain. As described above, since there is a trade-off between current gain and collector transit time, a collector-base breakdown voltage of only about 2 [■] can be obtained at most.

From the foregoing, it is difficult to operate the EXNOR gate described with respect to FIGS. 5 and 6.

The present invention makes simple modifications to the load resistances combined with resonant tunneling semiconductor devices such as RHETs and RBTs, making it possible to simply and easily obtain EXNOR gates and the like that operate well.

[Means to solve the problem]

In the resonant tunneling semiconductor device of the present invention, various semiconductor layers (for example, semi-insulating
nP substrate 1, n-type I nGaAs collector layer 2, i-type I
n (A-Ga)AS: 7 rectifier/barrier layer 3, n-type 1
The nGaAs base layer 4, the i-type 1 nAffiAs film, the resonant tunneling barrier layer 5 made of the i-type I nGaAs film, the n-type InGaAs emitter layer 6, etc.) are insulated and separated into islands. In addition, a resistance layer (for example, resistance layer 11) that acts as a resistance when carriers traveling in the semiconductor reach velocity saturation, and a resistance extraction electrode (for example, resistance extraction electrode 1) formed on the resistance layer.
2 and 13) (for example, load resistance RL).

[Effect]

By adopting the above means, the load resistance has a characteristic that its resistance value increases rapidly in response to a change in the base-emitter voltage VllE in the resonant tunneling semiconductor device. According to its characteristics, good operation is possible even if the withstand voltage between the collector and base of a resonant tunneling semiconductor device is low. The circuit can operate stably at a voltage of about 3V, which is much lower than that of about 3V when using conventional technology.

[Embodiment] Fig. 1 shows a circuit diagram of a main part for explaining one embodiment of the present invention, and the same symbols as those used in Figs. 5 and 6 represent the same parts or have the same meaning. shall have. Note that the EXNOR gate is also targeted here.

In the figure, R1', R2', and R3' are resistances, RL
' indicates the load resistance.

When this embodiment is viewed as a circuit, it is the same as the conventional circuit shown in FIG. There is.

FIG. 2 is a diagram for explaining the operation of the EXNOR gate shown in FIG. 1, and the vertical axis shows the base current 1. (or collector current rc), and the base-emitter voltage VIE is plotted on the horizontal axis.

In the figure, LL', L2', and L3' indicate load lines.

As is clear from the figure, the load lines LL' to L3' remain unchanged until the base-emitter voltage ■1 reaches the value, and then rapidly fall. , it does not show a linear shape that is sloped with respect to the change in the base-emitter voltage VBH as seen in FIG.

Therefore, with respect to the load line L3', the base current I.

(Thus, the collector current IC) = O, and the base-emitter voltage when the base current 18 (Thus, the collector current tC) = o, with respect to the load line L3. (2) The collector-base breakdown voltage is improved by the difference from the value of 1.

It is impossible to provide such characteristics with ordinary resistance materials, such as metal materials such as WSiN and NiCr.
The present invention utilizes velocity saturation of the semiconductor layer.

FIG. 3 is a cutaway side view of essential parts showing a specific structure of one embodiment of the present invention explained with reference to FIGS. 1 and 2, and FIG. 4 is a main part of the semiconductor device shown in FIG. 3. This is a partial plan view, and the same symbols as those used in FIGS. 1 and 2 represent the same parts or have the same meanings.

In the figure, 1 is a semi-insulating 1nP substrate, 2 is an n-type 1 nGaAs collector layer, 3 is an i-type 1 n (A/2Ga)As collector/barrier layer, 4 is an n-type InGaAs heath layer, and 5 is an n-type I nGaAs collector layer. Resonant tunneling barrier layer (emitter barrier layer) consisting of i-type 1 nAffiAs film and i-type InGaAs film, 6 is n-type 1 nGaAs emitter layer, 7 is emitter electrode consisting of Cr/Au, 8 is Cr
/Au base electrode, 9 is Cr/Au
11 is a resistance layer, and 12 and 13 are resistance lead electrodes, respectively.

The load resistance RL' in this embodiment is made by separating a part of the n-type 1 nGaAs base layer 4 in the RHET with air to form an independent resistance layer 11, and contacting it with resistance extraction electrodes 12 and 13. It is composed by letting

The resistivity of this load resistance RL' is determined by the thickness of the resistance layer 11 and the amount of doping with impurities (for example, silicon), so
In order to obtain the required resistance value, it is sufficient to control the size of the resistance pattern, and since the resistance in this case utilizes the velocity saturation that the carrier exhibits in the semiconductor, the voltage (in this example) For example, at about 1.5 (V)), the resistance value suddenly increases and exhibits a characteristic of saturation. Therefore, even if the collector-base withstand voltage is lower than when using a conventional load resistor with linear characteristics, it is possible to set and operate the EXNOR gate under conditions that allow it to function well.

The present invention is not limited to the RHET as in the above-mentioned embodiments, but can also be applied to, for example, an InGaAs/InAj2As-based RBT. In that case, by using the base layer of the RBT as the resistance layer, the You can get the same effect as the previous one.

[Effect of the invention] In the resonant tunneling semiconductor device according to the present invention,
By insulating and separating some of the stacked semiconductor layers to configure a resonant tunneling semiconductor device with negative conductance, the semiconductor layers become independent in the form of islands, and when the carriers traveling in the semiconductor reach velocity saturation, resistance increases. The load resistor includes a resistor layer that acts as a load resistor and a resistor lead-out electrode formed on the resistor layer.

By adopting the above configuration, the load resistance has a characteristic that its resistance value increases rapidly in response to a change in the base-emitter voltage VB in the resonant tunneling semiconductor device. According to its characteristics, good operation is possible even if the withstand voltage between the collector and base of a resonant tunneling semiconductor device is low. The circuit can operate stably with a voltage of about 3 [■], which is much lower than the voltage of about 3 [■] in the case of conventional technology. Further, compared to the conventional device using a load resistor made of a metal material, the area occupied per unit gate can be reduced, and even higher integration can be achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part for explaining one embodiment of the present invention, FIG. 2 is a line diagram for explaining the operation of the EXNOR gate shown in FIG. 1, and FIG. FIG. 4 is a cross-sectional side view of the main part of the embodiment of the present invention explained in FIG. 2 as a concrete structure, FIG. 4 is a plan view of the main part of the semiconductor device shown in FIG. FIG. 6 shows a main circuit diagram for explaining the EXNOR gate shown in FIG. 5, and a line diagram for explaining the operation of the EXNOR gate shown in FIG. In the figure, Q is a RHET transistor, R1,
R2 and R3 are resistors, RL is a load resistance, A and B are input terminals, C is an output terminal, Ll, L2 . L3 is the load line, CPI, C
F2. CF3 is the intersection of each load line L1 to L3 and the characteristic line, P is the peak of the characteristic line, ■ is the valley of the characteristic, R1',
R2' and R3' are resistances, RL' is a load resistance, 1 is a semi-insulating InP substrate, 2 is an n-type 1nGaAs collector layer, 3
is an i-type In(A/2Ca)As collector/barrier layer, 4
5 is an n-type InGaAs base layer, 5 is an i-type 1nAfAs film, and an i-type 1nGaAs film.
Barrier layer (emitter barrier layer), 6 is n-type InGaA
s emitter layer, 7 is an emitter electrode made of Cr/Au, 8 is a base electrode made of Cr/Au, 9 is a collector electrode made of Cr/Au, 11 is a resistance layer, 12 and 13 are resistance extraction electrodes. are shown respectively.

Claims (1)

[Claims] By insulating and separating a portion of stacked semiconductor layers to constitute a resonant tunneling semiconductor device having negative conductance, carriers traveling in the semiconductor are separated into island-like structures. 1. A resonant tunneling semiconductor device comprising a load resistor including a resistor layer that acts as a resistor upon velocity saturation, and a resistor extraction electrode formed on the resistor layer.