JPH03201422A - Circuit pattern formation and applicable mask thereto - Google Patents

Abstract

PURPOSE:To form fine patterns without developing such a defect as the short circuit of patterns by a method wherein circuit patterns are transferred by exposing a wafer through the first masks formed in the first pattern regions and then the wafer is shifted so that the first pattern regions and the second pattern regions may be overlapped with each other to additionally expose the wafer. CONSTITUTION:Contact patterns 32A represent the contact patterns to be formed on the upper underneath stepped parts while contact patterns 32B represent the contact patterns to be formed on the lower stepped parts to expose the areas A using these patterns. The other contact patterns 32B1 are arranged only on the contact patterns 32B formed on the lower stepped parts. Then, the contact patterns 32A, 32B and 32B1 in the areas A and the areas B are dually exposed. Through these procedures, only the thick parts of a photoresist film on the lower stepped parts can be dually exposed partially thereby enabling the circuit patterns of the upper and lower parts to be formed simultaneously with high precision.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a photolithography process, which is one of the manufacturing technologies for semiconductor devices (hereinafter referred to as LSI), and a circuit using a reduction projection aligner as an exposure device. The present invention relates to a pattern forming method and a mask using the same.

(Prior art) Conventionally, in the formation of circuit patterns in LSI manufacturing,
Devices that use ultraviolet light for exposure are known, and in particular, a method in which a reduction projection aligner (hereinafter referred to as a stepper) and a reflection projection aligner are used in combination is commonly used.

Although the number of semiconductor wafers processed by steppers per unit time (hereinafter referred to as throughput) is lower than that of reflective projection aligners, steppers have high resolution ability in pattern formation and can form fine circuit patterns with high precision. Therefore, as LSIs become more highly integrated and smaller, the number of steps for forming fine circuit patterns that cannot be formed without using a stepper is increasing even in the photolithography process.

In addition, the photoresist used also requires high resolution, and in processes that require exposure with a stepper,
A positive photoresist whose main component is Talesol Novolac (for example, 0FRP-800 manufactured by Tokyo Ohka, TSMI?
-8800, TSMR-899 (trade name) is used for boat fishing.

However, even with the above-mentioned pattern forming method using a positive photoresist and a stepper, there was no particular problem in LSI manufacturing where the minimum dimension is around 14, but the minimum dimension is less than 1n. Even finer circuit patterns (for example, 0.
Wiring pattern of about 5-0.8n, 0.5-0.9j
In the manufacturing process of an LSI having a contact pattern of approximately Iy1, the following problems come to light and cannot be ignored.

In other words, due to the difference in the level of the base coated during LSI manufacturing,
It becomes difficult to accurately form both circuit patterns on the top of the step and on the bottom of the step at the same time, and this problem is particularly problematic when forming wiring circuit patterns that are performed after the LSI circuit pattern has been formed to a certain extent. In formation, this becomes more frequent as the step difference between the base layers becomes larger, and from FIG. 8 onwards, the formation of a contact pattern, which is the formation of a wiring circuit pattern for an LSI, will be explained in detail by way of example.

FIG. 8(a) is a cross-sectional view showing a section of a memory LSI having a MOSFET having a level difference in the base immediately before the wiring circuit pattern is formed. In this FIG. 8(a), 61
is an impurity diffusion region of a silicon substrate and indicates an element region. 62 is an LO with a film thickness of approximately 3,000 to 8,000 people
It is a field oxide film formed by the GO3 process,
A level difference of about 1,500 to 4,000 degrees was formed in the element region 61.

The gate electrode pattern 63 (hereinafter referred to as word line) is formed of a eutectic film or polycrystalline silicon film of metal such as tungsten, titanium, molybdenum, and silicon and having a film thickness of approximately 1500 to 4000 nm. Figure 8 (a
) Then field oxidation lI! 62.

After forming this word line 63, the first interlayer 1I16 is formed on the entire surface.
4 is formed. This first glabellar membrane 64 is about 200
It is a silicon oxide film having a thickness of 0 to 6000 μm.

Further, at a position above the field oxidation IPJ 62, a pattern 65 of about 10
The pattern 65 is formed of a polycrystalline silicon film of about 0 to 4000 layers, and serves as various electrodes or resistance circuits.

After forming this pattern 65, a second interlayer film 66, which is a silicon oxide film having a thickness of about 100 to 4000 layers, is formed.
A pattern 67 (hereinafter referred to as a bit line) made of the same material as the word line 63 and having a film thickness of approximately 1,500 to 4,000 layers is formed on the second glabellar membrane 66, and is also formed on the field oxidized WIA 62. It is formed to be located at.

Further, a third glabellar film 68 made of a silicon oxide film having a thickness of about 1,500 to 4,000 is formed on the upper surface.

In the above structure, there is an unavoidable step due to the thickness of the word line 63, pattern 65, and bit line 67, and this step is not specific to the memory LSI, but is similar to other LSIs.
Regarding SI, this is a step that inevitably occurs due to the structure, and in the state shown in Figure 8(a), it is about 2000 to 600
A level difference of about 0 Å is generated.

Next, as shown in FIG. 8(b), contact patterns 69A and 69B are formed on the bit line 67 and the element region 61 to be bonded using a wiring material (not shown).

(Problem to be solved by the invention) However, as shown in FIG. 8(a), due to the difference in base
It is extremely difficult to simultaneously form the contact pattern 69A to be formed on the top of the step and the contact pattern 69B to be formed on the bottom of the step with high accuracy, which will be explained in detail from FIG. 9(a) onwards.

FIG. 9(a) is a sectional view showing a state in which a photoresist 1170 is formed on the base shown in FIG. 8(a). This photoresist lI*70 is most commonly manufactured using the spin code method, and is approximately 9000λ thick on a wafer with no steps.
The surface of the photoresist film 70 formed under the above conditions is considerably flattened, and the photoresist film 70A1 on the top of the step and the bottom of the step differ. Photoresist film 7 in
In 0B1, a difference in film thickness occurs by a value almost equal to that of the underlying step bone.

In this state, exposure and development processing is performed using a stepper, but here, the dimension of the contact pattern on the top of the step is 70A, and the dimension of the contact pattern on the bottom of the step is 70B, so that both contact patterns are simultaneously and accurately processed. It is required to be completed.

However, as shown in FIG. 9(b), the photoresist pattern 71 after exposure and development is such that, under exposure conditions that allow the contact pattern 71A at the top of the step to be completed with high precision, the contact pattern 71B at the bottom of the step is formed by the photoresist film. Due to the difference in thickness, the amount of exposure is insufficient, and photoresist remains on the bottom portion 71B1 of the contact pattern 71B.

On the other hand, if the exposure process is performed under conditions that allow sufficient opening of the contact pattern 71B on the bottom of the step, the contact pattern 71A on the top of the step will be overexposed. The dimensions of the desired contact pattern increase, resulting in a rapid increase in the occurrence of wiring defects (electrical short circuits).

In order to solve the above problem, by setting the dimension 70B of the contact pattern formed on the lower part of the step larger on the mask, the bottom part 71 of the contact pattern 71B
Although it becomes difficult for photoresist to remain on B1, since the dimension 11B of the contact pattern becomes large, the occurrence of wiring defects (electrical conflicts with the word line 63 pattern) rapidly increases.

This problem has been solved as LSIs become more precise and smaller.
This is particularly noticeable when it is absolutely necessary to form a contact pattern of about 0.9n.

Therefore, if the contact size is set to be large on either the top of the step or the bottom of the step (for example, on the top of the step, the bit line 6
If the size of the pattern 7 is set large, and the pattern spacing of the word lines 63 is set large above the lower part of the step, etc.), this becomes a major hindrance to miniaturization of the LSI.

In the present invention, the invention of claim 1 solves the problems that the prior art has, such as a contact pattern to be formed on the upper part of the step and a contact pattern to be formed on the lower part of the step, which are present in the structure of LSI. It is difficult to simultaneously form the contact patterns with high precision, and if the dimensions of the contact patterns formed on the top and bottom of the steps are different, this will impede miniaturization and make it impossible to form a pattern with high precision. The present invention provides a circuit pattern forming method that solves these problems.

Further, the invention of claim 2 is applicable not only to forming a circuit pattern having steps with high precision, but also to pattern formation by performing exposure that adjusts the amount of light, and to simultaneous exposure of a plurality of LSI chips. The present invention provides a mask for use in the method.

(Means for Solving the Problems) In order to solve the above problem, the invention of claim I provides a circuit pattern forming method in which a circuit is formed on a wafer through a first mask pattern formed in a first pattern area. A step of exposing the wafer to light to transfer the pattern, and then moving the wafer to a second pattern area at a distance by the size of the semiconductor chip and transferring the mask pattern of the second pattern area to the first mask. This method introduces a process in which the wafer is additionally exposed through the wafer.

The invention of claim 2 also provides a mask for use in a circuit pattern forming method, in which a first mask formed in a first pattern region within a reticle and a first mask formed in a first pattern region separated from the first pattern region by the size of a chip of a semiconductor device are provided. A second mask is formed in a second pattern area at a position and is smaller than the first mask for performing multiple exposure on the wafer through predetermined portions of the first mask.

(Function) According to the invention of claim 1, since the above steps are introduced in the circuit pattern forming method, the circuit pattern is formed by exposing the wafer to light through the first mask formed in the first pattern area. After the transfer, the wafer is moved so that the first pattern area and the second pattern area overlap on the wafer, and predetermined portions of the first mask 7 and the second mask are overlapped to perform additional exposure on the wafer. Therefore, the exposure amount of the wafer is reduced to 1! The pattern can be formed by knotting, and the above-mentioned problems can therefore be eliminated.

Further, according to the invention of claim 2, since the mask is configured as described above, after the wafer is exposed through the first mask, a predetermined portion of the first mask and a second mask smaller than the first mask are exposed. The wafer is additionally exposed to light with the exposure amount adjusted through the mask No. 2. Therefore, it is possible to form patterns with high precision regardless of the presence or absence of steps, and it is also possible to perform simultaneous exposure of multiple LSI chips. Applicable to a wide range of exposures.

(Example) Hereinafter, an example of the circuit pattern forming method of the present invention and a mask using the same will be described based on the drawings. FIG. 1 is an explanatory diagram of an exposure state in which exposure processing is performed on a wafer applied to a circuit pattern forming method.

Further, FIG. 2 is a plan view of a reticle for explaining one embodiment thereof.

First, in FIG. 2, 1 is the exposure area of the stepper, and 2 is the reticle. 3 is LSI chip 4,5
This is a scribe line area located around the reticle 2, and two LSI chips 4 and 5 are arranged on the scribe line 3. However, especially 2
It is not limited to chips.

Here, in area A of the LSI chip 4, a normally used circuit pattern is arranged, and the LSI chip 5
In area B, only the above-mentioned pattern for partially performing additional exposure is arranged.

Next, the case where exposure processing is actually performed on the wafer 6 will be explained with reference to FIG. Arrow a is the direction in which the wafer 6 steps, and the arrow indicates the length of the step, and this length b is equal to the dimension of the LSI chip 4.5 on the wafer 6 in the short side direction.

In addition, 7 indicates a chip that has already been double exposed,
On the outermost chip 7a of the wafer 6, only area A is exposed once.

However, the corner portion of the outermost chip 7a of the wafer 6 is protruding from the wafer 6, and in reality, the LSI is a good product.
It cannot be.

Also, 8 is the area exposed in the previous shot, and the chips in the step direction of wafer 6 have already been double exposed, but the other chip areas have only been single exposed in area B. do not have.

Exposure processing is performed in the state shown in FIG. 1, and the chip 9
As shown in FIG.
Exposure processing is performed by overlapping the chips to the areas where only the chips have been exposed.

Next, an example of a normal pattern placed in area A is shown in FIG. 3(a). 32A and 32B are contact patterns, indicating areas where chromium 31 is absent.

The rest of the surface is covered with chromium 31, and the exposure light is masked.

Contact pattern 32A indicates a contact pattern to be formed on the top of the step of the base step, and contact pattern 32B indicates a contact pattern to be formed on the bottom of the step.

FIG. 3(b) shows a contact pattern placed in area B that is to be partially subjected to additional exposure.

A normal contact pattern 32 arranged in area A only in the contact pattern part to be formed on the lower part of the step.
A contact pattern 32B1 somewhat smaller than B is arranged.

As described above, the contact patterns 32A, 32B, and 32B1 in area A and area B are
By performing the heavy exposure process, as shown in FIG. 3(c), the contact pattern 32A formed on the upper part of the step is exposed only once as usual, and is further formed on the lower part of the step. The contact pattern 32B is formed by additionally exposing the contact pattern 32B1 to the contact pattern 32B which has been subjected to the normal exposure process, and therefore the contact pattern 32B2 is exposed to the lower part of the step. Become.

As described above, according to the embodiment of the circuit pattern forming method shown in FIGS. 1 to 3(c), when forming a pattern on a wafer having a base step, only the portion where the photoresist film above the step is thick is formed. Since it is possible to partially perform double exposure processing, it is easily possible to form both circuit patterns simultaneously at the upper part of the step and at the lower part of the step with high precision.

Note that the same effect can be obtained even if the exposure process using area A and area B is performed in advance.

In particular, in the above embodiment, since the mask is formed so that the dimensions of the contact pattern 32B1 for additional exposure on the lower part of the step are somewhat smaller than the dimensions of the normal contact pattern 32B, exposure of only the normal contact pattern 32B is required. , it becomes possible to sufficiently remove the remaining photoresist as shown in the bottom portion 71Bl of the contact pattern shown in FIG. 9(b), but the dimension of the contact pattern 71B hardly increases.

Further, since the dimensions of the contact pattern 71A1 on the top of the step are also subjected to the normal exposure process only once, it hardly occurs that the contact pattern 71A1 is formed larger than the desired dimension.

Furthermore, the presence or absence and dimensions of the contact pattern 32B1 to be additionally exposed shown in FIG. 3(b) can be set optimally by taking into consideration the size and shape of the step on the base, the reflectance of the base to the exposure light, etc. , it can be expected to be effective for pattern formation on all steps in a process having steps.

Therefore, the circuit pattern forming method of the present invention is not particularly effective only when forming contact patterns;
The present invention can also be applied to other pattern forming methods other than the contact pattern (in FIG. 5).

FIG. 4(c) is a plan view of FIG. 4(a) and FIG. 4(b), in other words, the cross-sectional view taken along the line A-A in FIG. 4(c) is ), and the cross-sectional view taken along line BB in FIG. 4(c) is shown in FIG. 4), and 42 in FIG. 4(c) is a photoresist pattern.

Photoresist patterns 42A and 42B having minute slits are simultaneously formed on a base 41A having a step as shown in FIG. 4(a) and on a flat base 41B without a step as shown in FIG. 4(a). Even in this case, photoresist residues 42A1 are likely to occur between the photoresist patterns 42A even in the lower step portion 41AI.

These figures 4(a) to 4(c) are also shown at the lower part of the step 41.
This is an example in which it is difficult to simultaneously form a pattern accurately on the top of the step 41 and on the top of the step.

Therefore, pattern formation is performed using the circuit pattern forming method of the present invention. Figure 5 (a) shows the area of the normal pattern on the mask, which corresponds to the area "A" in Figures 1 and 2; This corresponds to area "B".

5(a) is a portion covered with chrome, which corresponds to the photoresist pattern 42 in FIG. 4(c). Further, 52 is a slit portion through which light passes during exposure.

Next, FIG. 5) shows a mask pattern for partially performing additional exposure. Flat base 4 shown in Figure 4(c)
A slit pattern 53 is formed only at the location where the photoresist residue 42A1 in 1B occurs, and the rest is covered with chromium 54.

The pattern 511 is a normal pattern and is used to indicate the positional relationship between the portion 51 covered with chrome and the pattern 511, and does not actually exist.

In addition, in the embodiments shown in FIGS. 1 to 3(c) above, in order to simplify the explanation, two patterns are formed: a through hole for the uppermost layer wiring and a through hole for the substrate. However, in some cases, a through hole between the second layer wiring or the third layer wiring is also required.

In this case, it is preferable to prepare three patterns with different areas through which light passes.

FIG. 6(a) shows an example of this, and FIG. 6(a)
) patterns 80A to 80D are sequentially applied to the top layer, second layer, and third layer.
The figure shows the case where the amount of light passing through the layer and the substrate is increased sequentially and overlapping exposure is performed, and the shaded area is the area through which light passes.

Therefore, in this case, the uppermost layer pattern 80A is not exposed.

In addition, since this invention adjusts the amount of light, the sixth
As shown in (in the figure), one block may be formed by a plurality of patterns 90A to 90D.

That is, since the pattern of each block does not need to be patterned into its shape, the pattern may be fine beyond the exposure limit.

Thereby, the small pattern 80B in FIG. 6(a) can be made into a pattern whose size matches the through hole, and the entire through hole can be irradiated with light almost uniformly.

Furthermore, since this invention is characterized in that a pattern for light*m nodes is provided in the actual pattern and a part shifted by one chip from the actual pattern, the energy amount of the light irradiated onto the wafer can be adjusted for each part. Can be adjusted.

Therefore, it can be applied not only to through-holes but also to patterns of other shapes. For example, when wiring is to be carried out across a recessed part, it may be formed at a position corresponding to the intermediate part.

Furthermore, as shown in FIG.
It can also be applied to a mask in which the SI chips 4A to 4D are arranged and exposed simultaneously.

As described above, the present invention can be expected to have sufficient effects not only for forming contact patterns but also for forming ordinary fine slit patterns.

However, by applying this invention, there may be a drawback that the number of exposures on one wafer increases and the throughput decreases, but the process in which pattern formation can be performed without using this invention is the second step. For area B shown in the figure, simply place the same pattern as area A on the mask and set the step size of the wafer to double the step length indicated by the arrow in figure 1. This makes it possible to apply this method in conjunction with a normal pattern forming process.

That is, the present invention can be applied only to processes that cannot be done without using the present invention, and other processes can be carried out using completely normal methods.

Furthermore, the stacking of chips may be performed in either area A or area B, and is not particularly different from the usual method.

In general, the exposure area is not limited to two areas in particular, as long as an area where double exposure is performed is ensured.

(Effects of the Invention) As described above in detail, according to the invention of claim 1, the circuit pattern is transferred by exposing the wafer through the first mask formed in the first pattern area, and the circuit pattern is transferred to the wafer.
After moving the wafer by a dimension such that the second pattern area and the first pattern area, which are located apart from the pattern area by the size of the LSI chimp, overlap on the wafer, a second pattern area formed in at least the second pattern area is moved. Since additional exposure is performed on the wafer through the mask pattern and predetermined portions of the first mask pattern, there is no need to set the circuit pattern size large, and defects such as short circuits in the pattern formed on the wafer can be avoided. A fine pattern can be formed at a predetermined location with high precision without causing any damage.

Further, according to the invention of claim 2, a first mask pattern for transferring a circuit pattern to a wafer is formed in a first pattern area disposed within a reticle, and an L
Since a second mask pattern that can be additionally exposed on the wafer is formed through a predetermined portion of the first mask pattern in at least a second pattern region located apart by the size of the SI chip, the second mask pattern is formed on the wafer so that additional exposure is possible. Applicable to a wide range of wafer exposures, including forming circuit patterns with high precision simultaneously on the bottom of steps, pattern formation by adjusting the light intensity, and simultaneous exposure of multiple LSI chips. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the exposure state of a wafer in the circuit pattern forming method of the present invention, and FIG.
FIG. 3(a) is a plan view of the arrangement state of the pattern area of the first
FIG. 3(b) is a plan view of the contact pattern formed in the first pattern area in the figure, FIG. 3(b) is a plan view of the contact pattern that becomes the second mask pattern, and FIG. FIG. 4(a) and FIG. 4(b) are plan views of the state in which additional exposure is performed on a wafer, respectively, for explaining another embodiment of the circuit pattern forming method of the present invention. 4(c) is a plan view of FIG. 4(a) and FIG. 4(b), and FIG. 5(a) shows a normal pattern area on a mask of the circuit pattern of this invention. 5(b) is a plan view showing a mask pattern for additional exposure; FIG. 6(a) is a plan view of another mask pattern; FIG. 6(b) is a plan view showing a mask pattern for performing additional exposure;
) is a plan view of a different embodiment of the mask pattern, FIG. 7 is a plan view of still another embodiment of the mask, and FIG. Figure 8(b) is a cross-sectional view of the state in which a contact pattern is formed on the stepped portion of the base in Figure 8(a), and Figure 9(a) is a sectional view of the state in which a photoresist is formed on the base in Figure 8(a). 9) is a cross-sectional view of the state in which photoresist remains at the bottom portion of the contact pattern below the step. 1... Exposure possible area, 2.../ticle, 4,5LS
I chip, 6... Wafer, 7... Double exposed chip, 32A, 32B, 32B1.32B2... Contact pattern, 41A... Base having a step, 41
A1... Lower part of step, 42.42A, 42B... Photoresist pattern, 42A1... Remaining photoresist,
52...Slint portion, 80A-80D...Pattern. 2A 32nd area A contact pattern layout (a) 3281 B, 32nd 1 Area B contact pattern layout + 1) 1 (cJ Figure 3 Forming a slot on the base with a step cross-sectional view (0
) Step view with one slit formed in a flat base (b) Plan view of FIGS. 4(0) and 4(b) (c) FIG. 4I Plan view of the normal pattern area of the mask 1a) Plan view of the pattern area on the mask for radial partial exposure (b) Fig. 5 Figs. Figures 4A to 40: Plan view of 1 to 4 chips arranged on LSI chip reticle Figure 7

Claims (2)

[Claims] (1) (a) A step of exposing the semiconductor to the first pattern region to transfer the circuit pattern onto the wafer through the first mask pattern formed in the first pattern region; (c) moving the wafer by a dimension such that a second pattern area separated by a distance corresponding to the size of a chip of the device and the first pattern area are overlapped on the wafer; (c) the first mask pattern; A method for forming a circuit pattern, comprising: additionally exposing the wafer to light through a second mask pattern formed in a predetermined portion of the wafer and in the second pattern region. (2) (a) A first mask provided in a first pattern area arranged in the reticle for transferring a circuit pattern onto a wafer; (b) A chip size of a semiconductor device in the reticle; The first mask is provided in at least a second pattern area at a position apart from the first pattern area by a dimension corresponding to , and is provided in at least a second pattern area at a position apart from the first pattern area to perform multiple exposure on the wafer through a predetermined portion of the first mask. A second mask further reduced in size and a mask used in a circuit pattern forming method.