JPH03201287A - Delay quantity controllable semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prohibit the increase of the number of ROM control input terminal by providing a variable delay circuit and a ROM, setting the delay quantity control of the variable delay circuit with the ROM output data. CONSTITUTION:At each address of the ROM, the control data which correspond to the delay quantity of the variable delay circuits L0, L1 are housed. And the data specifying ROM address are inputted from the ROM address input terminals PO-PT to the ROM R, the delay quantity control input data c1-cn, n1-un from the ROM output terminals O1-On, (N+1)-2n are respectively outputted to the variable delay circuits L0, L1 and the delay quantity is controlled. In such a manner, the data controlling plural data delay quantity transmitted in parallel are housed in the ROM R. In such a manner, the number of control input terminals to input the signal designating data address, is not increase despite increasing the number of variable delay circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit in which delay amount can be controlled.

(Prior Art) Conventionally, this type of semiconductor integrated circuit capable of controlling the amount of delay has a configuration as shown in FIG. In Figure 4,
I-0 and 11 are variable delay circuits, and upper o and L1 are variable delay circuits respectively.Ol [10 input data, mO, ml
are the output data of variable delay circuits LO and Ll, respectively. Further, 01 to Cnu1 to In are delay amount control input data. In order to control the amount of delay, arbitrary values are input from the control input terminals AO to AJ and BO to BJ, decoded by decoders so and si, and output to the variable delay circuit.
．． Ll delay I Ill m input data C1-Cn.

The signals were output as u1 to Un, and the amount of delay was controlled.

[Problem to be solved by the invention]

The above-described conventional semiconductor integrated circuit capable of controlling the amount of delay has a drawback in that as the number of variable delay circuits increases, the number of control input terminals of the decoder increases.

Therefore, the present invention solves the above-mentioned drawbacks, and provides delay amount control that does not require an increase in the number of control input terminals for controlling the delay amount of the variable delay circuit even if the number of variable delay circuits increases. The purpose is to provide a semiconductor integrated circuit that is possible.

[Means to solve the problem]

A semiconductor integrated circuit capable of controlling delay amount of the present invention has a variable delay circuit capable of controlling delay amount by a delay amount control input, and transmits parallel data, wherein: It has a ROM that stores data and outputs delay amount control data corresponding to a designated address to the variable delay circuit.

(Function) In this way, data that controls the amount of delay of multiple pieces of data transmitted in parallel by multiple variable delay circuits is RO
Since the data is stored in M, the number of control input terminals for inputting signals indicating the address of this data does not increase even if the number of variable delay circuits increases.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a semiconductor integrated circuit capable of controlling the amount of delay according to the present invention, and FIG. Figure, Figure 2 (
2b) is a waveform diagram showing the waveform of input data io input to the variable delay circuit of FIG. 2(a) and the waveform of output data mQ for combinations of values of delay amount control input data 01 to Cn.

The semiconductor integrated circuit in FIG. 1 includes two variable delay circuits LO,
Has L1 and ROMR, variable delay circuit 1.0.11
Input data ig and 41 are input from data input terminals DO2D1, respectively. Further, the ROMR is connected to ROM address input terminals PO-PT for inputting an address, and the read data is transferred to variable delay circuits LO and L.
ROM output terminal 01 to On, 011 to output to 1
~2n. Then, the variable delay circuit [0 and Ll
are input data 0 and delay control input data 01, respectively.
~Cn and input data i1. Delayed suspension control input data u1~
Upon receiving Un, the output data m□ and ml are sent to the data output terminal K.
Output to O and 1 respectively.

Next, the operation of this embodiment will be explained.

A variable delay circuit LO is provided at each address of the ROMR.

Control data corresponding to the amount of delay of Ll is stored,
ROM address input terminals PO to PT to ROMR
Data specifying M address is input, and delay amount control input data C1 is input from ROM output terminals 1 to n, n+1 to 2n.
~Cn and u1~un are variable delay circuits LO and L, respectively.
The amount of delay is controlled.

Further, an example of the variable delay circuit and waveform diagrams illustrating its operation are shown in FIGS. 2(a) and 2(b), respectively. In FIG. 2(a), a□, ai...an are partial data outputs inside the variable delay circuit +-0 or Ll in FIG. 1, respectively.

These are combined by the OR element OR and output as output data m□ or ml.

Each of the semiconductor AND elements No, N+,...Nn has a minute delay characteristic of approximately NS (nano second), and a cascade connection circuit in which a plurality of these AND elements are connected in cascade is formed. A plurality of sets of cascade-connected circuits are further connected in series, and the output ends of each of the plurality of cascade-connected circuits are connected to AND elements ANo, ANl, . . . ANm, respectively. These AND elements each have delay amount control input data 01 to Cn.
controlled by

FIG. 2(b) shows that for the input data of the pulse waveform which is 0,
When the values of the delay amount control input data CI, C2, . . . Cn are changed into three types as shown in the figure, the OR element OR
It is a waveform diagram showing the waveform of the output data m□ output from the delay amount control input data c,,c2,...Cn.
This shows that the delay amount of the delay circuit can be changed at will. That is, in FIG. 2(a), AND element No.
, N1. ...Nn (7) The cascade connection circuit is a delay circuit with a fixed delay time, and is provided with delay amount control input data CI, c2.

. . . AND element ANo to which Cn is respectively input.

ANl...ANm and the OR element OR are combined to form a variable delay circuit between input data io and output data m□.

Next, as an application example of this embodiment, it will be explained with reference to FIG. 3 that enlarged output data m□ is obtained from input data io.

FIG. 3 is a waveform diagram for explaining one application example of this embodiment, and the waveforms of input data io and the output of AND element Nj are as shown in the diagram, and delay amount control input data 01
When ~Cn=1, the output aO of the AND element ANo is as shown in the figure.

Similarly, the output a1 of AND element AN1 and the AND element A
The output am of Nm is as shown in the figure, and the output data m□ of the OR element OR is enlarged and output as shown.

Now, in FIG. 1, the variable delay circuit LO.

Although the number of Ll is only two, if this number increases, the delay amount control input data c1 to Cn will inevitably be generated.

As the number of U1-un increases, the number of output terminals 1-n and n+1-2n of the ROMR also increases. But R
For OMR, ROM address, input terminals PO~PT
By simply increasing the number of ROM addresses instructed by R
There is no problem in the slightest if the number of OM III tl input terminals PO-PT remains as it is.

〔Effect of the invention〕

As explained above, the present invention includes a variable delay circuit that transmits a plurality of pieces of data in parallel, and an RO that outputs the stored data as delay amount control input data of the variable delay circuit.
By setting the delay amount control of the variable delay circuit using the output data of the ROM, there is an effect that the number of ROM control input terminals is not increased, and if a rewritable EPOM is used, Since arbitrary data can be stored, various settings can be made to suit the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a semiconductor integrated circuit capable of controlling the amount of delay of the present invention, FIG. 2(a) is a circuit diagram showing an example of a variable delay circuit of the present embodiment, and FIG. 2(1) ) is the input data i for the values of the delay amount control input data 01 to On input to this variable delay circuit. FIG. 3 is a waveform diagram showing the relationship between the waveform of output data m It is a diagram. LO, Ll...variable delay circuit, Do, Dl...data input terminal, KO, 1...data output terminal, R...ROM. 30.31...Decoder, PO~PT...ROM address input terminal, AO, AJ
, BO, BJ...control input terminal, ANo, AN1~
ANm, No, N+ ~Nn -...AND element, OR...OR element 01~On, n+1-2n・ROM output terminal, io,
Top 1...Input data, mQ, ml...Output data, aO~am...Output data of AND element ANo"ANm, C1~Cn, U+~un...Delay product control input data. 1st 7.11j IF Uchihara (a)

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit that has a variable delay circuit that can control the amount of delay by a delay amount control input and transmits parallel data, storing data for controlling the amount of delay of the variable delay circuit; A semiconductor integrated circuit capable of controlling a delay amount, comprising a ROM that outputs delay amount control data corresponding to a designated address to a variable delay circuit.