JPH0320099U

JPH0320099U -

Info

Publication number: JPH0320099U
Application number: JP7729189U
Authority: JP
Priority date: 1989-06-30
Filing date: 1989-06-30
Publication date: 1991-02-27

Description

[Brief explanation of drawings]

第１図は、従来の半導体メモリー回路固定ソケ
ツトの配置図。第２図は、本考案の半導体メモリ
ー回路固定を示す図。第３図は、半導体メモリー
回路収納ケース図。第４図は、本考案の概略図。１……収納舌型板接触溝、２……半導体メモリ
ー回路固定凸部、３……収納舌型板、４……半導
体メモリー回路固定ソケツト、５……半導体メモ
リー回路収納ケース、６……半導体メモリー回路
（ＤＩＰタイプ、書き込み可能）。 FIG. 1 is a layout diagram of a conventional semiconductor memory circuit fixing socket. FIG. 2 is a diagram showing the fixing of the semiconductor memory circuit of the present invention. Figure 3 is a diagram of the semiconductor memory circuit storage case. FIG. 4 is a schematic diagram of the present invention. DESCRIPTION OF SYMBOLS 1... Storage tongue template contact groove, 2... Semiconductor memory circuit fixing convex part, 3... Storage tongue template, 4... Semiconductor memory circuit fixing socket, 5... Semiconductor memory circuit storage case, 6... Semiconductor Memory circuit (DIP type, writable).

Claims

[Scope of utility model registration request]

In a semiconductor memory read/write device in which a semiconductor memory circuit (DIP type, writable) is attached to a socket part of the semiconductor memory read/write device to read and write data and programs, when the semiconductor memory circuit is fixed to the semiconductor memory read/write device, the semiconductor memory A semiconductor memory read/write device characterized by a structure in which sockets for fixing circuit leads are arranged in a line.