JPH03198420A - Logic integrated circuit - Google Patents
Logic integrated circuitInfo
- Publication number
- JPH03198420A JPH03198420A JP1339655A JP33965589A JPH03198420A JP H03198420 A JPH03198420 A JP H03198420A JP 1339655 A JP1339655 A JP 1339655A JP 33965589 A JP33965589 A JP 33965589A JP H03198420 A JPH03198420 A JP H03198420A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- reference voltage
- potential
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は論理集積回路に関し、特に電流切換型論理回路
を搭載した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic integrated circuit, and particularly to a semiconductor device equipped with a current switching type logic circuit.
従来の電流切換型論理回路には、2種類の入出力論理レ
ベルのものがあるが、一つの電流切換型論理回路におい
ては入出力論理レベルは固定されている。Conventional current switching type logic circuits have two types of input/output logic levels, but in one current switching type logic circuit, the input/output logic level is fixed.
上述した従来の電流切換型論理回路は、1種類の論理レ
ベルのみを有しているので論理レベルの異なる2種類の
ものを混用した場合若干のレベル差等が存在するため、
動作マージンの縮小がはなはだしい場合は誤動作すると
いう欠点が有った。The conventional current switching type logic circuit described above has only one type of logic level, so when two types of logic levels are used together, there will be a slight level difference, etc.
There is a drawback that malfunctions occur if the operating margin is significantly reduced.
本発明の論理集積回路は、基準電圧設定信号と電源電圧
を比較する比較回路と、前記比較回路の出力信号で択一
的に駆動される第1基準電圧発生回路及び第2基準電圧
発生回路と、前記第1基準電圧発生回路及び第2基準電
圧発生回路の出力端の共通接続点の電位をしきい電圧と
する論理回路と、前記論理回路の出力端に並列に接続さ
れた第1出力回路及び第2出力回路と、前記比較回路の
出力信号を受けて前記第1出力回路及び第2出力回路の
いずれか一方を選択して駆動状態にする出力切換回路と
を有するというものである。The logic integrated circuit of the present invention includes a comparison circuit that compares a reference voltage setting signal and a power supply voltage, and a first reference voltage generation circuit and a second reference voltage generation circuit that are selectively driven by an output signal of the comparison circuit. , a logic circuit whose threshold voltage is a potential at a common connection point of the output ends of the first reference voltage generation circuit and the second reference voltage generation circuit, and a first output circuit connected in parallel to the output ends of the logic circuit. and a second output circuit, and an output switching circuit that selects either the first output circuit or the second output circuit and puts it into a driving state upon receiving the output signal of the comparison circuit.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の構成を示すプロ、り図、第2図は本発
明の一実施例を示す回路図である。FIG. 1 is a schematic diagram showing the configuration of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
比較回路lは、電源電゛圧VEEを抵抗比t、aZで分
割し、基準電圧設定信号入力端子9の電位と比較する。The comparison circuit 1 divides the power supply voltage VEE by the resistance ratio t, aZ and compares it with the potential of the reference voltage setting signal input terminal 9.
第1基準電圧発生回路2はある基準電圧VRIを発生す
る回路であり、第2基準電圧発生回路3は他の基準電圧
V凡2(温度補償されているものとする)を発生する回
路である。入力回路4はECL型論理回路で、入力信号
端子11の電位を、第1基準電圧発生回w!52及び第
2基準電圧発生回路3の出力端の共通接続点の電位をし
きい電圧として増幅し、内部回路5(ECL型論理回路
)に供給する。内部回路5の出力端に並列に接続された
第1出力回路7.第2出力回路8はいずれも電流切換型
回路とその出力信号をエミッタホロワで取り出すトラン
ジスタとで構成されている。なお、第2出力回路8には
、逆並列に接続されたダイオードDl、D2及び抵抗R
IOからなる温度補償回路がついている。出力切換向w
I6は、比較回路lの出力信号を受けて、第1出力回路
7゜第2出力回路8のいずれか一方を選択して駆動状態
にする回路である。The first reference voltage generation circuit 2 is a circuit that generates a certain reference voltage VRI, and the second reference voltage generation circuit 3 is a circuit that generates another reference voltage V2 (assumed to be temperature compensated). . The input circuit 4 is an ECL type logic circuit, and changes the potential of the input signal terminal 11 to the first reference voltage generation time w! 52 and the common connection point of the output ends of the second reference voltage generation circuit 3 is amplified as a threshold voltage and supplied to the internal circuit 5 (ECL type logic circuit). A first output circuit 7 connected in parallel to the output end of the internal circuit 5. Each of the second output circuits 8 is composed of a current switching type circuit and a transistor from which an output signal is taken out by an emitter follower. Note that the second output circuit 8 includes diodes Dl and D2 and a resistor R connected in antiparallel.
It has a temperature compensation circuit consisting of IO. Output switching direction w
I6 is a circuit that receives the output signal of the comparator circuit 1, selects either the first output circuit 7 or the second output circuit 8, and puts it into a driving state.
次に動作について説明する。Next, the operation will be explained.
VEE=−5,2Vのとき、トランジスタQlのペース
電位より高い電位を基準電圧設定信号入力端子9に与え
ると、トランジスタQlはオフとなり、トランジスタQ
2はオンとなる。トランジスタQ3のペース電位は低く
なりトランジスタQ3はオフとなる。トランジスタQ4
のペース電位は接地電位となりトランジスタQ4はオン
となり、第2基準電圧発生回路3が駆動され基準電圧■
几2を入力回路4.内部回路5.第1出力回路7.第2
出力回路に供給する。又、トランジスタQ7のペース電
位は接地電位より抵抗R4の電圧降下分だけ低くなって
いるが、その電位より基準電圧VR3を高くしておくと
Qlはオフ、Q8はオンとなり、トランジスタQ14の
ペース電位が低下してQl4はオフとなる。従って出力
端子12の電位は第2出力回路8のトランジスタQ15
のエバツタ電位で与えられる。第2出力回路が選択され
るわけである。When VEE=-5.2V, if a potential higher than the pace potential of the transistor Ql is applied to the reference voltage setting signal input terminal 9, the transistor Ql is turned off, and the transistor Ql is turned off.
2 is turned on. The pace potential of transistor Q3 becomes low and transistor Q3 is turned off. Transistor Q4
The pace potential becomes the ground potential, turning on the transistor Q4, and the second reference voltage generation circuit 3 is driven to generate the reference voltage ■
Input circuit 2 to circuit 4. Internal circuit 5. First output circuit 7. Second
Supplies the output circuit. Also, the pace potential of transistor Q7 is lower than the ground potential by the voltage drop of resistor R4, but if the reference voltage VR3 is set higher than that potential, Ql is turned off and Q8 is turned on, and the pace potential of transistor Q14 is lowered by the voltage drop of resistor R4. decreases and Ql4 turns off. Therefore, the potential of the output terminal 12 is the same as that of the transistor Q15 of the second output circuit 8.
It is given by the evacuator potential of Therefore, the second output circuit is selected.
次に、VEE” 5vのとき、トランジスタQlのペ
ース電位より低い高位を基準電圧設定信号入力端子9に
印加すると、トランジスタQ3がオンし、基準電圧■ル
lが選択され、第1出力回路7が選択される。Next, when VEE" 5V is applied, when a high voltage lower than the pace potential of the transistor Ql is applied to the reference voltage setting signal input terminal 9, the transistor Q3 is turned on, the reference voltage l is selected, and the first output circuit 7 is turned on. selected.
以上、VEE=−5,2Vのとき、基準電圧■几2、第
2出力回路8が選択され、VEE=−5Vのとき基準電
圧VRt、第1出力回路7が選択される場合について説
明したが、VEE=−5,OVのとき、基準電圧vgt
、第1出力回路7が選択され、VEE =−5,2V6
D、!:i!!、基準電圧VR,2、第2出力回路8が
選択されるような動作も可能であるのはいうをまたない
。Above, we have explained the case where when VEE=-5.2V, the reference voltage 2 and the second output circuit 8 are selected, and when VEE=-5V, the reference voltage VRt and the first output circuit 7 are selected. , when VEE=-5, OV, the reference voltage vgt
, the first output circuit 7 is selected, VEE = -5, 2V6
D,! :i! ! , reference voltage VR,2, and second output circuit 8 are also possible.
以上説明したように本発明は、電流切換型論理回路に電
源電圧の比較回路と、2系統の基準電圧発生回路及び出
力回路を設ける事により2種類の使用電源電圧、入出力
論理レベルの異なる論理回路に組込み可能な論理集積回
路が得られる効果がある。As explained above, the present invention provides a current switching type logic circuit with a power supply voltage comparison circuit and two systems of reference voltage generation circuits and output circuits, so that two types of power supply voltages and logics with different input/output logic levels can be generated. This has the effect of providing a logic integrated circuit that can be incorporated into a circuit.
第1図は本発明の構成を示すブロック図、第2図は本発
明の一実施例の回路図である。
l・・・・・・比較回路、2・・・・・・第1基準電圧
発生回路、3・・・・・・第2基準電圧発生回踊、4°
°°゛°°入力回路・5・・・・・・内部回路、6・・
・・・・出力切換回路、7・・・・・・第1出力回路、
8・・・・・・第2出力回路、9・・・・・・基準電圧
設定信号入力端子、10・・・・・・電圧切換信号線、
11・・・・・・入力信号端子、12・・・・・・出力
信号端子、DI、D2・・・・・・ダイオード、■1〜
14・・・・・・定電流源、Ql−Ql5・・・・・・
トランジスタ、R1−J’L1o0996.、抵抗、V
几1〜VR3・・・・・・基準電圧。FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. l...Comparison circuit, 2...First reference voltage generation circuit, 3...Second reference voltage generation circuit, 4°
°°゛°°Input circuit・5・・・・・・Internal circuit, 6・・
... Output switching circuit, 7... First output circuit,
8...Second output circuit, 9...Reference voltage setting signal input terminal, 10...Voltage switching signal line,
11...Input signal terminal, 12...Output signal terminal, DI, D2...Diode, ■1~
14... Constant current source, Ql-Ql5...
Transistor, R1-J'L1o0996. , resistance, V
几1~VR3・・・Reference voltage.
Claims (1)
記比較回路の出力信号で択一的に駆動される第1基準電
圧発生回路及び第2基準電圧発生回路と、前記第1基準
電圧発生回路及び第2基準電圧発生回路の出力端の共通
接続点の電位をしきい電圧とする論理回路と、前記論理
回路の出力端に並列に接続された第1出力回路及び第2
出力回路と、前記比較回路の出力信号を受けて前記第1
出力回路及び第2出力回路のいずれか一方を選択して駆
動状態にする出力切換回路とを有することを特徴とする
論理集積回路。a comparison circuit that compares a reference voltage setting signal and a power supply voltage; a first reference voltage generation circuit and a second reference voltage generation circuit that are selectively driven by the output signal of the comparison circuit; and the first reference voltage generation circuit. and a logic circuit whose threshold voltage is the potential at a common connection point of the output ends of the second reference voltage generation circuit, and a first output circuit and a second output circuit connected in parallel to the output ends of the logic circuit.
an output circuit, and a first
1. A logic integrated circuit comprising: an output switching circuit that selects either the output circuit or the second output circuit and puts it into a driving state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1339655A JPH03198420A (en) | 1989-12-26 | 1989-12-26 | Logic integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1339655A JPH03198420A (en) | 1989-12-26 | 1989-12-26 | Logic integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03198420A true JPH03198420A (en) | 1991-08-29 |
Family
ID=18329555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1339655A Pending JPH03198420A (en) | 1989-12-26 | 1989-12-26 | Logic integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03198420A (en) |
-
1989
- 1989-12-26 JP JP1339655A patent/JPH03198420A/en active Pending
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