JPH03196635A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To reduce a capacitance between a base and a collector, a current applied to the outer base and a base resistance simultaneously by a method wherein, after a high resistance layer and a base layer are built up, a protective film is formed on the outer base and impurities are introduced through the intrinsic base layer. CONSTITUTION:A heavily doped n-type GaAs layer 2 which is to be a collector contact region, a GaAs layer 2 which is heavily doped with n-type impurity, a high resistance GaAs layer 3 and a p-type doped GaAs layer 4 which is to be a base and an outer base region are built up on a semi-insulating GaAs substrate 1 by epitaxial growth. Then an SiO2 protective film 5 is formed on the surface except a part which is to be the intrinsic part of a transistor, Si<+> ions are implanted and activated by annealing. Si is activated an n-type impurity to form an n-type region 10 which is to be a collector. With this constitution, a part of the layer 4 on the high resistance GaAs layer 3 which is to be an outer base region 14B is not damaged by ion implantation in processes such as ion implantation and a base resistance and a capacitance between the base and the collector can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing bipolar transistors.

BACKGROUND OF THE INVENTION Bipolar transistors, which are key devices in ultra-high frequency communications and ultra-high-speed digital circuits, are being actively developed. The maximum oscillation frequency f taax, which is one of the performance indicators indicating the high speed performance of bipolar transistors, is calculated using the cutoff frequency ft, f max = ff f t/
8 yr RbCbcRb: Base resistance Cbc: Represented by base-collector capacitance. In order to obtain a high f wax, ft must be increased and Rb and Cbc must be decreased.

Heterojunction uses a semiconductor with a larger bandgap than the base for the emitter as a bipolar transistor that can shorten the base length to increase ft and lower base resistance to increase fmax. There is a bipolar transistor (hereinafter referred to as rHBTJ).

A conventional example of the HBT manufacturing method will be explained with reference to the drawings. As shown in Figure 2(a), semi-insulating GaAs
On the substrate 21, a heavily n-type GaAs layer 22, n
Type-doped GaAs layer 23, p-type doped Cj
aAs layer 2.4, n-type doped AlGaAs layer 25
, emitter electrode 4! form.

Next, as shown in FIG. 4B, dry etching is performed using the emitter electrode 41 as a mask to expose the p-type GaAs layer 24. After that, in order to reduce the capacitance between the base and the collector, a p-type GaAs layer 24 which becomes an external base layer is
Through this, hydrogen ions are implanted to form a high resistance region 3B. Subsequently, photolithography and etching are performed to form a transistor structure, and as shown in FIG. 2C, a base electrode 42 and a collector electrode 43 are formed, respectively. 31 is a collector contact region, 32 is a collector region, 33A is a base region made of layer 24, 33B
34 is an emitter region, 35 is an emitter region, and 44 is an element isolation region.

Problems to be Solved by the Invention However, in the manufacturing method described above, in order to reduce the base-collector capacitance in an emitter-top type bipolar transistor, the flow from the emitter to the external base in the collector-top type bipolar transistor is reduced. When ion implantation is performed through the layer that serves as the external base in order to reduce the current, there is a problem that the layer 24 that serves as the external base is damaged and the resistance of the external base region 33B becomes high, increasing the base resistance. .

The present invention solves these problems by simultaneously reducing the base-collector capacitance and base resistance in an emitter-top type bipolar transistor, and reducing the current flowing from the emitter to the external base in the collector-top type bipolar transistor. The present invention provides a method for manufacturing a bipolar transistor that can reduce the base resistance and the base resistance at the same time.

Means for Solving the Problems In order to solve the above problems, in the present invention, after laminating a high resistance layer and a base layer, a protective film is formed on the external base except for the intrinsic base part, and the intrinsic base layer is A feature is that a collector (emitter) region is formed by introducing impurities through the layer.

Function: In the method for manufacturing a bipolar transistor described above, since a high resistance layer exists under the external base layer and the protective film serves as a mask against the introduction of impurities, the external base layer is not damaged either. Therefore, in the emitter top type,
Reduce base-collector capacitance and base resistance at the same time.
In the collector top type, it is possible to simultaneously reduce the current flowing from the emitter to the external base and the base resistance.

EXAMPLE Hereinafter, a method for manufacturing a bipolar transistor according to an example of the present invention will be described with reference to the drawings.

As shown in FIG. 1(a), a semi-insulating GaAs substrate 1 is covered with a highly n-type doped GaAs layer 2 that will serve as a collector contact region, a high-resistance GaAs layer 3, and a p-type GaAs layer that will serve as a base and external base region. After epitaxially growing the doped GaAs layer 4, a protective film 5 made of 5102 is formed except for the part that will become the intrinsic part of the transistor.
By implanting Si” and annealing for activation, the St
It is activated as a type impurity to form an n-type region 10 that becomes a collector.

The lower part of the protective film 5 (external base region forming part) is not implanted with Si" because the protective film serves as a mask.

Next, as shown in the same figure (b), a p-type doped thin GaAs layer 6, an n-type doped AlGaAs layer 7 which becomes an emitter region with a wider forbidden band width than the base, and an emitter contact region. Highly doped n-type GaAs
A layer 8 is grown epitaxially on the region that will become the intrinsic part of the transistor, and an emitter electrode material 9 is deposited over the entire surface.

At this time, the semiconductor layer stacked on the protective film 5 is amorphous. Thereafter, as shown in FIG. 2C, the 5102 protective film 5 is removed together with the semiconductor layer thereon and the emitter electrode material using hydrofluoric acid. Next, a transistor is manufactured by photolithography and etching similar to conventional methods. The completed diagram is shown in figure (d). I0 is a collector region, 12 is a collector contact region, 14A is a base region, 14B is an external base region, 17 is an emitter region, +8 is an emitter contact region, Ift is a base electrode, 19 is a collector electrode, and 20 is an element isolation region. .

According to the above method, the portion of the layer 4 that will become the external base region 14B on the high-resistance GaAs layer 3 is not damaged by ion implantation during the ion implantation process as in the conventional method.
It becomes possible to reduce the base resistance and the base-to-collector capacitance.

In the examples, a heterojunction made of AlGaAs/GaAs was used, but InAlAs/InGaAs or S
Other material systems such as l/Ge are also possible. It is also possible to use a bipolar transistor whose emitter and base are made of the same material.

In the embodiment, the emitter is provided above the collector, but it is also applicable to a so-called collector top type case in which the region IO is the emitter and the region 17 is the collector, and the collector is provided above the emitter. In this case, the current flowing from the emitter to the external base and the base resistance can be reduced.

In the example, the emitter electrode was formed by removing unnecessary parts of the emitter electrode material at the same time as the protective film, but it is also possible to form the emitter electrode by photolithography and a lift-off method after removing the protective film. It is possible.

In the embodiment, an ion implantation method was used as a method for introducing impurities, but methods such as a diffusion method are also possible.

Effects of the Invention As described above, in the method for manufacturing a bipolar transistor of the present invention, in the emitter top type, the base-collector capacitance and base resistance can be reduced at the same time. You can get a transistor. Furthermore, in the collector top type, the current flowing from the emitter to the external base and the base resistance can be reduced at the same time, so a bipolar transistor with excellent DC current amplification factor and high frequency characteristics can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) show HBTs in embodiments of the present invention.
FIGS. 2(a) to 2(C) are cross-sectional views showing a conventional HBT manufacturing method. 1... Semi-insulating GaAs substrate, 2...
n-type highly doped GaAs layer, 3...high resistance GaA
s layer, 4...p-type GaAs layer, 5...
Slo? Protective film, 8...p-type GaAs layer,
7...N-type AlGaAs layer, 8...
n-type highly doped GaAs layer, 9... emitter electrode material, 10... n-type region (collector region), I
2... Collector contact 'AXtt4.14
A... Base area, 14B...External base area, 16
...Base electrode, 17 ... Emitter region, 18 ... Emitter contact region, 19.
... Collector electrode, 20 ... Element isolation region.

Claims (3)

[Claims] (1) A step of sequentially stacking at least a first semiconductor layer and a second semiconductor layer for forming a base region having a first conductivity type from the substrate side, and an intrinsic base layer on the second semiconductor layer. After forming a protective film except for the region, introducing an impurity into the first semiconductor layer through the intrinsic base region to stack at least a third semiconductor layer having a second conductivity type; A method for manufacturing a bipolar transistor, comprising the steps of removing a protective film and at least the third semiconductor layer on the protective film. (2) The step of laminating an electrode material on the third semiconductor layer, and the step of removing the protective film and at least the third semiconductor layer and the electrode material on the protective film. A method for manufacturing a bipolar transistor according to claim 1. (3) A method for manufacturing a bipolar transistor according to claim 1, wherein the method for introducing impurities is an ion implantation method.