JPH0319640B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a nonvolatile semiconductor memory device as a rewritable read-only memory.

(Prior art) Writing to a rewritable non-volatile semiconductor memory device (hereinafter referred to as EPROM) is performed using the source
This is done by injecting and accumulating hot electrons generated between the drains into the floating gate. FIG. 3 shows a cross-sectional view of an n-channel MIS field effect transistor (hereinafter referred to as n-MIST) having a floating gate as an EPROM memory transistor. 1 is a P-type substrate, 2 and 3 are n-type drains and sources, and 5 is a floating gate, which is wrapped and insulated between a first gate oxide film 4 and a second gate oxide film 6. 7 is a control gate.

For write operation, source 3 and substrate 1 are grounded, control gate 7 is applied approximately 20V, and drain 2 is applied approximately 10V.
By applying the voltage , hot electrons generated in a depletion layer region (pinch-off region) formed under the first gate oxide film 4 near the drain 2 are injected and accumulated in the floating gate 5.

FIG. 4 shows a circuit diagram of a conventional EPROM.
For writing, apply approximately 20v to the power supply V _PP and connect the row line
Apply a voltage of approximately 20v to the write control signal Di
As, the preset program time t _w
When a voltage of approximately 20V is applied during the period, the column line Y becomes n-
The voltage reaches approximately 10V, which is determined by the load characteristics of MISTQ ₂ , and memory transistor Q ₁ turns on, injecting hot electrons into the floating gate.

As EPROMs become increasingly integrated and the memory capacity per chip increases, the data write time, ie, the program time _tw , becomes a problem. For example, if you write with a pulse width of 50 msec per byte, it will take 14 to 15 minutes (819.2 seconds + α) on a chip with a memory capacity of 128 Kbits (16 Kbytes).
Shortening the writing time is essential. However, the conventional technology has major drawbacks in this respect. The disadvantages of the prior art will be explained below.

Figure 5 shows the amount of hot electrons flowing into the floating gate, that is, the floating gate potential of the injection current I _G.
V shows _FG dependence. The injection current I _G is at its maximum when the floating gate potential V _FG is approximately equal to the drain potential V _D , and is characterized in that I _G decreases as V _FG decreases.

The floating gate 5 in FIG. 3 is connected to the control gate 7 and the substrate 1.
As shown in Fig. 6, there is a capacitive coupling between the floating gate-control gate capacitance _C2 and the floating gate-substrate capacitance _C1 , and the potential _VFG of the floating gate 5 is injected and accumulated in the floating gate. When the amount of charge stored in the capacitor is Q _F , the potential applied to the control gate 7 is V _CG , the charge stored in the capacitor C ₂ is Q ₂ , and the charge stored in the capacitor C ₁ is Q ₁ , Q ₂ =C ₂ (V _FG - V _CG ), Q ₁ = C ₁ V _FG , and the charge accumulated in the floating gate Q _F = Q ₁ + Q ₂ , so Q _F = C ₂ (V _FG - V _CG ) + C ₁ V _FG Solving this equation for V _FG gives V _FG ≒C ₂ V _CG +Q _F /C ₁ +C ₂ ≡f(Q _F )...(1), and the floating gate potential V _FG is equal to the amount of charge Q _F of the accumulated electrons. One-on-one correspondence. Since this Q _F is the electrons accumulated in the floating gate, it has a negative value,
The larger this value is, the lower V _FG becomes. In Figures 4 and 6, the floating gate-control gate capacitance
If C ₂ and the floating gate-to-substrate capacitance C ₁ are made equal, then
When approximately 20v is applied to the row line X and approximately 10v to the column line Y, the floating gate potential V _FG is initially approximately 10v.
Therefore, it becomes equal to the column line potential, that is, the drain potential, and the maximum injection current I _G is obtained.

However, since the row line potential, that is, the control gate potential V _CG is constant, as hot electrons are injected and accumulated in the floating gate, Q _F increases, the floating gate potential V _FG decreases, and the injection current I _G decreases. In other words, when writing starts, the injection current I _G
begins to decrease, and as writing progresses, the injection current I _G decreases, making this a very inefficient writing method. Therefore, the programming time _tw requires a long time, and as the capacity increases, the increase in chip write time becomes a serious problem.

(Objective of the Invention) An object of the present invention is to provide a rewritable nonvolatile semiconductor memory device that eliminates the above-mentioned drawbacks and can realize highly reliable short-time writing.

(Structure of the Invention) A nonvolatile semiconductor memory device of the present invention has a single conductive conductor having a memory function in which one electrode is connected to a column line, the other electrode is connected to a first power supply, and a gate electrode is connected to a row line. a first MIS field effect transistor of the type, one electrode connected to the first connection point, the other electrode connected to the column line or the column line via a selection circuit, and a write control signal as a gate input; and a second MIS field effect transistor of one conductivity type, a first current mirror having an input terminal connected to the first connection point and an output terminal connected to the second connection point. a second current mirror circuit whose input terminal is connected to a dummy current source that generates a predetermined current and whose output terminal is connected to the second connection point;
a third MIS field effect transistor of opposite conductivity type, a gate electrode connected to the second connection point, one electrode connected to the row line, and a row line selection signal input to the other electrode; It is configured to include a load element connected between the second power supply.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The memory transistor _Q11 consists of an n-MIST having a memory function, its source is grounded (first power supply), its drain is connected to the column line Y, and the source of the n- _MISTQ12 whose gate input is the write control signal Di is Connected to column line Y, drain is connected to connection point 15
It is connected to the. A first current mirror circuit 8 has an input terminal 11 connected to a connection point 15 and an output terminal 12 connected to a connection point 16. and,
The first current mirror circuit 8 has a drain and a gate connected to the input terminal 11, and a source connected to the V _PP power supply (the third
p-MISTQ ₁₄ whose gate is connected to input terminal 11 and whose drain is connected to output terminal 1
p- connected to 2 and source connected to V _PP supply
MISTQ ₁₅ and p-MISTQ 14 and Q 15 are set to the same dimension, and p-MISTQ ₁₄ and Q ₁₅ are set to the same dimension.
It has a function of causing a current of i ₁ to flow through p-MISTQ ₁₅ when a current of i ₁ flows through MISTQ ₁₄ . Therefore, if the current I _M flows through the memory transistor Q ₁ , the current I _M will also flow through the p-MISTQ ₁₅ .

A second current mirror circuit 9 has an input terminal 14 connected to a dummy current source 10 that generates a predetermined current, and an output terminal 13 connected to a connection point 16. The second current mirror circuit 9 has a drain and a gate connected to the input terminal 14, and a source grounded (second power supply).
It consists of MISTQ ₁₆ and n-MISTQ ₁₇ whose gate is connected to input terminal 14, drain is connected to output terminal 13, and source is grounded.
MISTQ ₁₆ and Q ₁₇ are set to the same dimension, and if a current of i ₂ flows through n-MISTQ ₁₆ , n
- Has the function of trying to cause a current of i ₂ to flow through MISTQ ₁₇ . Since the input terminal 14 is connected to the dummy current source 10, if the set current of the dummy current source 1 is _IO , a current of _IO will flow through the n-MISTQ ₁₇ .

The output terminal 12 of the first current mirror circuit 8 and the second
The output terminal 13 of the current mirror circuit 9 is connected to the connection point 16
As shown in FIG. 2, the potential at the connection point 16 becomes a potential V ₁₆ determined by the balance between the current characteristics of the p-MISTQ ₁₅ and the n-MISTQ ₁₇ . In other words, the current iQ ₁₅ to be applied to p-MISTQ ₁₅ is
If the current iQ ₁₇ to be applied to n-MISTQ ₁₇ is larger, V ₁₆ becomes high, and conversely, if iQ 17 is larger than iQ ₁₅ , _{V 16 becomes} low. This means that if the current I _M flowing through the memory transistor Q ₁₁ is smaller than the preset current I _O of the dummy current source,
This means that V ₁₆ will be low, and conversely if I _M is greater than I _O , V ₁₆ will be high.

_Q13 is a p-MIST whose drain is connected to the row line X, whose gate is connected to the connection point 16, and when the row line selection signal Xi is input to the source and selected, a high potential is applied. _R1 is a load element connected between the row line X and ground (second power supply). When V ₁₆ decreases, the conductance of p-MISTQ ₁₃ increases and the row line
The potential of increases. Conversely, when V ₁₆ increases, p-
The conductance of MISTQ ₁₃ deteriorates and the potential of the row line X decreases. Therefore, from the preset dummy current source current I _O , the memory transistor Q ₁₁
If the current I _M is small, the potential of the row line X increases,
If I _M is larger than I _O , the row line potential decreases and I _M becomes I _O
try to make it the same as

Now, to write memory transistor _Q11 ,
Assume that the V _PP power supply is approximately 20 V, and from the load characteristics of the n-MISTQ ₁₂ , the potential of the column line Y, that is, the drain potential V _D of the memory transistor Q ₁₁ is approximately 10 V.
At this time, the injection current of hot electrons is largest when the floating gate potential V _FG is approximately the drain potential V _D as shown in Figure 5, that is, approximately 10 V.
It's time. In the simplest approximation, the current I _M flowing through the memory transistor Q ₁₁ is I _M ≒ β/2 (V _FG − V _T ) ² …(2) where V _T is the threshold voltage seen from the floating gate, β ; is a constant determined by the design of MIST, and has a one-to-one correspondence with the floating gate potential V _FG . Therefore, the current I _O of the dummy current source is reduced to the floating gate potential V _FG
If the current I _M | V _D flowing through the memory transistor Q ₁₁ is set to 10 when is 10 V, the current I _M flowing through the memory transistor Q ₁₁ will be maintained at I _M | V _D = 10, and therefore V _FG is kept at 10v.

Actually, in memory transistor _Q11 , V _D
Writing starts when V _FG is 10 V and V FG is 10 V. When hot electrons are injected into the floating gate and V _FG decreases, I _M decreases and the set current I _O of the dummy current source decreases.
(=I _M |V _D =10), the potential of the row line X rises, and V _FG rises due to capacitive coupling and remains at 10V. Therefore, V _FG can always be made equal to V _D , and the maximum injection current can always be obtained during the programming time.

In order for the written memory cell to be determined to be in the written state without error, the threshold voltage V _TM seen from the control gate of the memory transistor must be sufficiently high, and V _TM is V _TM = C It is expressed as ₁ +C ₂ /C ₂ V _T −Q _F /C ₂ ...(3) and has a one-to-one correspondence with Q _F. Now, if the threshold voltage V _TM at which it can be judged that stable writing has been performed with sufficient consideration given to reliability is V _TMS , a charge greater than Q _FS shown in the following equation is injected and accumulated in the floating gate, and Q _FS = (C ₁ +C ₂ )V _T −C ₂ V _TMS …(4) would be satisfactory. According to the invention, the injection current I _G
Since is always the maximum injection current I _G max, the programming time t _w required to write to the threshold voltage V _TMS at which it can be determined that stable writing has been performed with due consideration to reliability is t _w = Q _FS / I _G max ...(5) Therefore, the programming time t _w can be significantly shortened.

Note that it is more effective to achieve 30 to 40 V for the row line selection signal Xi in Figure 1 by using a high potential supplied from a power source separate from the V _PP power supply, or a high potential generated from a booster circuit. be. Further, the first power supply connected to the source of the memory transistor _Q11 does not necessarily need to be grounded, and the same effect can be obtained even if it is set to a low voltage of approximately 0.5 to 1.5V.

Furthermore, the source of n-MISTQ ₁₂ and the drain of memory transistor Q ₁₁ are used for selection as a selection circuit whose gate input is the column line selection signal Xi.
It can be easily inferred that even connection via MIST is included in the present invention.

(Effects of the Invention) As described above in detail, according to the present invention,
With the above configuration, a highly reliable, short-time writable and rewritable nonvolatile semiconductor memory device can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the main part of an embodiment of the present invention, Fig. 2 is a principle diagram for explaining the connection point potential, and Fig. 3 is an n-channel with a floating gate.
A cross-sectional diagram showing an example of a MIS field effect transistor,
Fig. 4 is a circuit diagram showing the configuration of a conventional EPROM, Fig. 5 is a characteristic diagram showing the floating gate potential dependence of the injection current of the MIS field effect transistor of Fig. 3, and Fig. 6
The figure shows the capacitive coupling between the control gate, floating gate, and substrate. DESCRIPTION OF SYMBOLS 1...p-type substrate, 2...drain, 3...source, 4...first gate oxide film, 5...floating gate, 6...second gate oxide film, 7...control gate, 8 ...First current mirror circuit, 9...Second current mirror circuit, 10...Dummy current source, 11,
14... Input terminal of current mirror circuit, 12, 13
...Output terminals of the current mirror circuit, 15, 16...
Connection point, C ₁ ...Floating gate-substrate capacitance, C ₂ ...
...Capacitance between floating gate and control gate electrode, Di...
Write control signal, I _D ……Drain current, Q ₁ ,
Q ₁₁ ... memory transistor, Q ₂ , Q ₁₆ , Q ₁₇ ...
n-channel MIS field effect transistor, _Q13 ,
Q ₁₄ , Q ₁₅ ... p-channel MIS field effect transistor, R ₁ ... load element, V _D ... drain voltage,
V ₁₆ ...Potential of connection point 16, V _PP ...Power supply, X...
...Row line, Xi...Row line selection signal, Y...Column line.

Claims (1)

[Claims] 1. A first MIS field effect of one conductivity type having a memory function in which one electrode is connected to a column line, the other electrode is connected to a first power supply, and the gate electrode is connected to a row line. a transistor, and a second MIS of one conductivity type, one electrode of which is connected to the first connection point, the other electrode of which is connected to the column line or the column line via a selection circuit, and has a write control signal as a gate input. a field effect transistor; a first current mirror circuit having an input terminal connected to the first connection point and an output terminal connected to the second connection point; and a predetermined current a second current mirror circuit whose input terminal is connected to a dummy current source that generates the current and whose output terminal is connected to the second connection point, and whose gate electrode is connected to the second connection point and whose one electrode is connected to the second connection point; A third electrode of the opposite conductivity type is connected to the row line and receives the row line selection signal as the input of the other electrode.
A nonvolatile semiconductor memory device comprising an MIS field effect transistor and a load element connected between the row line and a second power source. 2 The first current mirror circuit connects a fourth MIS field effect transistor of opposite conductivity type, with one electrode and the gate electrode connected to the input terminal and the other electrode connected to the third power supply, and the gate electrode connected to the input terminal. a fifth electrode of opposite conductivity type connected to the terminal, the other electrode connected to the third power supply, and one electrode connected to the output terminal.
MIS field effect transistor, and the second current mirror circuit is a sixth MIS field effect transistor of one conductivity type, in which one electrode and the gate electrode are connected to the input terminal and the other electrode is connected to the second power supply. A patent claim consisting of a transistor and a seventh MIS field effect transistor of one conductivity type, whose gate electrode is connected to an input terminal, the other electrode is connected to a second power source, and one electrode is connected to an output terminal. The nonvolatile semiconductor memory device according to scope 1.