JPH03196355A - Parallel computer - Google Patents
Parallel computerInfo
- Publication number
- JPH03196355A JPH03196355A JP1337940A JP33794089A JPH03196355A JP H03196355 A JPH03196355 A JP H03196355A JP 1337940 A JP1337940 A JP 1337940A JP 33794089 A JP33794089 A JP 33794089A JP H03196355 A JPH03196355 A JP H03196355A
- Authority
- JP
- Japan
- Prior art keywords
- substrates
- processor
- torus network
- dummy
- parallel computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008878 coupling Effects 0.000 claims abstract description 5
- 238000010168 coupling process Methods 0.000 claims abstract description 5
- 238000005859 coupling reaction Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 abstract 13
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は、複数のプロセッサ基板をトーラス網形式で
相互結合し、構成した並列計算機に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a parallel computer configured by interconnecting a plurality of processor boards in a torus network format.
第２図は複数のプロッサを相互結合するトーラス網を示
す図であり、並列計算機を構成する各プロセッサ（１，
）は、トーラス網方式を採る相互結合網にて各々相互結
合されている・
第３図は従来のトーラス網実現方式を示す図であり、マ
ザーボード（４）に複数のプロセッサ基板（３）が実装
され、各プロセッサ基板（３）はマザーボード（４）中
で相互結合網にて相互結合される。FIG. 2 is a diagram showing a torus network that interconnects multiple processors, and shows each processor (1, 1,
) are each interconnected by an interconnection network that adopts a torus network method. Figure 3 is a diagram showing a conventional torus network implementation method, in which multiple processor boards (3) are mounted on a motherboard (4). Each processor board (3) is interconnected in an interconnection network within the motherboard (4).
実際マザーボード（４）には各プロセッサ基板（３）を
相互結合する相互結合網がプリント配線され、該プリン
ト配線によって各プロセッサ基板（３）を相互結合する
ことで第２図に示すトーラス網が実現する。In fact, an interconnection network is printed on the motherboard (4) that interconnects each processor board (3), and by interconnecting each processor board (3) using the printed wiring, the torus network shown in Figure 2 is realized. do.
（発明が解決しようとする課題〕
従来の並列計算機は、以上のように構成されているため
、トーラス網を構成するプロセッサ数はマザーボードの
配線により固定であり、プロセッサ数を可変する為には
、そのプロセッサ数に応じたトーラス網を実現する必要
がある。(Problem to be Solved by the Invention) Conventional parallel computers are configured as described above, so the number of processors that make up the torus network is fixed by wiring on the motherboard, and in order to vary the number of processors, It is necessary to realize a torus network corresponding to the number of processors.
この発明は上記のような問題点を解消するためになされ
たもので、マザーボード上のトーラス接続に変更を加え
ることなくプロセッサの数に応じたトーラス網を容易に
実現できる並列計算機を得ることを目的とする。This invention was made to solve the above-mentioned problems, and the purpose is to obtain a parallel computer that can easily realize a torus network according to the number of processors without changing the torus connection on the motherboard. shall be.
この発明に係る並列計算機は、並列計算機を構成する複
数のプロセッサ用基板とともに、これらプロセッサ用基
板を相互結合する信号線網を配設したダミー基板をマザ
ーボードに立設したものである。The parallel computer according to the present invention includes a plurality of processor boards constituting the parallel computer, and a dummy board on which a signal line network for interconnecting these processor boards is installed upright on the motherboard.
この発明によれば、マザーボード上て実装されないプロ
セッサ基板の代わりにダミー基板を実装することで、プ
ロセッサ基板間の相互結合信号をダミー基板によって中
継し、トーラス網を実現することができる。According to this invention, by mounting a dummy board in place of a processor board that is not mounted on a motherboard, mutual coupling signals between processor boards can be relayed by the dummy board, and a torus network can be realized.
以下、この発明の一実施例を図について説明する。第１
図は本実施例における並列計算機の構成図である。複数
のプロセッサ基板（３）・・・（３）と図示しないマザ
ーボードに実装されたダミー基板（５）は、各プロセッ
サ基板（３）・・・（３）間の相互結合信号を中継し、
トーラス網を実現する基板である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a configuration diagram of a parallel computer in this embodiment. A plurality of processor boards (3)...(3) and a dummy board (5) mounted on a motherboard (not shown) relay mutual coupling signals between each processor board (3)...(3),
This is a board that realizes a torus network.
次に、本実施例の作用について説明する。図に示す横方
向のプロセッサ基板間を信号によって相互結合する場合
は、各プロセッサ基板間にダミー基板を実装し、該ダミ
ー基板により、プロセッサ基板間の信号を中継すること
で、現在マサ−ボードに実装されている数のプロセッサ
基板のみでトーラス網を形成することができる。Next, the operation of this embodiment will be explained. When interconnecting processor boards in the horizontal direction shown in the figure using signals, a dummy board is mounted between each processor board, and the dummy board relays signals between the processor boards. A torus network can be formed using only the number of processor boards mounted.
又、上記実施例ては横方向のプロセッサ基板間の相互結
合信号を中継する場合を示したが、ダミー基板に配設し
た中継線路によって、各方向のプロセッサ基板間の相互
結合信号を中継することができ、数々のプロセッサ数の
トーラス網を実現することができる。Further, although the above embodiment shows a case in which mutually coupled signals between processor boards in the horizontal direction are relayed, mutually coupled signals between processor boards in each direction may be relayed by a relay line arranged on a dummy board. It is possible to realize a torus network with a large number of processors.
以上のように、この発明によれば各プロセッサ基板間を
中継線路を配設したり′ミー基板を介して相互結合する
構成としたので、基板を実装するマザーボードの配線を
変更せずとも、数々のプロセッサから構成される並列計
算機が容易かつ安価にできる効果がある。As described above, according to the present invention, each processor board is configured to be connected to each other via a relay line or a base board, so that it is possible to perform various This has the effect that a parallel computer consisting of several processors can be easily and inexpensively created.
第１図はこの発明の一実施例による並列計算機の構成方
式を示した図、第２図は従来のトーラス網による並列計
算機を示した図、第３図は従来のトーラス網実現方式を
示す図である。
図において、（１）はプロセッサ、（２）は相互結合網
、（３）はプロセッサ基板、（４）はマザーボート、（
５）はダミー基板。
尚、図中同一符号は同−又は相当部分を示す。FIG. 1 is a diagram showing a configuration method of a parallel computer according to an embodiment of the present invention, FIG. 2 is a diagram showing a parallel computer using a conventional torus network, and FIG. 3 is a diagram showing a conventional torus network implementation method. It is. In the figure, (1) is a processor, (2) is an interconnection network, (3) is a processor board, (4) is a motherboard, (
5) is a dummy board. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
、これらプロセッサ用基板を相互結合する信号線網を配
設したダミー基板をマザーボードに立設したことを特徴
とする並列計算機。1. A parallel computer comprising a plurality of processor boards constituting the parallel computer, and a dummy board on which a signal line network for mutually coupling these processor boards is installed on a motherboard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1337940A JPH03196355A (en) | 1989-12-26 | 1989-12-26 | Parallel computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1337940A JPH03196355A (en) | 1989-12-26 | 1989-12-26 | Parallel computer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03196355A true JPH03196355A (en) | 1991-08-27 |
Family
ID=18313433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1337940A Pending JPH03196355A (en) | 1989-12-26 | 1989-12-26 | Parallel computer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03196355A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015027320A1 (en) | 2013-08-29 | 2015-03-05 | Dan Oprea | Method and apparatus to manage the direct interconnect switch wiring and growth in computer networks |
-
1989
- 1989-12-26 JP JP1337940A patent/JPH03196355A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015027320A1 (en) | 2013-08-29 | 2015-03-05 | Dan Oprea | Method and apparatus to manage the direct interconnect switch wiring and growth in computer networks |
| JP2016532209A (en) * | 2013-08-29 | 2016-10-13 | ダン オプレア | Method and apparatus for managing the wiring and growth of direct interconnect switches in a computer network |
| EP3022879A4 (en) * | 2013-08-29 | 2017-03-01 | Dan Oprea | Method and apparatus to manage the direct interconnect switch wiring and growth in computer networks |
| AU2014311217B2 (en) * | 2013-08-29 | 2018-02-08 | Rockport Networks Inc. | Method and apparatus to manage the direct interconnect switch wiring and growth in computer networks |
| US10303640B2 (en) | 2013-08-29 | 2019-05-28 | Rockport Networks Inc. | Method and apparatus to manage the direct interconnect switch wiring and growth in computer networks |
| AU2018200155B2 (en) * | 2013-08-29 | 2019-09-26 | Rockport Networks Inc. | Method And Apparatus To Manage The Direct Interconnect Switch Wiring And Growth In Computer Networks |
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