JPH03195228A - Redundant system selecting circuit - Google Patents

Redundant system selecting circuit

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Publication number
JPH03195228A
JPH03195228A JP33743389A JP33743389A JPH03195228A JP H03195228 A JPH03195228 A JP H03195228A JP 33743389 A JP33743389 A JP 33743389A JP 33743389 A JP33743389 A JP 33743389A JP H03195228 A JPH03195228 A JP H03195228A
Authority
JP
Japan
Prior art keywords
data
circuit
data string
selection
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33743389A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Moriguchi
森口 好之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33743389A priority Critical patent/JPH03195228A/en
Publication of JPH03195228A publication Critical patent/JPH03195228A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To prevent momentary production of error for the selection of a data string of a redundant system and to eliminate the abnormality of both systems by providing 2-stage constitution for two 1st selective circuits and a 2nd selective circuit and providing a delay circuit between two stages. CONSTITUTION:DATA i (i=1-n) in a data string of same frame constitution having the redundant system is given to a 1st selective circuit 11 and a DATA ia (i=1-n) is inputted to a 1st selective circuit 12, an output data string is delayed respectively by delay circuits 13, 14 and inputted to a 2nd selective circuit 15. A selection control pulse is outputted from a control circuit 16 before a data string whose error is detected by a path pattern detection circuit 17 or 18 reaches the selective circuit 15 and the data string is subjected to selection control without causing momentary error in the transmission data string. In the selection control, the selective circuit 15 is controlled before the selection circuits 11, 12. After data strings DATA 1-n including the data string DATA j having a fault are switched by the selective circuit 15 and the selective circuit 11 selects a data string DATA k (not equal to j) and this system is in standby as a standby system.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、冗長系を有するディジタル通信分野において
、パスパタン検出による自己監視機能により冗長系を選
択する回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that selects a redundant system using a self-monitoring function based on path pattern detection in the field of digital communication having a redundant system.

〔従来の技術〕[Conventional technology]

従来、この種のO/1冗長系選択回路では、冗長系を有
するデータ列の瞬時誤りを伴なわない選択回路を実現し
得る回路構成ではなく、1つの系に障害が発生した直後
のパスパタン検出期間の間は正常な系へ切り替えられて
おらず、さらに、正常な系に切り替わった後は故障パネ
ルを保守しない限り片系運用となっており、更に運用中
のパネルが故障した場合には両系異常となる回路構成と
なっていた。
Conventionally, this type of O/1 redundant system selection circuit does not have a circuit configuration that can realize a selection circuit that does not cause instantaneous errors in data strings having a redundant system, but only detects a path pattern immediately after a failure occurs in one system. During this period, the system was not switched to the normal system, and after switching to the normal system, unless the failed panel was maintained, it would be one-sided operation, and if the panel in operation failed, both systems would be operated. The circuit configuration caused a system error.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の冗長系選択回路においては、冗長系を有
するデータ列と、その両系のデータ列のうち正常な系の
データを選択する制御パルスとが同じ位相遅延で選択回
路に入力されるためデータの瞬時誤りを伴い、さらに、
正常な系に切り替えられた後は故障パネルを保守しない
限り片系運用となっており、運用パネルが故障した場合
には両系異常となる回路構成となっているので、システ
ムが異常となる欠点かある。
In the conventional redundant system selection circuit described above, the data string having the redundant system and the control pulse for selecting the data of the normal system among the data strings of both systems are input to the selection circuit with the same phase delay. With instantaneous errors in the data, and furthermore,
After switching to a normal system, unless the failed panel is maintained, it will be in single system operation, and if the operating panel fails, both systems will become abnormal, so the circuit configuration is such that the system will become abnormal. There is.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の冗長系選択回路は、パスパタンをそれぞれ含む
0本(nは2以上の整数)のデータ列をそれぞれ入力し
1列を選択して出力する2つの第1の選択回路と、これ
ら第1の選択回路のそれぞれが出力した前記データ列を
それぞれ監視する2つのパスパタン検出回路と、前記第
1の選択回路のそれぞれが出力した前記データ列をそれ
ぞれ入力する2つの遅延回路と、これら遅延回路のそれ
ぞれが出力した前記データ列を入力しいずれか一方を選
択して出力する第2の選択回路と、前記パスパタン検出
回路の検出結果に基ついて前記第1及び第2の選択回路
の選択動作を制御する制御回路とを備えている。
The redundant system selection circuit of the present invention includes two first selection circuits each inputting 0 data strings (n is an integer of 2 or more) each including a path pattern, and selecting and outputting one column; two path pattern detection circuits that respectively monitor the data strings output from each of the first selection circuits; two delay circuits that receive the data strings output from each of the first selection circuits; a second selection circuit which inputs the data strings output from each, selects and outputs one of them, and controls selection operations of the first and second selection circuits based on the detection results of the path pattern detection circuit; control circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図であり、冗長系
を有する2組のそれぞれ0本のデータ列を入力とする。
FIG. 1 is a block diagram of an embodiment of the present invention, in which two sets of data strings each having a redundant system with zero lines are input.

第1図に示すように、冗長系を有する同一のフレーム構
成のデータ列D A、 T A 1〜D A T A 
nDATA 1 a〜DATAnaが入力される。入力
されたデータ列のうち、DATAj  (i=1〜n)
は第1の選択回路11に、DATAia(i=]〜n)
は第1の選択回路12に入力され、その出力のデータ列
がそれぞれ遅延回路13.14でmビット遅延されて第
2の選択回路15に入力される。
As shown in FIG. 1, data strings D A, T A 1 to D A T A of the same frame structure with redundant system
nDATA 1 a to DATAna are input. Among the input data strings, DATAj (i=1 to n)
is sent to the first selection circuit 11, DATAia(i=]~n)
are input to the first selection circuit 12, and the output data strings are delayed by m bits in delay circuits 13 and 14, respectively, and input to the second selection circuit 15.

パスパタン検出回路17又は18で誤りが検出されたデ
ータ列が選択回路15に到達するよりも先に制御回路1
6より選択制御パルスか出力され、伝送データ列の瞬時
誤りをおこすことなく、常時、冗長系を有する各系9本
のデータ列の選択制御を行う。ただし、選択制御は選択
回路15を選択回路11.12より先に制御する。
The control circuit 1
A selection control pulse is outputted from 6, and the selection control of nine data strings in each system having a redundant system is always performed without causing instantaneous errors in the transmitted data strings. However, the selection control controls the selection circuit 15 before the selection circuits 11 and 12.

パスパタン検出回路1つにより選択されたデータ列は空
きタイムスロットに挿入されたパスパタンの検出を行い
、自己監視を行なう。
The data string selected by one path pattern detection circuit performs self-monitoring by detecting a path pattern inserted into an empty time slot.

障害を起したデータ列DATAjを含む側のデータ列D
ATAI〜nを選択回路15が切り替えた後、選択回路
11にてデータ列DATAk (≠j)に切り替え、予
備の系として待機する。データ列DATA1a〜naに
障害が発生した場合についても同様である。
Data string D on the side that includes the faulty data string DATAj
After the selection circuit 15 switches ATAI~n, the selection circuit 11 switches it to the data string DATAk (≠j) and stands by as a standby system. The same applies when a failure occurs in the data strings DATA1a to DATAna.

選択されたデータ列と選択制御パルスの例を第2図のタ
イミング図に示す。
An example of the selected data string and selection control pulse is shown in the timing diagram of FIG.

第2図の例では、最初に選択回路11がデータ列DAT
AI、選択回路12がデータ列DATAla、選択回路
15がO系のデータ列DATAIを選択しており、選択
されたデータ列はDATAlになっている。データ列D
ATAIに障害が発生ずると、パスパタン検出回路17
がそのことを検出し、この検出結果に基づいて制御回路
16が選択制御パルスを発生し、選択回路15に1系の
− データ列DATA1aを選択させ、選択回路11にはデ
ータ列DATA2を選択させる。データ列DATAI、
laは遅延回路13.14によって遅延させられている
ので、データ列DATAIの障害による誤りが選択回路
15に到達する前に選択回路15はデータ列DATAl
a側に切替っており、瞬時誤りは発生しない。同様にし
て、次にデータ列DATA1aに障害が発生すると選択
回路15はデータ列DATA2を選択し、選択回路12
はデータ列DATA2aを選択する。
In the example of FIG. 2, the selection circuit 11 first selects the data string DAT.
AI, the selection circuit 12 selects the data string DATAla, and the selection circuit 15 selects the O-system data string DATAI, and the selected data string is DATA1. Data column D
When a failure occurs in ATAI, the path pattern detection circuit 17
detects this, and based on this detection result, the control circuit 16 generates a selection control pulse, causing the selection circuit 15 to select the - data string DATA1a of the 1st system, and causing the selection circuit 11 to select the data string DATA2. . data string DATAI,
Since la is delayed by the delay circuits 13 and 14, the selection circuit 15 selects the data string DATAI before an error due to a failure in the data string DATAI reaches the selection circuit 15.
Switching to side a, no instantaneous error occurs. Similarly, when a failure occurs in the data string DATA1a next, the selection circuit 15 selects the data string DATA2, and the selection circuit 12 selects the data string DATA2.
selects the data string DATA2a.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、2つの第1の選択回路と
第2の選択回路との2段構成にし、これら2つの段の間
に遅延回路を設けることにより、選択制御パルスが冗長
系を持つデータ列よりも早く伝送され、冗長系のデータ
列の選択が瞬時的に誤りをおこすことなく行うことがで
き、さらに、正常な系を選択した後も、故障パネルを保
守することに関係なく片系運用になることはなく、従っ
て両系異常になることはないという効果がある。
As explained above, the present invention has a two-stage configuration of two first selection circuits and a second selection circuit, and a delay circuit is provided between these two stages, so that the selection control pulse can pass through the redundant system. The redundant system data sequence can be selected instantaneously and without error, and even after the normal system has been selected, the data sequence can be transmitted faster than the existing data sequence, regardless of whether the faulty panel is maintained. This has the effect that one-system operation will not occur, and therefore, both systems will not experience an abnormality.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示したブロック図、第2図
は第1図の実施例のタイミンク′図である。 ]、 1. 、1.2・・・第1の選択回路、13.1
.4・・遅延回路、15・・・第2の選択回路、16・
・・制御回路、17.1.8.19・・・パスパタン検
出回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram of the embodiment of FIG. ], 1. , 1.2...first selection circuit, 13.1
.. 4...Delay circuit, 15...Second selection circuit, 16.
...Control circuit, 17.1.8.19...Pass pattern detection circuit.

Claims (1)

【特許請求の範囲】[Claims] パスパタンをそれぞれ含むn本(nは2以上の整数)の
データ列をそれぞれ入力し1列を選択して出力する2つ
の第1の選択回路と、これら第1の選択回路のそれぞれ
が出力した前記データ列をそれぞれ監視する2つのパス
パタン検出回路と、前記第1の選択回路のそれぞれが出
力した前記データ列をそれぞれ入力する2つの遅延回路
と、これら遅延回路のそれぞれが出力した前記データ列
を入力しいずれか一方を選択して出力する第2の選択回
路と、前記パスパタン検出回路の検出結果に基づいて前
記第1及び第2の選択回路の選択動作を制御する制御回
路とを備えたことを特徴とする冗長系選択回路。
Two first selection circuits each input n data strings (n is an integer of 2 or more) each containing a path pattern, select and output one column, and the two path pattern detection circuits that respectively monitor data strings; two delay circuits that input the data strings output from each of the first selection circuits; and two delay circuits that input the data strings output from each of these delay circuits. and a control circuit that controls selection operations of the first and second selection circuits based on the detection result of the path pattern detection circuit. Features redundant selection circuit.
JP33743389A 1989-12-25 1989-12-25 Redundant system selecting circuit Pending JPH03195228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33743389A JPH03195228A (en) 1989-12-25 1989-12-25 Redundant system selecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33743389A JPH03195228A (en) 1989-12-25 1989-12-25 Redundant system selecting circuit

Publications (1)

Publication Number Publication Date
JPH03195228A true JPH03195228A (en) 1991-08-26

Family

ID=18308585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33743389A Pending JPH03195228A (en) 1989-12-25 1989-12-25 Redundant system selecting circuit

Country Status (1)

Country Link
JP (1) JPH03195228A (en)

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