JPH03195227A - Spread spectrum code synchronizing circuit - Google Patents

Abstract

PURPOSE:To shorten the time up to synchronization establishment stably by utilizing principles such that an inverse spread code (M series code) synchronously with an input signal is immediately obtained when the input signal fetched to a shift register as an initial value has no error and the signal '0' is subject to spread modulation. CONSTITUTION:An input signal is given to one data input of a selection means 10. A circuit means 12 is provided with a shift register 120 and fetches an input signal sequentially when the selection means 10 selects the input signal and an M series code generator in a path of the selection means 10 is formed when other input is selected and generates an inverse spread code (M series code) by using the fetched value as the initial value. A correlation verification means 14 calculates the degree of the correlation between the inverse spread code and the input signal. A control means 16 controls the selection means 10 to input an input signal into the circuit means 12 as an initial value and selects the selection means 10 to form the M series code generator with the circuit means 12, and selects the selection means again to set an initial value to the circuit means 12 when an output of the correlation verification means 14 represents that no correlation is present between the inverse spread code and the input signal.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a spread spectrum code synchronization circuit that is stable and shortens the time required to establish synchronization. selection means having an input and a selection input for selecting one of the two data inputs, and when the selection means selects the one manual input, the selection means takes in the input signal and selects the other input; circuit means for forming an M-sequence generator that includes a path of the selection means and generates an M-sequence code having the captured value as an initial value as a despreading code; (4) correlation verification means for calculating and outputting the degree of correlation between the input signal and the input signal; and the selection means selecting the human input signal; control means for switching the selection means again and setting an initial value in the circuit means when the output of the correlation verification means indicates that there is no correlation between the despreading code and the input signal; Equip and configure.

[Field of Industrial Application] The present invention relates to a spread spectrum code synchronization circuit that generates a despreading code synchronized with an input signal in order to despread a signal spread modulated by a spread spectrum method.

Since the spectrum communication method has excellent communication privacy and is less susceptible to noise and interference, its adoption in communication using power lines and satellite communication systems has recently been considered. The present invention refers to a spread spectrum code synchronization circuit that generates a despreading code for despreading a signal encoded by this method to restore original data.

(5) (Prior Art) In Spectrum Spread (SS) communication, the transmitting side processes one bit of data at a bit rate several hundred to several million times the bit rate of that data. Spread modulation is performed using a random (PN) code that repeats each bit period as one cycle.

On the receiving side, a continuous PN code is generated at the same frequency and in the same sequence as the transmitting side, and its frequency and phase are adjusted and synchronized with the received signal to create a despreading code, thereby despreading the received signal. By doing this, the signal before spread modulation is obtained.

In order to simplify the explanation, FIG. 5 shows a PN code generator having a period of 23-1=7 bits and 2 bits, which is generated by a PN code generator having a three-stage shift register configured as shown in FIG.
A signal before spread modulation (column (A)), a PN code (column (B)), and a signal after spread modulation (column (C)) are shown when seven times spread modulation is performed using a code.

P generated by a PN generator with a three-stage shift register
The N code (column (B)) is continuous with a period of 2'-1 = 7 bits (6), and coincides with the 1-bit period (represented by To) of the signal before modulation (column A). There is.

Spread modulation is performed by calculating the exclusive OR of both. Therefore, the signal after spread modulation (column (C)) has a pattern that is the inversion of one cycle of the PN code during the period when the original signal is 1, and becomes the PN code itself during the period when the original signal is O. There is.

On the receiving side, the PN code shown in column (B) of Fig. 5 is generated by the PN code generator shown in Fig. 6, and the frequency and phase of the PN code are adjusted so that the correlation with the received signal is maximized. This is used as a despreading code, and an exclusive OR with the received signal is performed to obtain a signal before spreading modulation.

FIG. 7 shows a typical delay locked loop (DLL) circuit as a synchronization circuit for obtaining this despreading code.

PN code generator 56 having an n-stage shift register 57
The output of two trees is extracted from . They are taken out from adjacent stages of the shift register 57 (7), resulting in a PN code in which one phase is delayed by one bit than the other. The input signal is multiplied by these two PN codes in multipliers 50 and 51, and passes through envelope detectors 52 and 53, respectively, to produce a signal representing the amplitude of the envelope of the signal.

The outputs of the envelope line detectors 52 and 53 are correlation functions between the input signal and the PN code. A subtracter 54 subtracts the output of the envelope detector 53 from the output of the envelope detector 52,
The frequency of the output of the voltage controlled oscillator 55 is controlled by the output. The output of voltage controlled oscillator 55 is provided as a clock to PN generator 56.

Due to the nature of the PN code, the output of the envelope line detector 52 reaches a maximum at a point where the input signal and the PN code are correlated, as shown in column (A) of FIG. 8, and becomes constant as it moves away from that point. The output of the envelope detector 53 is similar, but is delayed by one clock of the PN code, so it is shifted by one clock as shown in the column (B) of FIG. therefore,
If we take the difference between them, as shown in column (C), the area where the correlation function is linear across the midpoint of both peaks (indicated by a black circle) (
8) exists, the frequency of the voltage controlled oscillator 55 is controlled in this part to maintain synchronization.

[Problems to be Solved by the Invention] In the above-mentioned DLL circuit, the range that can be drawn by itself is only the above-mentioned linear portion, and the correlation function becomes flat as it moves away from the bowing point. Therefore, there is a problem in that it takes a lot of time to establish synchronization.

Additionally, since it includes an analog circuit, there is also the problem of poor stability due to variations in the temperature characteristics and characteristics of the components.

Therefore, an object of the present invention is to provide a spread spectrum code synchronization circuit that is stable and takes a short time to establish synchronization.

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle configuration of a spread spectrum code synchronization circuit according to the present invention.

The selection means 10 has two data inputs and a selection input for selecting one of them (9), and an input signal is connected to one of the data inputs. The circuit means 12 sequentially takes in the input signals when the selection means 10 selects the input signal, forms an M-sequence generator including the path of the selection means 10 when the other input is selected, and converts the taken values into initial values. A despreading code (M-sequence code) is generated as follows. The correlation verification means 14 calculates and outputs the degree of correlation between the despreading code and the human signal. The control means 16 controls the selection means 10 to input the input signal into the circuit means 12 as an initial input signal, and then switches the selection means 10 to form an M-sequence generator together with the circuit means 12, and to input the input signal into the circuit means 12 as an initial input signal. When the output indicates that there is no correlation between the despreading code and the input signal, the selection means is switched again and an initial value is set in the circuit means 12.

The circuit means 12 includes a shift register 120, a correlation verification means 14, a period setting means 140, and a leading value setting means 1.
42, first match determination means 144, and delay means 146
, second match determining means 148 , and counting means 149
It is preferable that the Period (10) The setting means 140 sets a period for determining the coincidence between the output of the circuit means 12 and the input signal, preferably the longest possible period included in the period of one bit of the non-spreading signal. . The start timing of this period is given by the first match determination means 144, and a certain period from that time is defined as a match determination period. The head value setting means 142 includes a shift I register 120 corresponding to the start timing of the match determination period.
The value of is set. The first match determination means 144 determines whether the value in the shift register 120 matches the value set in the head value setting means 142, and when they match, the period setting means 144
Give the start timing to 40. The delay means 146 applies the same delay to the input signal as the delay in the shift register 120 and outputs it. The second coincidence determination means 148 determines whether the despreading code and the output of the delay means 146 match. Counting means 149 is period setting means 140
The matching period of the second matching determining means 148 within the period set by is summed to provide an output representing the degree of correlation.

(11) [Operation] In the M-sequence code, a complete M-sequence code can be uniquely obtained from any value in the shift register up to -7. Therefore, if there is no error in the input signal taken in as an initial value, and if it is a spread-modulated signal "O", a despreading code synchronized with the human input signal can be obtained immediately.

After that, if there is no error in the input signal, the outputs of the second coincidence determination means 148 will all match within the period of 1 bit of the non-spreading signal or within the coincidence determination period set by the period setting means. This will result in a state of mismatch, and even if there are some errors, all will be close to matching or all will be close to mismatch. Therefore, the total value of the matching periods in the counting means 149 indicates the degree of correlation.

If there is an error in the human input signal or if it diffusely modulates the signal "1°", the output of the circuit means I2 and the output of the delay means 146 will match until the initial value taken is different from the output. However, after that, due to the nature of the M-sequence code (12), matches and mismatches will appear with a probability close to 172, and in this case, the control means 16 will again control the selection means 10 to take in the initial value. Repeat until synchronization is achieved.

〔Example〕

FIG. 2 is a diagram showing a spread spectrum code synchronization circuit 50 which is an embodiment of the present invention. 12001460, 1
All 68 are n-stage shift registers.

1402, 166, and 1492 are counters that count clocks (not shown) when the enable (EN) terminal is valid, and the counters 1402 and 166 generate ripples after counting T1 and 27-1 clocks, respectively. Outputs carry (RC). The shift register 1200 and the adder circuit 1202 are a well-known shift register code series generator that generates an M-sequence code with a period of 2'-1 when the select terminal (A/T) of the selector 100 selects input A at 11 levels. (SRG).

Further, while the select terminal of the selector 100 is at the L level, the input signal is taken into the register 1200 (13). Comparator 144
0 is used to compare whether or not the value of the shift register 1200 is equal to the leading value of the M sequence code; when both are equal,
-' output becomes H level. JK flip-flop 1400 is set when the J input becomes H level,
Allow the counter 1402 to count. counter 14
When 02 finishes counting T1 clocks, a ripple signal is output and the JK flip-flop 1400
is reset. That is, shift register 1200
When becomes equal to a predetermined leading value, the output of flip-flop 1400 becomes H level only during the TI clock period. Shift register 1460 is shift] register 120
The input signal is delayed by the same amount as the delay amount caused by 0, and the EOR gate 1480 determines whether the output of the input signal matches the output of the shift register 1200, that is, the despreading code. AND gate 1490 is JK flip-flop 1
400 is at H level (hereinafter referred to as T9 period).

) is the EOR game) 1480 is supplied to the enable terminal of the counter 1492. counter 14
92(14) counts the number of matches during period T4, and the result is latched into flip-flop 1494. Comparator 16
0 determines whether the value latched in the flip-flop 1494 is greater than the first dark value SH, and if so, sets the output "A>B" to H level. Comparator 162 indicates that the value latched in flip-flop 1494 is the second value.
It is determined whether it is smaller than the darkness value SL, and if it is smaller, the output "A >B" is set to H level. OR gate 1
The output of the comparator 160 "A>B'" and the output "'A>B" of the comparator 162 are connected to the input of the comparator 64.The first threshold SH is T1, that is, TIxJI
All EOR gate outputs are 1 within the interval (all mismatches)
The value is set slightly smaller than the value when , taking into account errors in the input signal. The second darkness value S1- is 0, i.e. T1
All EOR gate outputs are O within the period (all match)
The value is set slightly larger than the value when , taking into account errors in the input signal. Therefore, the output of the OR gate 164 is at H level while the despreading signal output from this circuit 50 and the input signal are synchronized, and becomes a signal representing the state of (15) synchronization. While the input r level is at the L level, the counter 166 controls the clock from 1 to 1L,
2'-] A ripple carry (RC) is output every clock, that is, every cycle of the M-sequence code.

The shift register 168 and the NOR gate 170 are circuits for controlling the selector 100 at a predetermined period to set an initial value to the shift register 1200 while the synchronization is not achieved, and a ripple carry is output from the counter 166. At this time, the output of the NOR gate 1-170 is at the L level for a period corresponding to the number of stages of the shift register 1200, that is, n clocks, and the selector 100 is controlled to select the input signal.

FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 2. The signal in column (A) represents the signal before spread modulation, the signal in column (B) represents the M-sequence code for spread modulation, and N represents the signal of one period of the M-sequence code with period 2''-1. Column (C) represents the signal in column (A) (
The signal in column B) represents the result of spread modulation, and this signal is assumed to be input to the circuit of FIG. Also, I is N (
16) It shall represent an inverted pattern. (C) ~ (I,
) The signals in the column each represent the state of the signal at the point labeled CL in FIG.

Column (D) is a control signal for the selector 100, and while the initial synchronization is not achieved, a negative pulse with a width n is output at a cycle of 2'-1. In the figure, the input signal is taken in during the first L level period, and then the M-sequence code is output using this as the initial value, but since the input signal (column (C)) is X, the column (F) A pattern N' that is not synchronized with the signal is output. Therefore, the signals shown in column (G) are 0 and 1.
have approximately equal probabilities. If it is assumed that the value in the shift register 1200 becomes equal to the predetermined leading value at the timing indicated by the leftmost pulse in column (H), then the number of matches is counted within the T1 clock, and the result is a((K ) column), this value is SI.

< a < S o, and the synchronization information ((L) column) is ■
, the level. Similarly, for the second pulse in column (D), column (C) is I, so the non-synchronized pattern N
' is output. Regarding the third pulse (17) in column (D), since the signal in column (C) is N, a pattern Nrr synchronized with the signal in column (F) and starting from the middle is output. N'' pattern ends, synchronization pattern N
When starts to appear, a pulse is output to the signal in column (H). After that, if the synchronization pattern N continues during the T1 clock period, the value latched in the flip-flop 1494 is 0.
(column (K)), and the synchronization information (column (L)) becomes H level. After that, if there is no error in the input signal, the value in the (K) column will be 0 or T, and even if there is some error, it will be a value close to either, and synchronization is maintained.

In this example, the straight line T1 counted by the counter 1402 is set to a value close to the pole (2+''-1) in one cycle.
The period must be continuous, but if it is shorter than this, it will be 1
The probability of achieving periodic synchronization increases. However, since the synchronization is determined for a part of one cycle, care must be taken when setting the dark value Sll + SL. Also,
It is also possible to take T1 longer than one cycle.

(18) It is not necessary that the number of squares counted by the counter 166 corresponds to one period of 2°-1, but it is preferable that the period be slightly longer than this.

FIG. 4 is a diagram showing a second embodiment of the present invention. In this example, two circuits 50 shown in FIG. 2 are used, and one is supplied with an input signal inverted by an inverter 52. and,
By selecting the despreading code whose synchronization information is at H level in the selector 54, the time required to establish synchronization can be further shortened. This is because even if it is an inverted pattern for one circuit 50, it will be a non-inverted pattern for the other circuit 50, and as long as there is no error in the input signal, a synchronized pattern will be immediately output from either circuit 50. It is.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a spread spectrum code synchronization circuit whose operation is stable because it is entirely composed of digital circuits, and the time required to establish synchronization is significantly shortened.

(19)

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a timing chart showing the operation of the circuit shown in Fig. 2, and Fig. 4 is a diagram showing the operation of the circuit of the present invention. A diagram showing the second embodiment, FIG. 5 is a diagram for explaining the spread spectrum method, FIG. 6 is a diagram showing an example of a PN code generator, FIG. 7 is a diagram showing a conventional synchronization circuit, FIG. 8 is a diagram for explaining the operation of the circuit shown in FIG. 7. In the figure, 144...first coincidence determination means, 148...second coincidence determination means, 168, 1200.1440...shift register, 1
66, 1402.1492...Counter. (20)

Claims (1)

[Claims] 1. Selection means (10) having two data inputs, one of which is connected to an input signal, and a selection input for selecting one of the two data inputs; an M-sequence generator that takes in the input signal when the selection means (10) selects the one input, and includes a path of the selection means (10) when the selection means (10) selects the other input; circuit means (12) forming an M-sequence generator that generates an M-sequence code having the initial value as a despreading code; and calculating and outputting the degree of correlation between the despreading code and the input signal. correlation verification means (14) and the circuit means (12)
The selection means (
10) selects the input signal, and then switches the selection means (10) to form an M-sequence generator together with the circuit means (12), and the output of the correlation verification means (14) is used for despreading. When it is shown that there is no correlation between the code and the input signal, the selection means (10) is switched again and the circuit means (1
2) A spread spectrum code synchronization circuit comprising control means (16) for setting an initial value in . 2. The circuit means (12) is a shift register (120) which forms a part of the M-sequence generator and receives the input signal as an initial value and holds each state of the M-sequence generator.
The correlation verification means (14) is a period setting means (140) for setting a period for determining a match between the output of the circuit means (12) and the input signal, and a period setting means (140) that sets a predetermined period from the timing as the match determination period; and a leading value setting means (140) in which a value of the shift register (120) corresponding to the start timing of the match determination period is set.
142), and a first step that determines whether the value in the shift register (120) and the value set in the head value setting means (142) match, and when they match, gives a start timing to the period setting means (140). 1, a delay means (146) for applying a delay equal to the delay amount from the input of the shift register (120) to the output of the M-sequence generator to the input signal and outputting the same; The output of the M-sequence generator and the delay means (1
46), and a second match determining means (148) that determines whether the output of the second match determining means (148) matches within the period set by the period setting means (140). counting means (149) for summing up the periods and producing an output representing the degree of correlation;
) The spread spectrum code synchronization circuit according to claim 1, comprising: 3. The first and second synchronization circuits according to claim 1; second selection means for selecting one of the despreading codes of the first and second synchronization circuits; and the second selection. and a second control means for controlling the control means, the control means (16) validating the control information when there is a correlation between the despreading code and the input signal, and the second control means for controlling the control means. A spread spectrum code synchronization circuit that controls the second selection means to select a despreading code on the side where information is valid.