JPH08330913A - Pn code generation circuit and communication terminal equipment - Google Patents

Abstract

PURPOSE: To repetitively generate the pseudo noise codes of an optional length by initializing a pseudo noise generator for every optionally prescribed value set previously regardless of the largest number of pseudo noise codes that can be generated. CONSTITUTION: The initial state loading means 15A and 15B serve as the circuits which supply the initial value that are loaded by the PN code generators 12A and 12B respectively in an initial mode. The type of the PN code generated by a PN code generation circuit 11 is decided by the bit number (n) of the initial value IB sent from both means 15A and 15B. In such a constitution. the circuit 11 can set the length and the type of a PN code independently of each other. Thus the pseudo noise codes of an optional length are continuously generated. Furthermore, the code series to be generated can be changed when the set state of the initial value is changed. Thereby, many codes can be generated regardless of their cycles.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example (1) First Example (1-1) Overall Configuration (1-2) Specific Example (2) Second Example (3) Third Example (4) Fourth Example (5) Other Example Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN code generating circuit and a communication terminal device. For example, it is suitable for application to a communication terminal device used in spread spectrum (SS) communication and its PN code generation circuit.

[0003]

Pseudo noise (PN) is used in spread spectrum (SS) communication for spreading the transmission band. Now, in an asynchronous spread spectrum (SS) communication system, pseudo noise (PN) with small cross-correlation for different users and systems.
By assigning a code, interference at the same frequency is eliminated and communication independence is secured. Therefore, asynchronous SS
To construct a communication system, it is necessary to generate a large number of PN sequences with small cross-correlation.

As a PN code sequence having a small cross-correlation, a GOLD sequence has been conventionally known. This GOL is shown in FIG.
An example of a PN generation circuit for generating a D code is shown. GOLD
The code generation circuit 1 includes a first m-sequence generation circuit configured by a shift register 2A and an exclusive OR circuit 3A and a second m-sequence configured by a shift register 2B and an exclusive OR circuit 3B. A GOLD code sequence by obtaining an exclusive OR of the first m-sequence output and the second m-sequence output output from these two sequence generation circuits by the exclusive OR circuit 4. Is designed to generate.

The output of the GOLD code generation circuit 1 becomes a different code sequence by changing the initial state of the shift register. In order to utilize this property, the GOLD code generation circuit 1 fixes the initial state of the shift register 2A in the first m-sequence generation circuit and changes the initial state of the shift register 2B in the second m-sequence generation circuit. ing. The types of codes to be generated are 2 ^ n + 1 when the number of stages of the shift register of one generator is n, and the code length is 2 ^ n-1. Incidentally, FIG. 8 shows the case where n = 6, and the code length is given as 63 at this time, and 65
Different PN sequences can be generated from one PN code generation circuit.

[0006]

However, the P of this configuration is
The N code generation circuit has the following problems. To demodulate the spread spectrum (SS) signal transmitted from the communication terminal device on the transmission side in the communication terminal device on the reception side, the spread spectrum (SS) signal received during despreading is multiplied by the PN code and the received signal. The PN code generated in the local communication terminal must be synchronized. That is, in the communication terminal device on the receiving side, the PN code must be quickly synchronized in order to start the demodulation operation.

However, the longer the repetition period of the PN code, the longer the time required for synchronization acquisition. Therefore, the PN period must be shortened to some extent. For example, when n = 20, the code length M is 1048575, so that when the chip plate is 1 [MHz], the repetition period of the PN code is 1.048575 [seconds]. Usually, as the time required to acquire code synchronization, in the worst case, a time longer than the code period is required, but 1 second is too long, which is a problem.

As described above, the GOLD code conventionally used has a drawback in that if the number of code types is increased, the code period becomes long and it takes time to acquire synchronization. Further, since the sequence length M of the GOLD code sequence can take only a discontinuous value of 2 ^ n-1, there is a problem that the code length M cannot be freely set even if it is desired to be set to a value other than the above value.

The present invention has been made in consideration of the above points, and an object thereof is to propose a PN code generating circuit and a communication terminal device that can generate a large number of types of codes and have a short code period. In addition to this, the present invention intends to propose a PN code generation circuit and a communication terminal device in which the code period can be arbitrarily set.

[0010]

In order to solve such a problem, according to the present invention, the number of codes of the pseudo noise code output from the synthesizing means is counted by the counting means, and every time the number of codes reaches a predetermined value, The first and second pseudo noise generators are initialized.

[0011]

The first and second pseudo noise generators are initialized for each arbitrary predetermined value regardless of the maximum number of pseudo noise codes that can be generated. As a result, a pseudo noise code having an arbitrary code length is repeatedly generated. Further, since the code sequence generated by changing the setting state of the initial value can be changed, many codes can be generated regardless of the code period.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment (1-1) Overall Configuration The PN code generation circuit described in this embodiment is characterized by periodically initializing a PN generator that generates a code sequence. FIG. 1 shows the block configuration of the PN code generation circuit. The PN code generation circuit 11 is a GOLD code generation circuit (P
The N generators 12A and 12B and the exclusive OR circuit 13) are used as a basic configuration, and an M-ary counter 1 as counting means is added to this.
4 and initial state loading means 15A and 15B are added. Each part has the following configuration.

First, the PN generators 12A and 12B are constituted by a shift register which operates at the rising edge of the clock CK. Each time the clock CK rises, a PN generator is provided.
It outputs one code. Each of the PN generators 12A and 12B is provided with a load input terminal LD and an input terminal IA for inputting an initial value of n bits, and the operating state is changed according to the value input to the load input terminal LD. It is designed to switch.

For example, when the value of the load signal input to the load input terminal LD is "L", the PN generators 12A, 12
B is in a normal operation state and generates a PN code at every rising edge of the clock CK. On the other hand, the value of the load signal input to the load input terminal LD is "H".
At this time, the PN generators 12A and 12B are in the initial value write state, and the initial values IA and IB are loaded into the shift register every time the clock CK rises.

These two PN generators 12A and 12B
The PN code output of is input to the exclusive OR circuit 13, and is output from the output end as the output of the PN code generation circuit 11. The M-ary counter 14 is for initial setting of the PN generators 12A and 12B. The M-ary counter 14 raises the value of the load signal from "L" to "H" every time the count value of the clock CK reaches a predetermined value M, and the PN generators 12A and 1
The operation state of 2B is set to the write state. The forced reset operation by the M-ary counter 14 enables the code length M of the PN code to be freely set.

The initial state loading means 15A and 15B are circuits for giving initial values to be loaded by the PN generators 12A and 12B at the time of initial setting. In the case of this embodiment, the initial state loading means 15A gives a fixed value as the initial value IA, and the initial state loading means 15A gives a predetermined arbitrarily set value as the initial value IB. At this time, the type of PN code generated by the PN generating circuit 11 is determined according to the number n of bits of the initial value IB given by the initial state loading means 15A and 15B, and there are 2 ^ n ways. According to the above configuration, a PN code generation circuit that can independently set the code length M and the code type of the PN code is realized.

(1-2) Specific Example FIG. 2 shows a specific example of the PN code generation circuit 11. In this example, n = 20 and M = 2304. The number of stages of the delay blocks UA1 to UA20 and UB1 to UB20 forming the shift register corresponds to the bit number n of the initial values 1A and IB. Therefore, in this example, the delay block U
The number of stages of each of A1 to UA20 and UB1 to UB20 is 20.

These delay blocks UA1 to UA20 and UB1 to UB20 are provided with an input terminal D, an output terminal Q, a load terminal LD and an initial setting input terminal A in addition to the clock input terminal. These delay blocks UA1-U
The operation of A20 and UB1 to UB20 is as shown in the table in the figure. That is, when the load terminal LD = "L", the delay block acts as a simple shift register, and the value of the input terminal D is transmitted to the output terminal Q. On the other hand, when the load terminal LD = “H”, the value of the input terminal A is transmitted to the output terminal Q and the initial value is loaded.

Incidentally, the input terminals A for initial setting of the delay blocks UA1 to UA20 constituting the PN generator 12A are grounded, and when the load terminal LD = "H", all the input terminals A for initial setting are set. "L" is input to. On the other hand, P
Delay blocks UB1 to UB2 constituting the N generator 12B
The initial setting load means 15 is connected to the initial setting input terminal A of 0.
When B is connected and the load terminal LD is "H", the initial value IB is input from the initial state loading means 15B.

In the case of this example, the M-ary counter 14 is 2
It operates as a 304-ary counter. Here, the count value of the M-ary counter 14 is Z. When the count value Z is "0" to "2302", the M-ary counter 14 outputs "L" as the output Y, and when the count value Z is "2303", it outputs "H" as the output Y. Incidentally, the M-adic counter 14
The maximum count value Z is "2303", and the count value Z is reset at the next rising of the clock so that the count value Z becomes "0".

As described above, the initial value IB is 2
The number N of PN codes generated in the PN generating circuit 11 is 2 ^ 20 because the bit string of 0 bits is set.
= 1048576. These 1048576 PN code sequences are all different. Generally, if the period M of the PN code is larger than the number of stages n of the shift register, 2 ^ n
As you can see, all PN codes are different.

As for the number of PN codes, if a PN code is generated in a bit string of 20 bits, the number N of PN codes is 2 ^ n + 1 = 1048577, which is between the circuit of the embodiment and the conventional circuit. There is no difference in the type of PN code generated in. On the other hand, for the code length M, in the case of the conventional circuit, if a PN code is generated in a 20-bit bit string, 2 ^ n-
Since 1 = 1048575, which is a very long value and a fixed value, the superiority of the circuit of the embodiment can be seen.

Thus, the PN code generating circuit 1 of this embodiment
If 1 is used, the number of different PN codes that can be generated is large, but the code length can be freely set to any value (for example, a relatively short value). As a result, initial synchronization with the PN code is easy, and the PN has good cross-correlation characteristics.
It is possible to realize a PN code generation circuit that can generate a large number of sequences. Further, since a PN code sequence having a desired sequence length M can be generated, a PN code generation circuit that can easily design various parameters (spreading gain, frame length, etc.) even when applied to a spectrum communication system is realized. be able to. Further, in the case of the asynchronous spread spectrum communication system, it is possible to realize a PN code generation circuit which can take a large number of channels or users.

(2) Second Embodiment In FIG. 3 in which parts corresponding to those in FIG.
A second embodiment of the code generation circuit will be shown. The PN code generation circuit 21 uses a comparison circuit 22 instead of the M-ary counter 14 to count the code length M of one cycle.
Is characterized by setting the timing of the code length M by monitoring the state of the PN generator 12A.

Specifically, the comparison circuit 22 is the PN generator 12
The state of the shift register in A is monitored, and the state of the shift register is the Mth state (pattern) from the initial state.
The timing for loading the initial value is set by detecting whether or not

That is, when the state of the n-bit shift register in the PN generator 12A is QA and the Mth state QA from the initial state IA is Z, the comparison circuit 22 compares the state QA with the state Z. Then, when the two states match, “H” is output as the comparison output Y, and “L” is output otherwise. The PN generators 12A and 12B read the initial states IA and IB by the initial state load means 15A and 15B when the clock is raised when the value input to the load terminal LD is "H", and reset the shift register.

According to the above configuration, the PN code generation circuit 1
It is possible to realize a PN code generation circuit that can obtain the same effect as that of 1. Further, in the case of this PN code generation circuit 22,
Since the comparison circuit 22 can be configured by an n-input AND circuit, the circuit scale can be reduced as compared with the case where the M-ary counter 14 is used.

(3) Third Embodiment FIG. 4 in which parts corresponding to those in FIG. 2 are assigned the same reference numerals shows a third embodiment of the PN code generating circuit. This PN code generation circuit 31 is different from the configuration of the first embodiment except that a mask means 32 for shifting the phase of the PN code generated by the second PN generator 12B is newly provided. It has a similar configuration.

Now, the structure of the mask means 32, which is a new structure, will be mainly described. When the shift register of the second PN generator 12B has n stages, the mask means 32
It is constituted by n 2-input AND circuits UD1 to UDn and an n-input exclusive OR circuit UDn + 1. In this case, since n = 6, it is composed of six 2-input AND circuits represented by UD1 to UD6 and a 6-input exclusive OR circuit of UD7.

The outputs of the delay blocks UB1 to UB6 forming the shift register are input to one input of the 2-input AND circuits UD1 to UD6, and the 6-bit mask input ( MASK) is given. In this example, mask input (MA
Give 6 bits as SK). At this time, the output of the 6-input exclusive OR circuit UD7 is P of the second PN generator 12B.
It is the N-sequence shifted in phase.

The phase shift amount is given by the mask input (M
Depending on the value of (ASK) and the state (pattern) of the shift register, in the case of 6-bit mask input (MASK), 2 ^ 6 -1 = 63 all shift patterns can be given. By the way, when all "0" is given as the mask input (MASK), the output of the mask means 32 becomes a constant value (that is, all 1s or all 0s).

Further, in the case of this embodiment, the PN generator 12A
The PN generator 12B and the PN generator 12B are the same as those in the first and second embodiments, respectively, but the initial values IA and IB given to the shift register are both fixed values. This is because if the PN sequence generated by the PN code generation circuit 31 is desired to be changed, the PN sequence generated can be changed by changing the bit pattern of the mask input (MASK). Even in this case, as with the PN code of the PN code generating circuit 11, it is possible to realize a PN code generating circuit which can output 2 ^ n different PN sequences and can set the code length M to an independent and arbitrary value. it can.

(4) Fourth Embodiment A fourth embodiment is shown in FIG. 5, in which parts corresponding to those in FIG. 4 are designated by the same reference numerals. The PN code generating circuit 41 is replaced with the M-ary counter 14 as in the case of the second embodiment, and the comparing circuit 4 is used.
It has the same configuration as that of the third embodiment except that the state of the shift register is reset by using 2. A concrete example of the comparison circuit 42 is shown in FIG. However, FIG. 6 shows an example in which the AND circuit has 6 inputs. 1st P
This is an example of the case where the state is input from the shift register of the N generator 12A, and is when the code length M is 10.

Here, the initial value IA is {0,0,0,0,
0,1}, the state of the shift register at the 10th clock becomes {0,1,0,1,1,1}. The comparison circuit 42 is configured so that the output Y becomes "H" in this state. With such a configuration, it is possible to realize a PN code generation circuit having a circuit scale smaller than that of the third embodiment.

(5) Other Embodiments In the above embodiment, the first PN generator 12 is provided by the comparison circuit 22 (42) as the internal state monitoring means.
Although the case of detecting the state A has been described, the present invention is not limited to this, and the state of the second PN generator 12B (12C) may be detected.

In the above embodiment, the case where the mask means 32 shifts the phase of the PN code generated in the second PN generator 12B has been described.
The present invention is not limited to this, and can be applied to the case of shifting the phase of the PN code generated in the first PN generator 12A.

Further, in the above-mentioned embodiment, the one in which the m-sequence code is generated as the first and second PN generators 12A and 12B has been described, but the present invention is not limited to this, and other types of PN code are also used. May be generated.

Furthermore, in the above-mentioned embodiment, the case where the same number of stages of shift registers constituting the first and second PN generators 12A and 12B is used, but the present invention is not limited to this. The number of stages of the shift register may be different. That is, if all of the 2 ^ n different codes are obtained and the necessary cross-correlation characteristics are obtained, then any 2
One code sequence can be used.

Further, in the above-mentioned embodiments, the PN code generating circuit has been described as a single structure, but the PN code generating circuit can be widely applied to the communication terminal apparatus of the system for transmitting information by spread spectrum. . For example, in FIG.
It can be used for the communication terminal devices 52 and 53 of the spread spectrum communication system 51 as shown in FIG.

Here, the communication terminal device 52 includes a spreader 52.
A, PN generation circuit 52B, mixer 52C, local oscillator 5
2D, an amplifier 52E, and an antenna 52F, and spreads the spectrum by multiplying the PN code generated by the PN generation circuit 52A and the data in the spreader 52A.

The communication terminal device 53 has an antenna 53.
A, amplifier 53B, mixer 53C, local oscillator 53D,
Synchronization circuit 53E, PN generation circuit 53F and despreader 53
The inverse spectrum is spread by multiplying the received wave in the intermediate frequency band by the PN code generated by the PN generation circuit 53F and synchronized with the PN code of the received wave.

In this way, each PN generation circuit 52B and 53
By using the PN generating circuit described in the above embodiment for F, it is possible to realize a communication terminal device in which various parameters (spreading gain, frame length, etc.) can be easily designed and the number of channels or users can be increased.

[0044]

As described above, according to the present invention, the first and second pseudo noise generators are initialized for each predetermined arbitrary value regardless of the maximum number of pseudo noise codes that can be generated. With this configuration, it is possible to realize a PN code generation circuit that can repeatedly generate a pseudo noise code having an arbitrary code length. Further, by using such a PN code generating circuit, it is possible to realize a communication terminal device with easy parameter design.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PN code generating circuit according to the present invention.

FIG. 2 is a block diagram showing a specific circuit example of a PN generation circuit.

FIG. 3 is a block diagram showing an embodiment of a PN code generating circuit according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a PN code generating circuit according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a PN code generating circuit according to the present invention.

FIG. 6 is a schematic diagram illustrating a configuration example of a comparison circuit.

FIG. 7 is a block diagram showing an embodiment of a communication terminal device using the PN code generating circuit according to the present invention.

FIG. 8 is a block diagram showing a configuration of a conventionally used PN code generation circuit.

[Explanation of symbols]

1 ... GOLD code generation circuit, 2A, 2B ... shift register, 3A, 3B, 4, 13 ... exclusive OR circuit,
11, 21, 31, 41, 52B, 53F ... PN code generation circuit, 12A, 12B ... PN generator, 14 ... M
Advance counter, 15A, 15B ... Initial state loading means,
22, 42 ... Comparison circuit, 32 ... Masking means.

Claims (6)

[Claims] 1. A first pseudo noise generator, a second pseudo noise generator, and a synthesizing means for synthesizing output codes of the first and second pseudo noise generators and outputting as a pseudo noise code. Counting means for counting the number of codes of the pseudo noise code and setting the first and second pseudo noise generators to an initial state when the code number reaches a predetermined value, and for setting the initial state A PN code generating circuit, comprising: initial state loading means for loading initial values into the first and second pseudo noise generators. 2. A first pseudo noise generator, a second pseudo noise generator, and a synthesizing means for synthesizing output codes of the first and second pseudo noise generators and outputting as a pseudo noise code. Monitoring the internal state of the first or second pseudo noise generator, and when the internal state reaches a predetermined state, the first state
And an internal state monitoring means for setting the second pseudo noise generator to an initial state, and an initial state loading means for loading an initial value to the first and second pseudo noise generators when the initial state is set. A PN code generating circuit characterized by comprising. 3. A first pseudo noise generator, a second pseudo noise generator, a mask means for shifting the phase of an output code output from the second pseudo noise generator and outputting the same. The output code of the first pseudo noise generator and the output code of the mask means are combined and output as a pseudo noise code, and the code number of the pseudo noise code is counted, and the code number is a predetermined value. When, the counting means for setting the first and second pseudo noise generators to the initial state, and the initial value is loaded to the first and second pseudo noise generators when the initial state is set. A PN code generating circuit comprising: initial state loading means. 4. A first pseudo noise generator, a second pseudo noise generator, mask means for shifting and outputting the phase of an output code output from the second pseudo noise generator, and The output code of the first pseudo noise generator and the output code of the mask means are combined and output as a pseudo noise code, and the internal state of the first or second pseudo noise generator is monitored. When the internal state reaches a predetermined state, the first
And an internal state monitoring means for setting the second pseudo noise generator to an initial state, and an initial state loading means for loading an initial value to the first and second pseudo noise generators when the initial state is set. A PN code generating circuit characterized by comprising. 5. A first pseudo noise generator, a second pseudo noise generator, and a synthesizing means for synthesizing output codes of the first and second pseudo noise generators and outputting as a pseudo noise code. ,
Counting the number of codes of the pseudo-noise code, and when the number of codes reaches a predetermined value, counting means for setting the first and second pseudo-noise generators to an initial state, and setting the initial state, A PN code generating circuit having an initial state loading means for loading an initial value to the first and second pseudo noise generators, and a transmission section for spectrum spreading the transmission data by multiplying the transmission data by the pseudo noise code. And a receiving unit that multiplies the received data by the pseudo noise code and inverse-spectrum spreads the received data. 6. A first pseudo noise generator, a second pseudo noise generator, and a synthesizing means for synthesizing output codes of the first and second pseudo noise generators and outputting as a pseudo noise code. ,
The internal state of the first or second pseudo noise generator is monitored, and when the internal state reaches a predetermined state, the first state
And an internal state monitoring means for setting the second pseudo noise generator to an initial state, and an initial state loading means for loading an initial value to the first and second pseudo noise generators when the initial state is set. A PN code generating circuit having the same, a transmission section for multiplying transmission data by the pseudo noise code to spread spectrum the transmission data, and a reception section for multiplying reception data by the pseudo noise code and inverse spectrum spreading on the reception data. And a communication terminal device.