JPH03193380A - Forming device for picture - Google Patents

Abstract

PURPOSE:To form a test pattern having approximately the same scale at all times regardless of the density of a picture element by keeping the pattern scale of a test pattern for test printing approximately constant even when the density of the picture element is changed over. CONSTITUTION:A test pattern generator 6 selects or forms a test pattern data optimum to the density of a picture element indicated by a signal DSEL, and outputs a test pattern signal synchronized with a picture clock to a writing control circuit 40, and the writing control circuit 40 outputs the test pattern signal to an LD driver 13 in place of a video signal, thus conducting test printing. A pattern scale is kept approximately constant even when the density of the picture element is changed in the test pattern signal selected or formed by the test pattern generator 6 as a pattern scale stabilizing means at that time. That is, a picture forming device is controlled in the number of revolution proportional to the density of the longitudinal picture elements of a print when the carrying speed of a form is kept constant, and controlled in the number of revolution also proportional to carrying speed when carrying speed is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image forming apparatus, and particularly to an image forming apparatus such as a laser printer capable of switching pixel density.

[Conventional technology]

Personal computer, EWS (Engineering Workstation) 2 document creation devices.

2. Description of the Related Art Image forming apparatuses are used as external or built-in output devices for office automation equipment such as digital copying machines and high-speed facsimile machines.

In response to the demands for improved processing speed and high-quality images of the above-mentioned ○A devices, that is, host machines, optical printers such as LCA (liquid crystal array) printers and laser printers (also called laser beam printers) are being introduced as image forming devices. The use of is increasing.

Both print speeds compared to other printers.

Although it is superior in terms of resolution, unlike LCA printers whose resolution is mechanically fixed, laser printers can change the resolution relatively easily.

Therefore, high-performance laser printers have variable resolution (dpi: number of dots per inch), which can be selected depending on the purpose and font.

Additionally, laser printers with this kind of performance generally test print a predetermined pattern independently, regardless of whether or not a host machine is connected, to check printing operation and evaluate print quality (image quality). There are many things that can be done.

The test pattern data has been developed in advance into a bitmap and stored in the ROM of the printer, or has been formed by combining logic circuits.

[Problem to be solved by the invention]

However, for example, the test pattern shown in Fig. 7, a part of which is enlarged, is created for a specific pixel density, so if you switch to a pixel density that is finer (larger value) than that specific pixel density, If the pixel density is changed to a coarser (lower value) pixel density, the pattern will be reduced as shown in Figure 8 (A), and if the pixel density is changed to a coarser (lower value) pixel density, the pattern will be expanded as shown in Figure 8 (B). turn into.

Therefore, it is important to evaluate the image quality of the test pattern, that is, how smooth or rough the outlines of characters and images become as the pixel density changes, and especially how the density expression of midtones changes in multi-tone images. This has the disadvantage that it becomes impossible to evaluate such matters, and the effectiveness of the test print using the test pattern is greatly reduced.

This invention was made in view of the above points, and even when the pixel density is switched, regardless of the pixel density,
An object of the present invention is to provide an image forming apparatus that always generates test patterns of approximately the same scale, and to facilitate accurate evaluation of image quality through test prints.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a laser diode that outputs a laser beam modulated in accordance with a video signal, a tarock generating means that outputs a tarock as a reference for synchronizing the video signal, and a pixel to be printed. A pixel density switching means for switching the density, a frequency changing means for changing the frequency of the clock output by the clock generation means in accordance with a pixel density signal outputted by the pixel density switching means, and an operation mode switching means for switching the printing operation mode. and,
An image forming apparatus comprising test printing means for performing test printing in accordance with an operation mode signal output by the operation mode switching means.

A pattern scale stabilizing means is provided for keeping the pattern scale of a test pattern for test printing substantially constant even when the pixel density is switched by the pixel density switching means.

Further, the pattern scale stabilizing means may include a programmable counter and a combinational logic circuit that sets the set value of the programmable counter in accordance with the pixel density signal.

[For production]

According to the image forming apparatus configured as described above, even if the pixel density is switched by the pixel density switching means and the frequency changing means changes the clock frequency output by the clock generating means in accordance with the pixel density signal outputted by the pixel density switching means, When the test printing means executes a test print in response to an instruction from the operation mode switching means, the pattern scale stabilizing means acts to keep the pattern scale of the test pattern approximately constant, so that the size of the printed test pattern is It never changes.

In addition, the pattern scale stabilization means is composed of a programmable counter and a combinational logic circuit, and the combinational logic circuit sets a value in the programmable counter according to the pixel density signal, so that the pattern scale is approximately constant regardless of the pixel density. can get.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 6 is a schematic diagram of the internal mechanism of a laser printer showing an embodiment of the present invention.

According to this laser printer, paper 11 is fed by a paper feed roller 12 from one of the upper and lower paper feed cassettes 10a and 10b, for example, a paper stack 11a on the upper paper feed cassette 10a. After being timed by the pair of registration rollers 13, the photoreceptor drum 15 is transported to a transfer position.

The surface of the photosensitive drum 15, which is rotationally driven in the direction of the arrow by the main motor 16, is charged by the charging charger 17, and is scanned with a modulated laser spot from the writing unit 18 to form an electrostatic latent image on the surface. It is formed.

This latent image is visualized by toner supplied from the cartridge 21 to the developing unit 20, mixed with carrier by an agitator 22, and then adhered by a developing roller 23.

This toner image is transferred onto the paper 11 conveyed by the registration roller pair 13 by the action of the transfer charger 25, and the transferred paper is separated from the photoreceptor drum 15 by a separation charger and a separation claw (not shown). , is sent to the fixing unit 27 by the conveyor bells 1 to 26, is pressed against the fixing roller 27b by the pressure roller 27a, and is fixed by the pressure and the temperature of the fixing roller 27b.

The paper 11 leaving the fixing unit 27 is discharged by a paper discharge roller 28 to a paper discharge tray provided on the side of the printer.

The toner remaining on the photosensitive drum 15 is removed and collected by the cleaning unit 31.

Also, above the inside of the printer are printed circuit boards 32 that constitute a controller and an engine driver, respectively.
is installed.

The image data to be written is input to the laser diode 1 of the writing unit 18 as a video signal.

It is converted into a laser beam modulated by the video signal, turned into a parallel or nearly parallel beam by a collimator lens (not shown), and rotated by a scanner motor (described later) to a polygon mirror 34 which together constitutes a rotating deflector. incident.

The laser beams reflected and deflected by the polygon mirror 34 pass through optical systems such as lenses and mirrors (not shown), and are emitted from the window 18a of the writing unit 18, forming a minute spot on the surface of the photoreceptor drum 15. is scanned in its axial direction (main direction).

An image is formed on the photosensitive drum 15 by scanning the modulated laser spot in the main direction and rotating the photosensitive drum 15 in the direction of the arrow (secondary direction).

FIG. 1 is a block diagram showing an example of the configuration of the engine driver control system among the controller and engine driver provided on the printing control circuit board 32 (FIG. 6), and is mainly used for pixel density switching and test printing. Shows related parts.

This control system consists of a CPU (Central Processing Unit) 2 which controls the printer engine and also serves as a frequency changing means and a test printing means, and a DPI which is a pixel density switching means.
Switching device! 3, a mode switching device 4 which is an operation mode switching means, and a clock control circuit 5 which is a clock generation means.
, a test pattern generator 6 as a pattern scale stabilizing means, a write control circuit 40, and a scanner/aperture control circuit 41.

The CPU 2 has a DPI switching device 3. Mode switching device 14.
Clock control circuit 5. The write control circuit 40 is directly connected to the scanner/aperture control circuit 41, and is also connected to the test pattern generator 6 via the write control circuit 40.

The clock control circuit 5 includes, for example, four oscillators (O5C
) 42a to 42d are connected, clocks of different frequencies are input from each, and a clock selected from among them is applied to the write control circuit 40 as a reference clock.

An LD driver 43 is connected to the write control circuit 40, and the LD driver 43 outputs a drive current for the laser diode (LD) 1 in response to a video signal input from the write control circuit 40.

The scanner aperture control circuit 41 includes a scanner motor 44 that rotationally drives a polygon mirror 34 (FIG. 6) that together constitutes a rotary deflector, and a scanner motor 44 that limits the size of the laser beam output from the laser diode 1. The apertures 45 are connected to each other, and the rotation speed of the scanner motor 44 and the opening size of the apertures 45 are controlled.

The CPU 2 is also connected via a controller I/F 46 to a controller 47 that controls the entire printer and develops image data including character codes input from a host machine (not shown) into a bitmap and outputs it as a video signal.

The DPI switching device 3 has a pixel density set, for example, 240 dpi, 3 according to an operator's instruction from an operation panel (not shown) or an instruction from a host machine.
A pixel density signal DSEL corresponding to 00dρi, 400dpi, and 480dpi is output to the CPU 2.

The CPU 2, which is the speed changing means, sends the signal DSEL to the clock control circuit 5. The write control circuit 40 is outputted to the scanner aperture control circuit 41, respectively.

The scanner aperture control circuit 41 controls the rotation speed of the scanner motor 44 according to the applied signal DSEL. That is, the transport speed of the paper 11 (the photosensitive drum 15
If the outer circumferential speed of The number of revolutions of the scanner motor 44 may be kept constant if it is inversely proportional to the pixel density).

Alternatively, the vertical and horizontal opening sizes of the aperture 45 are controlled to values according to the pixel density. That is, although not shown in the drawings, an aperture 45 that is generally provided in a place where the laser beam is parallel or nearly parallel to limit the size (thickness) of the beam is,
Due to light diffraction, the larger the aperture, the sharper the beam spot; the smaller the aperture, the wider the spot. Therefore, if the vertical and horizontal pixel density is thick (and the pixels are fine), the vertical and horizontal sizes of the aperture will be increased to sharpen the spot.
If the pixel density is low (pixels are coarse), the aperture size is made smaller and the spot is controlled to be wider.

The clock control circuit 5 selects the optimum lock among the clocks of different frequencies inputted from the four oscillators 428 to 42d according to the applied signal DSEL, and uses the clock as the reference clock (CLK) in the write control circuit 40. Output to.

The write control circuit 40 controls the scanner motor 4 based on the horizontal pixel density (and the vertical pixel density) based on the applied signal DSEL.
Since the rotation speed of 4) is known, the optimum (negative logic) image clock (/WCLK) is generated using the reference clock input from the clock control circuit 5.

When the mode switching device 4 is set to the normal print mode by an instruction from the operator or the host machine, the write control circuit 40 generates a bitmap (negative logic) in synchronization with the generated image clock. ) Video signal (/VIDEO) to controller I/F4E3
input from the controller 47 via the LD driver 4
3 to drive the laser diode 1, and normal printing is performed.

When the mode switching device 4 is set to the test print mode, the CPU 2, which is the test print means, writes a signal TES to the write control circuit 4 in response to the operation mode signal MSEL output from the mode switching device 4 to set the test print mode.
Output to 0.

The write control circuit 40 closes the gate for inputting the video signal from the controller 47 when the signal TES is input, and inputs the signal DS for instructing the test pattern generator 6 to determine the pixel density.
Outputs EL and image clock/WCLK.

The test pattern generator 6 selects or generates test pattern data that is optimal for the pixel density specified by the signal DSEL, outputs a test pattern signal (/WDATA) synchronized with the image clock to the write control circuit 40, and writes the data. The control circuit 40 sends the test pattern signal (/WDATA) to the LD driver 43 instead of the video signal (/VIDEO).
A test print is performed by outputting to .

At this time, the test pattern signal selected or generated by the test pattern generator, which is the pattern scale stabilizing means, is a signal in which the pattern scale is kept substantially constant even if the pixel density changes as described above.

FIG. 2 is a block diagram showing a first embodiment of this test pattern generator.

The test pattern generator 50 shown in the figure is of a type that selects and outputs a test pattern signal according to the pixel density, and is composed of four ROMs 51 to 54, an address decoder/generator 55, and a latch circuit 56. There is.

The four ROMs 51, 52, 53, and 54 each contain a test pattern of the same pattern scale at a pixel density (d
data expanded into bitmaps according to pi) 240, 300, 400, and 480 is stored.

The address decoder/generator 55 has a signal DSEL.
When inputting , the ROM that stores the data corresponding to the specified pixel density is selected among the four ROMs 51 to 54, and the bit map is sequentially mapped by specifying the address obtained by counting the image clock (/WCLK). Read data.

The data read out in parallel for each predetermined bit is input to the latch@15B, latched once, and then sent to the write control circuit 40 ( 1st
(Figure).

This first embodiment is capable of processing even complex patterns such as characters or multi-gradation figures.

Various test patterns can be generated by exchanging the ROM.

In addition, by changing the mounting location of the ROM, test prints with the same design but with different pattern scales can be obtained.
Plus the same printed circuit board.

It has many advantages, such as being able to accommodate any pixel density or combination thereof simply by replacing the ROM.

FIG. 3 is a block diagram showing a second embodiment of the test pattern generator.

The test pattern generator 60 shown in the figure is of a type that generates and outputs a test pattern signal according to the pixel density, and includes two programmable counters and a combinational logic circuit that sets their set values according to the pixel density. This is an example configured with

This test pattern generation device 60 includes two sets of pattern generation circuits 61 and 71 that generate patterns in the main scanning direction and sub-scanning direction, respectively;
．． It is composed of an OR circuit 6 which synthesizes pattern signals in the main scanning direction and sub-scanning direction generated by 71 and outputs it as a test pattern signal (/WDATA).

Further, the two sets of pattern generation circuits 61 and 71 each have a programmable counter (hereinafter simply referred to as a "counter") 62, 72 and a counter 62, 72 depending on one pixel density.
Data generator 6 that outputs the set value to be set to 72
3, 73i and the output (carry) of counters 62, 72
an F/F (flip-flop) circuit 64.74 that outputs a pattern signal after inverting the pattern signal, and a knot circuit 65.7.
It consists of a 5° knot circuit 66.7B and a control circuit 68.78 consisting of an AND circuit 67.77.

The control circuits 68 and 78 receive negative logic gate signals /LGATE and /FGAT in the main scanning direction and sub-scanning direction, respectively.
In accordance with E, the count/load switching of the counters 62 and 72 and the clearing of the F/F circuits 64 and 74 are controlled.

The signals input to this test pattern generator 60 are a signal DSEL indicating pixel density and a reset signal /RESE.
T and a gate signal in the main scanning direction that is active L° during the effective write period for each line (horizontal scanning line)/
LGATE, the image clock/WCL K output to synchronize each pixel during that time, and active °L° during the effective write period in the sub-scanning direction, that is, when printing for one page is executed. The gate signal /FGATE in the sub-scanning direction and the synchronization signal /LSYN output to synchronize the writing position for each line during that time.
It is C.

When the signal /RESET is input, the counters 62 and 72 are cleared and the test pattern generator 60 enters the standby state.

At this time, each signal /WCLK, /LGATE.

/FGATE, /LSYNC are all °H°, F
/F circuits 84 and 74 are both cleared, so the outputs of their output terminals, that is, the level of point A and point B are both °H.
Therefore, the 0-point test pattern signal /WDATA, which is the output of the OR circuit 69, is also H°, that is, inactive.

When the mode switching device 4 (FIG. 1) is switched to the test print mode and the write control circuit 40 inputs the signal TES and outputs the signal DSEL indicating pixel density to the test pattern generator 60, the data generator E );, 73
inputs the signal DSEL, decodes it, converts it into a corresponding setting value, and outputs it to the counters 62 and 72, respectively.

Hereinafter, the operation of this embodiment will be explained first with respect to the pattern generation circuit 61 in the main scanning direction.

Gate signal/LGATE is inactive °H.

At this time, the output of the NOT circuit 65 is L, and therefore the output of the AND circuit 67 is also L, so the counter 62 is in load mode, and the set value input from the data generator 63 is the next input image clock/WCL. It is only loaded by K and does not function as a counter.

Gate signal /LGATE becomes active °L° and becomes 1
When the image clock/WCLK (hereinafter also simply referred to as "clock") begins to be input, the input from the NOT circuit 65 of the AND circuit 67 becomes H.

On the other hand, the carry which is the output of the counter 62 is L°
Since the input from the NOT circuit 66 remains at "H-", the output from the AND circuit 67 becomes H°.

Therefore, the counter 62 is in counting mode,
It counts up according to the input clock/WCLK.

When all the bits of the counter 62 become °H°, a carry signal is output, and the output Q inverts the F/F circuit 64 which is fed back to the input terminal, and the output of the not circuit on the 6th becomes °L.

Therefore, the output of the AND circuit 67 also becomes L, and the counter 62 enters the load mode.

Therefore, when the next clock is input, the set value is loaded again, the carry disappears, the counter 62 returns to the count mode, and starts counting up from the next clock.

In this way, each time a number of clocks corresponding to the set value are input, a carry is output from the counter 82, and each time the F/
Since the F circuit 64 repeats inversion, the pattern generation circuit 61
outputs a pulse signal with a duty ratio of 1:1 at a constant period.

When the gate signal /LGATE becomes inactive °H, the output of the NOT circuit 65 becomes L", so the AND circuit 6
The output of 7 will also be L°.

Counter 62 is in load mode.

At that time, the F/F circuit 64 is cleared by the falling edge of the output of the NOT circuit 65, and since no carry is input from the counter 62, the output terminal Q remains high, and therefore the OR circuit 65
The current output /WDATA is also held in an inactive high state.

For the pattern generation circuit 71 in the sub-scanning direction, the gate signal /FGATE is used instead of the gate signal /LGATE.
If the clock /WCLK is replaced with a synchronization signal /LSYNC, the result is exactly the same.

Namely. Gate signal/FGATE is active °L°
While printing for one page is being executed, the pattern generation circuit 71 counts the number of lines (scanning lines), and calculates the number of degrees H for each predetermined number of lines.

A pulse signal in which and °L' are inverted is output to the OR circuit 69.

FIG. 4 is a waveform diagram showing an example of various signals of the test pattern generator 60 of the second embodiment shown in FIG. It shows the simplest example of inversion.

Figures 4 (A) to (D) are gate signals/FGA, respectively.
TE, synchronization signal/LSYNC, gate signal/LGATE
, clock/-W CL K is shown, and the same figure (E) to (
G) are the output signals of the pattern generation circuits 61 and 71 and the test pattern generation device 60, respectively, at points A and B;
It shows a level of 0 points.

The gate signal /FGATE shown in Figure 4 (A) is °L°
Then, a synchronization sensor (not shown) detects the laser spot for each line and generates the synchronization signal /LS shown in the same figure (B).
The same figure (C) that outputs YNC and is synchronized with it and is slightly delayed.
The gate signal /LGATE shown in is “L” during the effective scanning period.
During this time, the clock /WCLK, which is also synchronized with the synchronization signal shown in FIG. 3D, is input.

The pattern generation circuit 61 receives the signal shown in FIG. 4(E) (point A and bell) which is inverted by the fall of the clock /WCLK, and the pattern generation circuit 71 receives the synchronization signal /LSYNC.
The signal (8) shown in FIG.
point level) is output to the OR circuit on the 6th day.

Since the positive logic OR circuit 6th acts as a negative logic AND circuit, the test pattern shown in Figure 4 (G) becomes active only when the levels at both points A and B are "L-". Outputs signal /WDATA (0 point level).

As a result, a test pattern of an image as shown in FIG. 7 is printed.

To explain this with a numerical example, as shown in the table above, for example, if one horizontal side of the square black pattern shown in Figure 7 is composed of 20 dots at a pixel density of 400 dpi, then the pattern scale is the same as that of 20 dots. In order to obtain a test pattern of
When pi, each horizontal side is 12, 15, 24
It can be composed of dots.

The signal DSEL representing four types of pixel densities is 2 bits (D
SELI, DSELO) is required, and the pixel density is 240,
300, 400, 480dpiL: corresponding DSEL
(DSELI, DSELO) are 00, 01, 1 respectively.
Let it be 0,11.

The set value of the counter is taken as the two's complement of the number of dots shown in the table, so if the (programmable) counter 62 has a 5-bit configuration (indicated by A, B, C, D, and E from the lowest order), the value is 2' = 32 minus the number of dots, that is, 20 (1010
0), 17 (1001), 12 (01100), 8
(01000) is the respective set value.

In the case of a pixel density of 400 dpi, the counter 62 starts counting the clock from the set value "12" and outputs a carry when the input bit reaches °H°, that is, "31". Therefore, a carry will appear after counting 19 clocks, but in reality it takes 1 time to set the set value.
Since a clock is required, the carry period is 2o clocks, and one horizontal side is composed of 20 dots.

One side in the vertical direction is also composed of the number of lines in exactly the same way.

The logical expressions for deriving the counter setting values from the signal DSEL shown in the table are shown below from the most significant bits.

E=DSELl D=DSELI C=DSEL0 B=OA=DSEL1 ・DSELO=E-DSELO FIG. 5 shows an example of the configuration of the data generator 63 consisting of a combinational logic circuit embodying this logical formula. It is a circuit diagram.

This data generator 63 is composed of two NOT circuits and one AND circuit, and is clear from the formula and diagram except that the input terminal B of the counter 62 is grounded, so a description thereof will be omitted.

If a counter with 6 bits or more is used, all upper digits exceeding 5 bits may be directly connected to the power supply and set to H°.

The data generator 73 may also be configured in exactly the same manner.

Further, the data generator 73 is left as it is, and the period is equal to the initial set value for each line of the counter 62, for example, the number of vertical repeating lines, and the data generator 63
Increase by 1 for each synchronization signal/LSYNC from the output value of (
If you set the counted value (or down) and then set the output of the data generator 63 normally, the square pattern will be transformed into a diamond pattern, and it is also possible to evaluate the image quality of diagonal lines according to the pixel density. become.

According to the second embodiment described above, the test pattern generator, which is a pattern scale stabilizing means, is configured with a programmable counter and a combinational logic circuit that sets its set value in accordance with a pixel density signal, so that a simple circuit can be realized. With this configuration, test patterns of approximately the same scale can always be obtained regardless of pixel density, and are particularly suitable for creating test patterns in which the same pattern appears repeatedly.

Although the present invention has been described above with respect to an example implemented in a laser printer which is an external device such as a personal computer, it can also be applied to an image forming apparatus built into a digital copying machine, a high-speed facsimile machine, etc.

〔Effect of the invention〕

As explained above, the image forming apparatus according to the present invention has
Even when the pixel density is switched, test patterns of approximately the same scale can always be generated regardless of the pixel density, and therefore accurate evaluation of image quality by test prints is facilitated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a control system of an embodiment of a laser printer according to the present invention, and FIGS. 2 and 3 are block diagrams showing first and second embodiments of the test pattern generator, respectively. , FIG. 4 is a waveform diagram showing an example of each part signal of the second embodiment, FIG. 5 is a circuit diagram showing an example of the configuration of the data generator, and FIG. 6 is an example of the internal mechanism of the laser printer. A schematic configuration diagram showing the. FIG. 7 is an enlarged explanatory diagram showing an example of the test pattern, and FIG. 8 is an enlarged explanatory diagram showing an example of the test pattern printed by a conventional printer. 1... Laser diode 2... CPU (frequency changing means, test print means) 3... DPI switching device (pixel density switching means) 4...
Mode switching device (operation mode switching means) 5...Clock control circuit (clock generation means) 6.50.60...
Test pattern generator (pattern scale stabilization means) 61.71... Pattern generation circuit 62.72... Programmable counter 63.73.
...Data generator (combinatorial logic circuit)? ,'ber,uj. Figure 2 Figure 5 Figure 7 Figure 8 (A) CB)

Claims (1)

[Claims] 1. A laser diode that outputs a laser beam modulated in accordance with a video signal, a clock generating means that outputs a clock that serves as a reference for synchronizing the video signal, and a pixel that switches the pixel density to be printed. a density switching means, a frequency changing means for changing the frequency of the clock outputted by the clock generating means in accordance with a pixel density signal outputted by the pixel density switching means, an operation mode switching means for switching a printing operation mode; In an image forming apparatus comprising test printing means for performing a test print in accordance with an operation mode signal outputted by the operation mode switching means, even when the pixel density is switched by the pixel density switching means, the test print for the test print is performed. An image forming apparatus comprising a pattern scale stabilizing means for keeping the pattern scale of a pattern substantially constant. 2. The image forming apparatus according to claim 1, wherein the pattern scale stabilizing means includes a programmable counter and a combinational logic circuit that sets a set value of the programmable counter according to the pixel density signal. Image forming device.