JPH03192839A - Frame aligner - Google Patents

Abstract

PURPOSE:To reduce a minimum allowable phase difference, that is, a delay insertion/removal quantity by providing a frame conversion circuit applying high speed frame conversion in advance when a low speed input signal is overridden onto a high speed output signal. CONSTITUTION:When an input signal DIN is overridden onto an output signal DOUT at the speed of four times that of the input signal, the input signal DIN is fed to a selective circuit 13 and a delay circuit 12 via a frame conversion circuit 16. A frame conversion circuit 16 applies frame conversion compressing a signal in n-bit of one frame to attain the bit arrangement of nearly 4 times of speed to that of the input signal. Thus, after the frame conversion, an elastic storing memory 14 validates once for 4 times to a readout clock RCLK and the compressed n-bit output signal WD is read from the elastic storing memory 14, then an output signal DOUT is obtained, in which the input signal is spread on the frame of the output signal RD of the elastic store memory 14, that is, the input signal DIN is packed from the head of the frame up to the n-th bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame aligner, and more particularly to a frame aligner that is installed in an in-office device of a digital communication network and is used to replace a low-speed digital signal with a high-speed digital signal.

[Conventional technology]

In the current digital communications field, there is a need to perform various signal processing at the digital signal level. Therefore, in order to perform these various types of signal processing, the transmission path interface section of the inter-station relay transmission path and the device-to-device interface section of the device-to-device path within a station are used to process digital signals transmitted from the opposite station or device within the own station or within the device. Usually, a so-called frame aligner circuit is provided, which replaces the clock signal within the device and performs phase synchronization with the reference phase.

As shown in the block diagram of FIG. 3, a conventional frame aligner receives a digital input signal D having a frame synchronization signal in a frame transmitted at an arbitrary phase from an opposing station.
a frame synchronization circuit 31 that receives IN, establishes frame synchronization of the input signal, and issues a write reset signal WR at the same cycle as the frame synchronization; a delay circuit 32 that delays the input signal DIN by a predetermined time; A selection circuit 33 which has the signal DIN as one input and the output signal of the delay circuit 32 as the other input and selects according to the applied selection signal SEL, and the output signal of the delay circuit 33 is connected to the write reset signal WR from the frame synchronization circuit 31. is written with the write clock WCLK at the same speed as the input signal DIN from the given time, and the read reset signals R and R given from the outside write the written signal from the given time at the same speed as the input signal DIN or faster. The elastic store memory 34, which is read using a read clock RCLK having a similar speed, compares the phases of the write reset signals W, R and the read reset signals R, H, and issues a selection signal SEL to the selection circuit 33 according to the phase difference between the two. It is composed of a phase comparator 35 that provides

Next, in the operation of the conventional example, the speed of a signal input at an arbitrary phase from an opposing station or device is usually transferred to a clock of the same speed or a speed close to it, and then output. Therefore, it is sufficient for the conventional frame aligner to have a function of changing the speed of the digital input signal to the same speed or a speed close to it. Since the amount of delay insertion/removal for absorbing the frame phase difference is only a fraction of the number of bits of one frame length of the input signal, one type of delay circuit is provided for the digital input signal. Here, the write frame phase to the elastic store memory is set so that it is possible to write in two types of phases, with and without delay, and when it enters an inappropriate area, by inserting or dropping a delay, it is possible to write into the appropriate area. The phase was corrected so that it entered the range.

[Problem to be solved by the invention]

The above-mentioned conventional frame aligner is designed to replace the speed of the input signal transmitted from the corresponding station or device with a clock at or near the speed of the input signal. When generating an output signal that is transferred to a lock at a higher speed than that, the above-mentioned inappropriate region expands as the disparity between the input signal speed and the output signal speed increases, and the amount of delay insertion and removal increases. This has the disadvantage that the write frame phase approaches the read frame phase, resulting in a wide inappropriate region where data within the same frame moves back and forth between frames. This drawback will be supplementarily explained with reference to the explanatory diagram of the signal arrangement in FIG. Now, n bits of the input signal DIN, which has n bits of data in one frame, are placed in the part from the beginning of the frame to the n bits of the output signal D OUT, which is four times faster than the input signal DIN, in the form of packed data. In case of replacement. In the conventional example, the elastic store memory 34
Since the output signal RD from the frame aligner directly becomes the output signal DoUT of the frame aligner, the input signal DIN is unevenly distributed in the portion of the output signal RD from the beginning of the frame to n bits, and the amount of delay insertion and removal becomes extremely large. It will end up being put away.

[Means to solve the problem]

The frame aligner of the present invention is a frame aligner that superimposes a low-speed digital input signal on a high-speed digital output signal, and receives a digital signal having a frame synchronization signal transmitted at an arbitrary phase from an opposing station,
a frame synchronization circuit that is frame-synchronized with the frame synchronization signal and generates a write reset signal at this frame period; a frame conversion circuit that converts the digital input signal to a read-side signal arrangement that is a high-speed digital output signal; a delay circuit that delays the output signal of the frame conversion circuit by a predetermined time; one input is the output signal of the frame conversion circuit; the output signal of the delay circuit is the other input; Therefore, there is a selection circuit that selects one, and the output signal of the selection circuit is written at the same speed as the input signal from the time when the write reset signal from the frame synchronization circuit is applied, and the read reset signal that is applied from the outside is written. From the time when the signal is applied, the elastic store memory is read out using a clock faster than the input signal speed, and the phases of the write reset signal and the read reset signal are compared and a selection signal is issued according to the phase difference between the two. and a phase comparator for supplying the selection circuit to the selection circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the embodiment shown in FIG. 1, an input signal DIN having n bits of data in one frame is outputted to an output signal DOUT having a speed four times that of the input signal DIN, and data is packed in the portion from the beginning of the frame to n bits. This is a case where the vehicle is transferred in the form of a vehicle. In this embodiment, as can be seen from a comparison with the block diagram of FIG. 3, the input signal DIN is supplied to the selection circuit 13 and the delay circuit 12 via the frame conversion circuit 16. As shown in the explanatory diagram of the signal array in FIG. 2, the frame conversion circuit 16 performs frame conversion by compressing the signal of n bits per frame so that it becomes a bit array that is approximately four times faster than the input signal. . Therefore, by enabling the read clock RCLK in the elastic store memory 14 once every four times after frame conversion and reading the compressed n-bit output signal WD from the elastic store memory 14, the output signal of the elastic store memory 14 is It is possible to obtain a high-speed output signal DoUT in which the input signal is dispersed over the RD frame, that is, the input signal DIN is packed into n bits from the beginning of the frame.

〔Effect of the invention〕

As described above, the present invention provides a frame conversion circuit that performs high-speed frame conversion in advance when converting a low-speed input signal to a high-speed output signal, thereby achieving the minimum allowable phase difference, that is, the amount of delay insertion/removal. It has the effect of reducing

Input reset signal, R, R...read reset signal, SEL...selection signal.

Claims (1)

[Claims] A frame analyzer that replaces a low-speed digital input signal with a high-speed digital output signal receives a digital signal with a frame synchronization signal transmitted at an arbitrary phase from an opposing station, and receives a digital signal with a frame synchronization signal transmitted from an opposing station and performs frame synchronization with the frame synchronization signal. , a frame synchronization circuit that generates a write reset signal at this frame period; a frame conversion circuit that converts the digital input signal to a read-side signal arrangement that is a high-speed digital output signal; and a frame conversion circuit that converts the output signal of the frame conversion circuit in advance. a delay circuit that delays by a predetermined time; and a selection circuit that takes the output signal of the frame conversion circuit as one input, takes the output signal of the delay circuit as the other input, and selects one according to a given selection signal. , the output signal of the selection circuit is written at the same speed as the input signal from the time when the write reset signal from the frame synchronization circuit is given, and from the time when the read reset signal given from the outside is given, An elastic store memory that is read using a clock faster than the input signal speed, and a phase comparison that compares the phases of the write reset signal and the read reset signal, and issues a selection signal according to the phase difference between the two to the selection circuit. A frame aligner characterized by having a container.