JPH03190593A - Two stage speed controller for capacitor run motor - Google Patents

Abstract

PURPOSE:To reduce the size of controller and to suppress adverse thermal effect by performing switching to low speed rotating state with such timing as lowering the voltage across a phase advance capacitor sufficiently. CONSTITUTION:Starting point is set at the first zero-cross point of commercial power supply 1 after input timing of a two stage speed switching circuit specifying a low speed rotating state. A control means Y makes a first signal train, which has been ineffective continuously, effective continuously from the first zero-cross point after switching to the end of an interval, N times (N is an integer) of the half period of the commercial power supply 1, and then makes the first signal train effective. On the other hand, the control means Y makes a second signal train, which has been effective continuously, ineffective for an interval (N+1) times of the half period of the commercial power supply starting from the zero-cross point, and then makes the second signal train ineffective continuously. By such arrangement, the size can be reduced and thermal adverse effect can be suppressed.

Description

[Detailed description of the invention]

<Industrial Application Field> The present invention is a device for controlling the speed of a capacitor run motor in which a phase advance capacitor is connected between two windings into a high speed rotation state and a low speed rotation state in two steps. This invention relates to a two-stage speed control device for a capacitor run motor, in which a protective resistor is connected to protect the switching elements of the motor. <Prior Art> FIG. 9 is a block circuit diagram showing the electrical configuration of a conventional two-stage speed control device for a capacitor run motor, and FIG. 10 is a time chart showing the operation of the two-stage speed control device. The two-phase signal generation means A includes a power supply synchronized clock generation circuit 2 that receives a frequency signal a from a commercial power supply 1 and generates a clock signal having a frequency twice the commercial power supply frequency that rises at the zero-cross timing of the frequency signal a, and a clock It is composed of a 4-bit binary counter 3, a NOT circuit 4, and an XOR circuit 5 for inputting a signal and generating two-phase signals c and d with a frequency obtained by dividing the commercial power frequency by 1/8. . The input terminal of the NOT circuit 4 is the binary counter 3
Q, which outputs a signal q with a frequency divided by 1/8, is connected to a terminal,
The 2 input terminals of the XOR circuit 5 are 1 of the binary counter 3.
It is connected to the Q terminal which outputs the signal p divided by /4 and the Q3 terminal mentioned above. Note that the Ql terminal that outputs the signal m obtained by dividing the frequency of the binary counter 3 by 2 is not used. The exclusive OR output means B is composed of two XOR circuits 6.7 and a Q0 terminal which outputs the signal e of the binary counter 3 divided by 1/1. The two input terminals of the XOR circuit 6 are the Qo of the binary counter 3 divided by 1/1.
The two input terminals of the XOR circuit 7 are connected to the Q0 terminal and the output terminal of the XOR circuit 5. With this configuration, XOR
The output signal f of the circuit 6 and the output signal g of the XOR circuit 7 are, in principle, an exclusive OR signal that makes valid a half period of the frequency signal a of the commercial power supply 1. More specifically, as shown in the waveform of FIG. 10, the exclusive OR signal f is "L" in each half cycle before and after the fall of the two-phase signal C from the XOR circuit 6, and the two-phase The signal is a signal that repeats "H" and "L" alternately every half cycle, except that the half cycle before and after the rise of the signal C is "H" level.In other words, the exclusive OR signal f is
Following a signal consisting of 4 cycles in one period unit, in which a half cycle of commercial power supply 1 is enabled and the following half cycle is disabled in synchronization with commercial power a1, a half cycle of commercial power supply 1 is disabled and the following half cycle is enabled. This is the first signal sequence that is repeated with a signal consisting of four cycles in one period unit. Hereinafter, the exclusive OR signal f will be referred to as a first signal string f. Furthermore, the exclusive OR signal g is at the "L" level in each half cycle before and after the fall of the two-phase signal d from the XOR circuit 5, and is at the "H" level in each half cycle before and after the rise of the two-phase signal d. “H” alternately every half period, except for the point where
”, “L”. This exclusive OR signal g is a second signal train whose phase is delayed by approximately 90 @ with respect to the first signal train f.Hereinafter, exclusive OR signal g The signal g is described as a second signal train g. Therefore, the two-phase signal generating means A that generates the first signal train f and the second signal train g and the exclusive OR output means B are combined together. The selection means C consists of AND circuits 8, 9, NOT circuit 10, and O
It is composed of an R circuit 11. The two input terminals of the AND circuit 8 are connected to the output terminal of the XOR circuit 6 and the input terminal 12 of the two-stage speed switching signal, and the two input terminals of the AND circuit 9 are connected to the output terminal of the XOR circuit 7 and the input terminal 12 of the two-stage speed switching signal. terminal 12
The input terminal of the NOT circuit 10 is also connected to the input terminal 12, and the two input terminals of the OR circuit 11 are connected to A.
It is connected to the output terminal of the ND circuit 9 and the output terminal of the NOT circuit 10. With such a configuration, the selection means C can select the signal generation means X
A first signal train f, a second signal train g, and a two-stage speed switching signal are inputted from "L", where the two-stage speed switching signal specifies a high-speed rotation state of the capacitor run motor 14, which will be described later.
” level, the capacitor/run motor 14 is in the forward rotation state B (the solid line connection state of the forward/reverse switching means), and the AND
A by continuously inhibiting the output of the first signal train f from the circuit 8.
Output signal i of ND circuit 8 (i.e. line switching circuit 1
3 continuously outputs an invalid 1L'' level to the gate terminal G1 of the switching element THI, which will be described later, as a drive signal k) from the AND circuit 9, and continuously outputs the second signal sequence g from the AND circuit 9. A continuous "H" signal is generated by prohibiting the "L" level two-speed switching signal from being inverted by the NOT circuit 10.
゛The level signal is sent to the gate terminal G of the switching element TH2.
2 and the output signal of the OR circuit 11
(that is, the drive signal 1 from the line switching circuit 13), while the two-stage speed switching signal is "H" which specifies the low speed rotation state of the capacitor run motor 14.
``level, the capacitor run motor 14 is in the normal rotation state, and the first signal train f is outputted as the output signal i (drive signal k) in the same waveform state continuously, and The second signal train g is continuously enabled and outputted as the output signal j (drive signal l) in the same waveform state.It should be noted that the reverse state of the capacitor run motor 14 (forward/reverse switching means) In the connection state indicated by the dashed line), the drive signal becomes the signal j, and the drive signal l becomes the signal i. It has a line switching circuit 13 that connects two signal lines from the selection means C to the gate terminals G1 and G2 of the circuit by switching between a solid line state and a broken line state,
Based on line switching, selection means C as drive signals (trigger signals) k and A for both gate terminals Gl and G2.
The output signal i from the AND circuit 8 and the OR circuit 11 in
By switching the output signal j from the capacitor run motor 14, the capacitor run motor 14 is switched between a forward rotation state and a reverse rotation state. The capacitor run motor 14 connects the common terminal 15 of the two-phase first winding W1 and second winding W2 to one pole of a commercial 1fil (same as the one described on the left end), and
A phase advancing capacitor C1 is inserted between the other end of the winding AW1 and the second winding W2. The capacitor run motor drive means E includes a resistor R1 and a switching element TH between the connection point 16 between the first winding W1 and the phase advancing capacitor C1 and the other pole of the commercial power source l.
Insert a series circuit of I ( ) and reactor L1, and also connect the second winding W2 and the phase advance capacitor C.
] A series circuit including a resistor R2, a switching element TH2 (TRIAC), and a reactor L2 is inserted between the connection point 17 and the other pole 18 of the commercial power supply 1. Each resistor R1, R2 is connected to a switching element TI (ITH
This is for protection against 2. Next, the operation of this conventional two-stage speed control device for a capacitor run motor will be explained with reference to the time chart shown in FIG. Now, the line switching circuit 13 in the forward/reverse switching means is in the solid line connection state, and the capacitor run motor 14
Assume that the normal rotation mode is set. In this case, the output signals i and j of the selection means C each become 1 as a drive signal. When the two-stage speed switching signal is at the "ON" level, the AND circuit 8 is non-conducting, so it is not output as a drive signal, and therefore the switching element THI is 0FFL.
The current 11 flowing through the protective resistor R1 becomes zero. Also, although the AND circuit 9 is non-conductive, the output power of the NOT circuit 10 becomes less than "H" level, so the output signal j of the OR circuit 11 becomes a continuous @H2 level, and the line switching circuit 1
3, the output signal j becomes the drive signal p and is applied to the gate terminal G2 of the switching element TH2, so the switching element TH2 becomes continuously conductive, and the protective resistor R2, the switching element TH2, and the reactor L2
An alternating current a1 that is the same as the frequency signal a flows to the capacitor run motor 14 through the capacitor run motor 14.
rotates at high speed. The current from the commercial power source 1 flows directly through the second winding W2, whereas the current flows through the first winding W1 via the phase advance capacitor C1, so the rotation direction of the capacitor run motor 14 is positive. direction of rotation. At this time, the current 12 flowing through the protective resistor R2 becomes an alternating current with a small peak value. Time t. , when the two-stage speed switching signal switches to the "L" level and "H" level, each one of the AND circuits 8 and 9
Since the input terminal becomes “H” level, the XOR circuit 6.7
The first and second signal trains f2g from
It is applied to switching elements THI and TH2 as follows. Therefore, switching elements THI and TH2 each receive a drive signal of 7! It turns ON when it is at “H” level, and turns OFF when it is at “L” level. However, when the two-stage speed switching signal changes from “L” level to “H” level.
At time t0 when the level is changed, the drive signal l becomes “L”
However, due to the nature of the triac, the switching element TH2 does not turn off immediately, and at the zero cross time.

[Turn off with l. After this time t1, the switching elements THI and TH2 are 0N10F.
According to the F operation, a thinned energization waveform of the commercial power supply 1 is applied to the capacitor run motor 14. current jl+12
Looking at the thinned energization waveforms, four waveforms appear on the positive side over four cycles of the commercial power supply period, and four waveforms appear on the negative side over the same four cycles. However, the positive side waveform of the last cycle of the four cycles and the negative side waveform of the first cycle of the four cycles are continuous. When the envelopes of those eight waveforms are regarded as pseudo sine waves, the frequency is 1/8 of the commercial power supply frequency. The envelope of current 11 and the envelope of current 12 are out of phase by approximately 90°. Therefore, the capacitor run motor 14 rotates normally at a low rotation speed of 1/8 of the high speed rotation. When rotating the capacitor run motor 14 by the target number of revolutions, if it is rotated at high speed from beginning to end, the target number of revolutions will be exceeded and the equipment controlled by the capacitor run motor 14 will be overstretched. Control (e.g. speed control of mechanical continuously variable transmission)
However, by shifting the capacitor run motor 14 from a high-speed rotation state to a low-speed rotation state slightly before reaching the target rotation speed as described above, the above-mentioned problem of overshoot can be eliminated and control accuracy can be improved. It's a commercial item. <Problem to be solved by the invention> By the way, when the two-stage speed switching signal changes from the "L" level to the "r" level,
]" level is at random in relation to the commercial power supply cycle. Figure 10 shows just one example of the timing when the two-speed switching signal switches to "H" level. However, in this case, immediately after the switching timing (within half a cycle from the switching timing), the two switching elements T
The timing is such that H1 and TH2 are turned on at the same time. When both switching elements THI and TH2 are turned ON at the same time, as shown in an enlarged view in Fig. 11, the charge accumulated in the phase advance capacitor C1 during high-speed rotation is transferred from the protective resistor R1 to the switching element TH1 to the reactor. 1-Reactor top 2-Switching element TH2=Protective resistor R
It is rapidly discharged in the closed loop path of 2 or the opposite closed loop path, and a surge current +1 is generated in the switching elements THI and TH2! +'ffi! flows. When commercial power B1 is 200 (V), phase advance capacitor C1
The voltage across it exceeds 500 (V). For example, when used for shifting a mechanical continuously variable transmission, the capacitor run motor 14 usually has a power of about 6 to 80 (W), and 10 (A) class triacs are used for the switching elements THI and TH2. The surge-on current of this class of triac is 100 (
Since the size is about A3, the switching elements THI and TH2
The resistance value of the protective resistor RIR2, which is inserted in series in order to protect from the surge current 'IS+129, is set to, for example, 5.1 [Ω], and the switching elements THI, T
Surge current j + flowing through H2! The magnitude of i + I ZS is 50 (A), which is 1/2 of the surge-on current 100 (A).
). Since a thinned-out energization waveform is applied during low-speed rotation, the ratio V/F of the applied voltage and frequency is greatly disrupted, and the average value of each current 'I+'Z during low-speed rotation changes from the average value at high speed (
1,8 (A)), reaching approximately 8 [A]. At this time, the capacity of each protective resistor R1, R2 is 3
2MW), but in the case of the capacitor run motor 14 for speed change of a mechanical continuously variable transmission, it does not rotate all the time, and it rotates at both high speed and low speed. , 80 (W). As described above, in the conventional two-stage speed control device for a capacitor run motor, both switching elements THI and T
Surge current when H2 is simultaneously ON '+3+'
The protective resistors R1 and R2 inserted to protect the switching elements TH1 and TH2 from the 2M are used with large resistance values, which increases the size of the two-stage speed control device and also There was a problem in that the amount of heat generated from the resistors R1 and R2 was large, and the degree of adverse thermal effects on surrounding circuit elements was also high. The present invention was devised in view of the above circumstances, and is designed to switch from a high-speed rotation state to a low-speed rotation state at a timing when the voltage across the phase advance capacitor in the capacitor run motor becomes sufficiently low. It is an object of the present invention to reduce the resistance value of a protective resistor for protecting a switching element from surge current, thereby reducing the size of a two-stage speed control device and suppressing adverse thermal effects. <Means for Solving the Problems> In order to achieve the above object, the present invention has the following configuration. In other words, the two-stage speed control device for a capacitor run motor of the present invention synchronizes with the commercial power supply, enables a half cycle of the commercial power supply, and disables the next half cycle, in units of M cycles (M is an integer of 2 or more). ) followed by a signal consisting of a signal consisting of M cycles in units of one period in which half a cycle of the commercial power supply is invalidated and a signal consisting of M cycles of one period with the half cycle being valid, and this first signal sequence. a signal generating means for generating a second signal train whose phase is delayed by approximately 90 degrees; a first winding and a second winding connected to one pole of a commercial power supply; A capacitor run motor in which a phase advance capacitor is connected between the second winding and a first switching element is connected to one pole of the phase advance capacitor in this capacitor run motor, and a first switching element is connected to the other pole of the phase advance capacitor. 2 switching elements are connected, the other ends of both switching elements are connected to the other pole of the commercial power supply, and both switching elements are connected in a closed loop circuit of the phase advance capacitor, the first switching element, and the second switching element. capacitor run motor driving means into which a protective resistor is inserted; a state in which the output to the switching element is continuously disabled and an output to the second switching element of the second signal train is continuously enabled; and a state in which the output to the second switching element of the second signal train is continuously enabled, and 1
and a selection means for selecting a state in which both outputs of the second signal train are enabled, the input timing of a two-stage speed switching signal specifying the low-speed rotation state. The signal element synchronized with the commercial power source that constitutes the second signal string that has been continuously valid until then starts from the time when the commercial power supply zero-crosses for the first time. It is disabled continuously for a period of (N+1) times the half cycle of the commercial power supply (N is a positive integer), which is the period up to the start of one consecutive cycle of the power supply, and then it is continuously enabled. The invalid first signal train is moved from the above starting point to N times the half period of the commercial power supply (N
is a positive integer). Immediately after the two-stage speed switching signal is switched from the specified state of high-speed rotation to the specified state of low-speed rotation, the two switching elements are simultaneously turned on, and the accumulated charge in the phase advance capacitor, which is a component of the capacitor run motor, is discharged. There are several switching phases of the two-speed switching signal that cause discharge. If the phase in which both switching elements are simultaneously turned on after starting the output of the drive signal for both switching elements for low-speed rotation is the phase in which the voltage across the phase advance capacitor is the lowest, then the protective resistor If the resistance value is the same as before, the surge current flowing through both switching elements will be the smallest. In other words, if the surge-on current of both switching elements is the same as before, and therefore the allowable surge current is the same as before, then it is best to minimize the resistance value of the protective resistor. can. In other words, as the phase in which the output of the drive signal to both switching elements is started, a specific drive signal is selected such that the voltage across the phase advance capacitor is the lowest in the phase in which both switching elements are simultaneously turned on after the output starts. All you have to do is find the output start phase. The inventor of the present invention conducted an experiment from this point of view and found that the second signal sequence starts from the time when the commercial power supply first zero-crosses after the input timing of the two-speed switching signal that specifies the low-speed rotation state. A drive signal is output to both switching elements for low-speed rotation from a phase half a cycle before the start of one continuous cycle of the commercial power supply (hereinafter referred to as a specific phase) of the signal elements synchronized with the commercial power supply that constitute the It has been found that if the switching element is started, the voltage across the phase advance capacitor becomes the lowest when both switching elements are turned on simultaneously for the first time. That is, the output of the drive signal is started for the first signal train after a period of N times the half cycle of the commercial power supply (N is a positive integer) has elapsed from the starting point, and the output of the drive signal is started for the second signal train. For, (N+
1) It has been found that if the test is carried out from the time when double the period has elapsed, the voltage across the phase advance capacitor becomes the lowest when both switching elements are turned ON simultaneously for the first time. To explain this in detail with reference to FIG. 3, the phase of the signal element of the second signal train that is half a cycle before the start of one continuous cycle is the phase φ2 starting from time T2, and this is the specific phase. be. If the output of the drive signal for low-speed rotation to both switching elements is started from this specific phase φ,
After that, in phase φ4 where both switching elements are simultaneously turned on for the first time, the voltage across the phase advance capacitor starts outputting 1 to the drive signal from any phase other than the specific phase φ2. They found that it was the lowest. The above configuration of the present invention is based on such knowledge. The effects of the above configuration of the present invention are as follows. That is, when the two-stage speed switching signal is switched from a high-speed rotation specified state to a low-speed rotation specified state, the control means is continuously disabled until then, regardless of the phase in which the two-speed switching signal is switched. The first signal train that was
While continuing to be disabled for a period of N times the half cycle of the commercial power supply (N is a positive integer) from the above-mentioned starting point, the second signal train that had been continuously enabled until then is It is made invalid for a period of (N+1) times the half cycle of the commercial power supply from the starting point, and then it is made valid continuously. As a result, the output of the drive signal for low-speed rotation to both switching elements is started from the start time of the specific phase, so that the voltage across the phase advance capacitor is the lowest for the above-mentioned reason. Therefore, if the surge-on currents of both switching elements are the same and the allowable surge currents are the same, the resistance value of the protective resistor can be made sufficiently small. <Example> Hereinafter, an example of the present invention will be described in detail based on the drawings. Figure 1 is a block circuit diagram of a two-stage speed control device for a capacitor run motor according to a first embodiment of the present invention. In FIG. 1, the same reference numerals as those shown in FIG. 9 according to the conventional example refer to the same parts as those indicated by the reference numerals in this embodiment. Also, unless otherwise specified,
Even if the connection relationship is 7, the present embodiment and the conventional example have the same configuration. In addition, if only the code names of common parts are listed, A is two-phase signal generation means, B is exclusive OR output means, X is signal generation means, C is selection means, D is forward/reverse switching means, and E is capacitor.・Run motor drive means, ■ is a commercial power supply, 2 is a power synchronization clock generation circuit, 3 is a binary counter, 4 is N
07 circuit, 5°6.7 is the XOR circuit, 8.9 is the AND circuit, 10 is the N07 circuit, 11 is the OR circuit, 12 is the input terminal for the two-stage speed switching signal, 13 is the line switching circuit, 14
is the capacitor run motor, 15 is the common terminal, 16, I
T, 18 is the connection point, Wl is the first winding, W2 is the second winding,
Ct is a phase advancing capacitor, R1 and R2 are protective resistors, and T
HI and TH2 are switching elements using triacs, G1. G2 is a gate terminal, Ll and L2 are reactors, a is a frequency signal, b is a clock signal, c and d are two-phase signals, and e. m, p, q are the output signals of the binary counter 3, f is the first
signal sequence, g is the second signal sequence, '+ J is the output signal,
k and J are drive signals, and h is a two-stage speed switching signal. Hereinafter, in this embodiment, a different configuration from the conventional example will be explained. The reset signal generating means F is constituted by a one-shot multi-by-break which outputs a one-shot signal as a reset signal n at the timing of the rise of the two-stage speed switching signal. The reset signal n is guided to the reset input terminal of the binary counter 3 in the two-phase signal generation means A forming part of the signal generation means X and the reset input terminal of the delay means G. The delay means G is D
It is composed of a flip-flop, and its data input terminal is connected to the DC power supply Vcc, and its clock input terminal is connected to the 1/2 frequency-divided Q terminal of the binary counter 3. The delayed signal r from the Q terminal of the D-flip-flop is
It is configured to lead to one input terminal each of AND circuits 19 and 20 added to the forward/reverse switching means. AND circuit 1
The other one input terminal of 9 is the AND circuit 8 in the selection means C.
The other input terminal of the AND circuit 20 is connected to the output terminal of the OR circuit 11 in the selection means C. Each input terminal of the AND circuits 19 and 20 is connected to the line switching circuit 13. The AND circuit 1920 added to the reset signal generating means F, the delay means G, and the forward/reverse switching means controls the control means Y that enables the first signal train f and the second signal train g at a predetermined timing. It consists of The reset signal generating means F generates a one-shot signal n to the binary counter 3 of the two-phase signal generating means A.
Therefore, after being reset at the input timing of the reset signal n, the binary counter 3 immediately releases the reset and starts counting from the initial state of the binary counter 3. That is, in the case of this embodiment, from the time of the first zero cross after switching the two-stage speed switching signal from high speed rotation to low speed rotation, there is a period during which the first signal train, which had been invalid until then, continues to be invalid. This corresponds to the case where N=1 with respect to "N" in a period N times the half cycle of the commercial power supply 1 for . A D-7 lip-flop (hereinafter referred to as D
- Since the flip-flop (represented by the symbol G) outputs "L level" from its Q terminal upon input of the reset signal n, the AND circuit 1920 is made non-conductive, and the selection means C
It is prohibited to output the output signal f from the AND circuit 8 as a drive signal, and it is prohibited to output the output signal j from the OR circuit 1 as a drive signal l. Since the D-flip-flop G inputs the 1/2 frequency-divided output signal m of the binary counter 3 to its clock input terminal, After half a cycle of the commercial power frequency signal a has elapsed (N=1), the delayed signal r from the Q terminal is set to "H" level and the AND circuit 1
9.degree. 20 is brought into a conductive state, that is, a state where output signals i and j can be output. Next, the operation of this first embodiment will be explained based on the time chart of FIG. 2 and the time chart of FIG. 3, which is a partially enlarged excerpt of FIG. Assuming that the two-stage speed switching signal switches from the "L" level, which specifies high-speed rotation, to the "H" level, which specifies low-speed rotation, at time To', the reset signal generation means F, which constitutes a part of the control means Y, outputs a one-shot reset signal n, thereby resetting the binary counter 3 to the two-phase signal generating means constituting a part of the signal generating means X and the D flip-flop G of the delay means. No matter what count value output state of the binary counter 3 the two-stage speed switching signal is switched to, the binary counter 3 will change to the phase φ at which the switching occurred. i.e. terminals Q3, Ql, Ql, Qo
The output of is o, o, o,. Therefore, counting starts from the start time T1 of the next phase φ1. However, in phase φ1, terminal Q. The outputs of Qz, Ql, and Qo are O, O, 0, 1, and the output signal m of the Q1 terminal of the binary counter 3 is still “L”.
'' level, the delayed signal r from the Q terminal of the D-flip-flop G also remains at the "L" level, and since the AND circuits 19 and 20 in the forward/reverse switching means are in a non-conducting state, the binary counter 3 and the drive signal generated by the selection means C, the output signals i and j as I! are not output to the switching elements THI and TH2.And, at the stage of phase φ, the capacitor run motor Although the voltage VCI across the phase advance capacitor C1 at phase 14 is slightly lower than that at phase φ, it is still quite high.However, since both switching elements THI and TH2 are not ONL, the accumulated charge of the phase advance capacitor CI causes a surge current. The current does not flow to the switching elements TH1, TH2, and the switching elements THI, TH2 are protected.Normally, in the first phase φ1 in the counting process of the binary counter 3, the switching element TH2 is turned on and the switching element TH2 is turned on. A current 12 flows through TH2 in the direction of the arrow in FIG. Winding W1-phase advance capacitor C
1 in a closed loop to lower the voltage VCI across the phase advance capacitor C1 in advance. At the start time T2 of the next phase, the specific phase φ2,
Terminals Qs and QZ of binary counter 3. The outputs of Ql and Qo become 0.0.1.0, and the output signal m of the QI terminal becomes "H" level and is applied to the clock input terminal of the D-flip-flop G. Therefore, the D-flip-flop G receives direct current. The “H” level of the power supply Vcc is latched, and the delayed signal r from the Q terminal changes from the “L” level to “H” again.
" level and activates the AND circuits 19 and 20. As a result, the output signals i and j are supplied as drive signals and as β to the switching elements TH1 and TH2. The first clock signal after resetting the binary counter 3 Since the input timing of S is at time T, that time T
The time τ from 1 to when the delayed signal r returns to the “H” level is equal to a half period of the commercial power frequency signal a. At the specific phase φ, since the drive signal k is at the "H" level and the drive signal l is at the "L" level, the switching element TH
I is turned on, and a current il flows through the switching element THI in the opposite direction to the arrow in FIG. At this time,
The direction of the current flowing through the phase advance capacitor C1 is the same direction as when the phase is φ (direction from connection point 16 to connection point 17)
Therefore, the voltage VCI across the phase advancing capacitor C1 further decreases. However, even at this specific phase φ2, both switching elements THI, TH2, etc. and the phase advancing capacitor C1
A closed loop is not formed due to the switching elements T
A surge current due to the discharge of the phase advance capacitor C1 does not flow through I(1, TH2.The state shifts to a low speed rotation state from this specific phase φ2. In the next phase φ, the switching element TH2 is turned ON. , an electric current mi2 flows through the switching element TH2 in the direction of the arrow in FIG.
6), and the voltage across the phase advance capacitor CI increases. rises. If the switching element TH2 is in phase φ1,
If the ON of is not prohibited, the phase φ. The voltage V Cl across the phase advance capacitor CI is quite high, but since switching element TH2 is actually prohibited from turning on during phase φ1, the voltage VC+ across the phase advance capacitor c1 increases during phase φ3. However, it remains at a low level. At the next phase φ4, after switching the two-stage speed switching signal from the "L" level to the "H" level, both switching elements TH1 and TH2 are simultaneously turned on for the first time, and the accumulated charge in the phase advance capacitor CI changes from C1 to R2→TH2→L2→L1→
It is discharged in a closed loop of THI → R1 → C1, and at this time,
Surge current ' l in both switching elements THI and TH2
3. '! 3 flows. However, as mentioned above, since the voltage VCI across the phase advance capacitor C1 has been lowered to a low level in advance, the surge current '+3+128 is reduced to 1/2 of the surge-on current of 100 (A) of the switching elements THI and TH2. The resistance value of the protective resistors R1 and R2 required to limit the current to 50 (A) may be sufficiently small compared to the conventional example, and is approximately 1/10 of 0.51 (Ω).
It was confirmed that this is fine. The resistance value at this time was the lowest compared to any case where the output of l was started as a drive signal from any phase other than the specific phase φ2. Since the resistance value can be reduced to about 1/10, the protective resistor R1
, R2 is also approximately 8 [W], which is 1/10 of that of the conventional example. In this way, from the specific phase φ2, both switching elements THI
By starting to output l as the drive signal for , TH2, the resistance values of the protective resistors R1 and R2 can be made sufficiently small. It is possible to achieve miniaturization, and by reducing the capacitance, it is possible to minimize the adverse thermal effects of the protective resistors R1 and R2 on peripheral elements. Note that the protective resistors R1 and R2 are connected to the switching element T.
It may be inserted between H1, TH2 and the reactors LL, L2, or it may be inserted separately on both sides of the switching element THITH2. In addition, there is a 1
Only one of them may be inserted as a common protection resistor for both switching elements THI and TH2. This point also applies to the following examples. FIG. 4 is a block circuit diagram showing a set signal generating means and its surroundings in a two-stage speed control device for a capacitor run motor according to a second embodiment. The reset signal generating means F' is a reset signal generating circuit 21 corresponding to the cent signal generating means F of the first embodiment,
D-flip-flop 22. The clock input terminal of the D-flip-flop 22 is connected to the output terminal of the power-synchronized clock generation circuit 2, the mutual terminal is connected to the reset input terminal of the binary counter 3, and the reset input terminal of the D-flip-flop 22 is connected to the output terminal of the power synchronization clock generation circuit 2. It is connected to the output terminal of the circuit 21. The output terminal of the reset signal generation circuit 21 is connected to the reset input terminal of the D-flip-flop G, which is a delay means, and the QI terminal of the binary counter 3 is connected to the D-flip-flop G.
The point that it is connected to the clock input terminal of the clip-flop G is the same as in the first embodiment. Further, other circuit blocks not shown are also similar to those in the first embodiment. The power supply synchronous clock generation circuit 2 and the binary counter 3 constitute a part of the signal generation means X, and the reset signal generation circuit 2
1, the D-clip-flop 22, and the D-flip-flop G constitute a part of the control means Y. Next, the operation of the second embodiment will be explained based on the time chart of FIG. 5, using the third time. As shown by the broken line in FIG. 3 and also shown in FIG. 5, at time T-,' during phase φ-1, the two-stage speed switching signal changes from "L" level, which specifies high-speed rotation, to low-speed rotation. When switched to the specified °H level, the reset signal generation circuit 21, which constitutes a part of the control means Y, outputs a one-shot reset signal n to the D flip-flop 22 and the D-flip-flop G. Reset. D
- When the flip-flop 22 is reset, the reset signal n1 from its mutual terminal becomes "H" level, and the binary counter 3 forming a part of the signal generating means X is reset. Furthermore, the delay signal r becomes "L" level, and the output of the output signals i and j as 1 in the drive signal to the switching elements THI and TH2 is prohibited. The reset signal n of the D-flip-flop 22 has the next phase φ. The binary counter 3 is maintained at the "H" level until the start time T0, and therefore the binary counter 3 is also maintained in the reset state. When the clock signal n is input to the clock input terminal of the D-flip-flop 22 at time T0, the D-flip-flop 22 latches the "H" level of the DC power supply Vcc, and the reset signal n of the corresponding terminal becomes "L". " level, and releases the reset state of the binary counter 3. At this time, the terminals Qs, Q2,
The outputs of Qt and Qo are o, o, o, . It is. At the start time T of phase φ1, the terminals Q3QZ and Qt of the binary counter 3 are inputted by the clock signal S.
, the output of Qo is 0. It becomes O, 0, 1 and starts counting. At this phase φ1, the output signal m of the Ql terminal is “L”
"level, and the delayed signal r of the D-clip flop G
maintains the “L” level, and the switching elements THI, T
The drive signal to H2 continues to be in an output inhibited state of 1. At the start time T2 of phase φ2, terminal Q. The outputs of Qt, Qt, and Qo become O, 0, 1, 0, and the output signal m of the Q terminal becomes "H" level, so D-
The delayed signal r of the flip-flop G returns to the "H" level. As a result, the phase φ2 is also set as a specific phase, and IL is supplied as a drive signal from this specific phase φ2 to the switching elements TH1 and TH2, and the capacitor run motor 14 shifts to a low speed rotation state. In this case, as in the first embodiment, the surge current jll1zJt generated at the timing of simultaneous ON of both switching elements THI and TH2 in phase φ4 and the resistance value of the protective resistors R1 and R2 are set to 0.51 ( Ω], the surge-on current of switching elements THI and TH2 is 1
It becomes 50 (A) which is 1/2 of 00 [A). In the case of this second embodiment, the input timing of the first clock signal after resetting the binary counter 3 is time T0.
Therefore, the time τ1 from time T0 until the delayed signal returns to 'H' level is equal to the commercial power frequency signal a.
It is twice the half period of . In other words, from the time of the first zero cross after switching the two-stage speed switching signal from high-speed rotation to low-speed rotation, the first
Regarding rNJ during the period N times the half cycle of commercial power supply 1 for the period in which the signal train continues to be invalidated, N=
This corresponds to case 2. Note that the current i1 after the specific phase φ2. The waveform of i2 is the first
It is the same as the example. Solution 1: Major advantages and disadvantages FIG. 6 is a block circuit diagram showing a reset signal generating means and its surroundings in a two-stage speed control device for a capacitor run motor according to a third embodiment. The reset signal generating means FIf is composed of a reset signal generating circuit 21 corresponding to the reset signal generating means F of the first embodiment, and two D-flip-flops 22 and 23. That is, in the second embodiment (FIG. 4), D
- A clip-flop 23 is added, and the data input terminal of this D-flip-flop 23 is connected to the D-clip-flop 2.
2, the clock input terminal is connected to the output terminal of the power synchronous clock generation circuit 2, the vine terminal is connected to the reset input terminal of the binary counter 3, and the reset input terminal is connected to the output of the reset signal generation circuit 21. Connect it to the terminal. The power supply synchronous clock generation circuit 2 and the binary counter 3 constitute a part of the signal generation means X, and the reset signal generation circuit 2
1, D-flip-flop 22, 23 and D-flip-flop G constitute a part of control means Y. The rest of the structure is the same as that of the second embodiment, and other circuit blocks not shown are the same as those of the second embodiment. Next, the operation of the third embodiment will be explained based on the time chart of FIG. 7 while using FIG. 3. As shown by the two-dot chain line in FIG. 3 and also shown in FIG. 7, at time T-2' in the middle of phase φ, the two-stage speed switching signal changes from "L" level, which specifies high speed rotation, to low speed rotation. When switching to the "H" level that specifies the signal, the cent signal generation circuit 21, which constitutes a part of the control means Y, outputs a one-shot reset signal n to the D-flip-flops 22 and 23 and the D-flip-flop G. When the D-flip-flop 23 is reset, the reset signal n2 from the 5Φ-times terminal becomes "H" level, and the binary counter 3 forming a part of the signal generating means X is reset. Further, the delay signal r becomes "L" level, and the output signal as a drive signal !, j is inhibited from being output to the switching element THE.TH2.The reset signal n2 from the D-flip-flop 23 is
Next next phase φ. The binary counter 3 is maintained at the "H" level until the start time T0, and therefore the binary counter 3 is also maintained in the reset state. Time T-. When the clock signal Suga is input to the clock input terminal of the D-flip-flop 22, the D-flip-flop 22
latches the "H" level of the DC power supply Vcc, and the output signal of the Q terminal is inverted to "H" level.
Although it is input to the flip-flop 123, the reset signal n2 from the D-flip-flop 23 maintains the "H" level because it is slightly delayed from the input timing of the clock signal n2. Phase φ. At the start time T0, the D-flip-flop 23 latches the "H" level output signal S from the D-flip-flop 22 at the input timing of the clock signal S, and the reset signal n2 is inverted to the "L" level. , cancels the reset state of the binary counter 3. At this time,
The outputs of terminals Q3Q, , Q, , qo are o, o, o, o. At the start time T1 of the phase φ, the clock signal S is input to the terminal Q of the binary counter 3. The outputs of Qz, Q+, and Qo are 0. It becomes O, 0, 1 and starts counting. At this phase φ1, the output signal m of the Q terminal is at "L" level, and the D-flip-flop G
The delay signal r maintains the "L" level, and the output prohibition state of 1 continues for the drive signals to the switching elements THI, TH, and 2. At the start time T of phase φ, terminals Q3Qz and Q
Since the outputs of + and Qo become O, 0, 1, O and the output signal m of the Q terminal goes to the ")I" level, the delayed signal r of the D-flip-flop G returns to the "H" level. As a result, the phase φ2 is also set as a specific phase, and from this specific phase φ2, f is applied to the switching elements THI, T.
H2, and the capacitor run motor 14 shifts to a low speed rotation state. In this case, as in the first embodiment, the surge current '+3ff' t9 generated at the timing of simultaneous ON of both switching elements TH1 and TH2 in phase φ4 increases the resistance value of the protective resistors R1 and R2. , sicΩ] is 50 (A), which is 1/2 of 100 (A), which is the surge-on current of the switching elements THI and TH2. In the case of this third embodiment, the input timing of the first clock signal after resetting the binary counter 3 is time T-
1, the delayed signal r is 1H from that time T −+.
``The time τt required to return to the level is three times the half cycle of the commercial power frequency signal a, that is, the time τt required to return to the level is three times the half cycle of the commercial power frequency signal a, that is, the time τt at the first zero cross after switching the two-speed switching signal from high speed rotation to low speed rotation. This corresponds to the case where N=3 with respect to rNJ during the period N times the half cycle of the commercial power supply 1 for the period in which the first signal train, which had been disabled until then, continues to be disabled. The waveform of the current t,,i, after phase φ2 is the first
It is the same as the example. FIG. 8 is a block circuit diagram showing two-phase signal generating means, exclusive OR output means, and reset signal generating means of a two-stage speed control device for a capacitor run motor according to a fourth embodiment. The binary counter 3 in the two-phase signal generating means A' whose Q0 terminal is a component of the exclusive OR outputting means B has its reset input terminal inputting the reset signal n of the reset signal generating means F. point, and Q
The point that the output signal m of the l@ child is guided to the clock input terminal of the D-flip-flop G, which is the delay means, is the same as in the first embodiment, and the two-phase signal generation means A' and the exclusive OR output means B constitute the signal generation means X, and the reset signal generation means F and the delay means G constitute a part of the control means Y. The two-phase signal generation means A' of this embodiment includes a power supply synchronized clock generation circuit 2 connected to a commercial power supply 1, a 5-bit binary counter 3, an AND circuit 24, 25, and a NOT
It is composed of circuits 26, 27, and XOR circuits 28, 29, and 30. Q2 terminal of binary counter 3 is AN
It is connected to one input terminal each of D circuits 24 and 25. Q
, the terminal is the input terminal of the NOT circuit 26 and the AND circuit 25
and one input terminal of the XOR circuit 29, and the output terminal of the NOT circuit 26 is connected to the other input terminal of the AND circuit 24. The Q4 terminal is connected to an input terminal of the NOT circuit 27 and another input terminal of the XOR circuit 29. The output terminal of the AND circuit 24 and the output terminal of the XOR circuit 29 are connected to the two input terminals of the XOR circuit 30, and the output terminal of the AND circuit 25 and the output terminal of the NOT circuit 27 are connected to the two input terminals of the XOR circuit 28. There is. The Q0 terminal is connected to one input terminal each of the XOR circuits 6 and 7 in the exclusive OR output means B, the output terminal of the XOR circuit 28 is connected to the other input terminal of the XOR circuit 6, and the
The output terminal of the R circuit 30 is connected to another input terminal of the XOR circuit 7. With this configuration, the two-phase signals c and d of the two-phase signal generating means A' are obtained by dividing the commercial power supply frequency signal a by 1/16. In the case of this embodiment, illustration of the time chart is omitted, but
When the two-stage speed switching signal is switched from the L level to the H level, the switching element THI TH2 becomes 0N.
According to the 10FF operation, the commercial power supply 1 is thinned out to the capacitor run motor 14! A waveform is applied. current +1
+'! As for the thinned-out energization waveform, eight waveforms appear on the positive side over eight cycles of the commercial power supply period, and eight waveforms appear on the negative side over the same eight cycles. However, the positive side waveform of the last cycle of 8 cycles and 8
The cycle is continuous with the negative waveform of the first cycle. When the envelope of those 16 waveforms is regarded as a pseudo sine wave, the frequency is 1/16 of the commercial power supply frequency. The envelope of the current i and the envelope of the current 12 are approximately 90" out of phase. Therefore, the rotation speed of the capacitor run motor 14 is 1/16 of the high speed rotation. In this embodiment, the rotation speed is 1/16 of the high speed rotation. Current +1+ only for phases φ2 to φ6 in case
'! Looking at the waveform, it is exactly the same as in Figure 2. That is, after the two-stage speed switching signal is set to the "H" level, the binary counter 3 starts counting at the timing of inputting the first clock signal, and then starts counting for half a cycle of the commercial power frequency signal a from that timing. With a delay, the drive signal k. l is now applied to switching elements TH1 and TH2 (N=1). In this embodiment, the reset signal generating means F' shown in FIG.
If we use
2) If the signal generating means F // of Fig. 6 is used, the above delay becomes three times the half cycle (N = 3).
. In each of the above embodiments, the output signals i and j are used as drive signals,
The AND circuits 19 and 20 for switching between the state of outputting as 1 and the state of inhibiting the output are provided on the input side of the forward/reverse switching means, but instead of this, they may also be provided on the output side of the forward/reverse switching means. A similar effect can be obtained. The two-stage speed control device for a capacitor run motor of the present invention can be used in various types of equipment, and in the case of a capacitor run motor that does not perform forward/reverse rotation, no forward/reverse switching means is required. <Effects of the Invention> According to the present invention, the following effects are achieved. In other words, no matter in which phase the two-stage speed switching signal from high-speed rotation to low-speed rotation is switched, the first signal train, which had been continuously disabled until then, becomes commercially available from the time of the first zero cross after switching. While continuing to be disabled for a period of N times the half cycle of the power supply (N is a positive integer) and then enabled, the second signal train that had been continuously enabled until then is disabled from the time of the zero crossing mentioned above. By disabling it for a period of (N+1) times the half cycle of the commercial power supply and then continuously enabling it, the low-speed rotation for both switching elements is started from a specific phase, that is, the phase where the voltage across the phase advance capacitor is the lowest. Assuming that both switching elements have the same allowable surge current, the resistance value of the protective resistor to protect the switching element from surge current is It can be made sufficiently small, and it is possible to promote miniaturization of the protective resistor and thus the two-stage speed control device, and it is also possible to significantly suppress the adverse thermal influence of the protective resistor on peripheral elements.

[Brief explanation of drawings]

Figures 1 to 3 relate to the first embodiment of the present invention.
The figure is a block circuit diagram of a two-stage speed control device for a capacitor run motor, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is an enlarged time chart of a portion of FIG. 2. 4 and 5 relate to the second embodiment, FIG. 4 is a block circuit diagram showing the reset signal generating means and its surroundings in a two-stage speed control device for a capacitor run motor, and FIG. 5 is a time chart thereof. be. 6 and 7 relate to the third embodiment, and FIG. 6 is a block circuit diagram showing reset signal generating means and its surroundings in a two-stage speed control device for a capacitor run motor;
FIG. 7 is the time chart. FIG. 8 is a block circuit diagram showing two-phase signal generation means, exclusive OR output means, and reset signal generation means of a two-stage speed control device for a capacitor run motor according to a fourth embodiment. 9 to 11 relate to conventional examples, FIG. 9 is a block circuit diagram of a two-stage speed control device for a capacitor run motor, and FIG.
The figure is a time chart, and FIG. 11 is a time chart for pointing out problems.

Claims (1)

[Claims] (1) Following a signal consisting of M cycles (M is an integer of 2 or more) in units of one period, in which a half cycle of the commercial power supply is valid and the next half cycle is invalid, the half cycle of the commercial power supply is synchronized with the commercial power supply. a first signal sequence that repeats a signal consisting of M cycles in units of one period, with the subsequent half period being valid;
A second signal train whose phase is delayed by approximately 90° with respect to this first signal train.
a signal generating means for generating a signal train, a first winding and a second winding connected to one pole of a commercial power source, and a phase advance capacitor connected between the first winding and the second winding. A first switching element is connected to one pole of the phase advance capacitor in this capacitor run motor, a second switching element is connected to the other pole of the phase advance capacitor, and both switching elements are connected to each other. A capacitor run motor in which the other ends are connected to the other pole of the commercial power supply, and a protective resistor for both switching elements is inserted in a closed loop circuit of the phase advancing capacitor, the first switching element, and the second switching element. a drive means, and a drive means for continuously disabling the output of the first signal train of the signal generating means to the first switching element based on a two-stage speed switching signal specifying a high-speed rotation state of the capacitor run motor; The first speed switching signal specifies a state in which the output of the second signal train to the second switching element is continuously enabled and a two-stage speed switching signal that designates a low speed rotation state.
and a selection means for selecting a state in which both outputs of the second signal train are enabled, the input timing of a two-stage speed switching signal specifying the low-speed rotation state. The signal element synchronized with the commercial power source that constitutes the second signal string that has been continuously valid until then starts from the time when the commercial power supply zero-crosses for the first time. It is disabled continuously for a period of (N+1) times the half cycle of the commercial power supply (N is a positive integer), which is the period up to the start of one consecutive cycle of the power supply, and then it is continuously enabled. The invalid first signal train is moved from the above starting point to N times the half period of the commercial power supply (N
A two-stage speed control device for a capacitor run motor, characterized in that the control means is continuously disabled and then enabled for a period of time (where is a positive integer).