JPH0318930A - Microprogram control system - Google Patents

Microprogram control system

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Publication number
JPH0318930A
JPH0318930A JP15379989A JP15379989A JPH0318930A JP H0318930 A JPH0318930 A JP H0318930A JP 15379989 A JP15379989 A JP 15379989A JP 15379989 A JP15379989 A JP 15379989A JP H0318930 A JPH0318930 A JP H0318930A
Authority
JP
Japan
Prior art keywords
microprogram
memory
rom
ram
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15379989A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Izawa
伊沢 三敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15379989A priority Critical patent/JPH0318930A/en
Publication of JPH0318930A publication Critical patent/JPH0318930A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To facilitate the change, the addition, etc., of programs by transferring a microprogram to a 2nd memory from a 1st memory and carrying out the microprogram via the 2nd memory. CONSTITUTION:A ROM 1 has a large capacity and a low speed and is rewritable. A RAM 3 has a medium capacity and a high speed and receives an edited microprogram from the ROM 1 via a transfer circuit 2. The microprogram received from the circuit 2 is changed to a horizontal type from a vertical type. At this time point, the ROM 1 and the circuit 2 are separated from a microprogram control part 8. Hereafter the part 8 carries out the normal microprogram control via the RAM 3. As a result, the microprogram can be easily changed with the inexpensive hardware.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は制御装置の制御方式、 クロプログラム制御に関する。[Detailed description of the invention] [Industrial application field] The present invention provides a control method for a control device, Regarding black program control.

〔従来の技術〕[Conventional technology]

特に水平型マイ 従来からマイクロプログラムはROMに格納され、それ
を逐−読み出すことによりシーケンシャルにプログラム
されるという制御であった。
In particular, horizontal type microcontrollers have conventionally been controlled in such a way that microprograms are stored in a ROM and programmed sequentially by reading them one by one.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本ROMは高速アクセスタイムが必要であり、高速のP
ROM等が使用されることがほとんどてあり、低速な書
き換え可能なIC等は使用されなかった。
This ROM requires high-speed access time, and a high-speed P
ROM etc. were mostly used, and low-speed rewritable ICs etc. were not used.

また、マイクロプログラムにバグがある場合、大程の場
合は数個〜士数個のICを変換しなければいけないとい
う欠点を有していた。
Furthermore, if there is a bug in the microprogram, it has the disadvantage that, in most cases, several to several ICs must be converted.

ここでPROM等を使用せず上位がらタウンロードする
場合には上記ケースは生じないが、書き換え時のロード
プログラムの変更、追加等が生じ、他装置との変更の同
期合せ等多大な時間を費やすという欠点を有していた。
If you download from the upper level without using PROM, etc., the above case will not occur, but the load program will have to be changed or added when rewriting, and it will take a lot of time to synchronize the changes with other devices. It had the following drawback.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、水平マイクロプログラム制御にて制御
を実行する制御装置において、マイクロプログラムを垂
直式に記憶する第一のマイクロブログラムメモリと、水
平式に記憶する第二のマイクロプログラムメモリと、前
記第一のメモリから第二のメモリに編集移送する手段と
を有し、移送された後の第二のメモリ上でマイクロプロ
グラムを実行することを特徴とするマイクロプログラム
制御方式が得られる。
According to the present invention, in a control device that executes control using horizontal microprogram control, a first microprogram memory that stores microprograms in a vertical manner, a second microprogram memory that stores them in a horizontal manner; A microprogram control method is obtained, comprising means for editing and transferring from the first memory to the second memory, and executing the microprogram on the second memory after being transferred.

〔実施例〕〔Example〕

次に本発明の一実施例を示した図面を参照して本発明の
詳細な説明する。
Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

第1図を参照すると本発明の実施例においては、大容量
低速ROM1は8ビット単位に第2図の如<8X6=4
8ビット単位にプログラムされ、第3図の如<1−1.
1−2.〜1−6までで1つの命令コードを形成するも
のとする。
Referring to FIG. 1, in the embodiment of the present invention, the large-capacity low-speed ROM 1 is stored in 8-bit units as shown in FIG.
It is programmed in 8-bit units, as shown in FIG.
1-2. 1 to 6 form one instruction code.

命令記憶(水平マイクロプログラム)RAM3は第3図
の形式にて記憶されている。ROMIからROM3ヘマ
イクロプログラムを移送する移送回路2.RAMB上の
マイクロプログラムをフェッチするMIR(マイクロプ
ログラムインストラクションレジスタ)5、そのフェッ
チしたMIRをもとに演算する高速プロセッサ6、高速
プロセッサの制御のもとに動作する下位制御部7、RA
MB上のアドレスを与えるSC(シーケンスコントロー
ラ)5により構成されている。
The instruction storage (horizontal microprogram) RAM 3 is stored in the format shown in FIG. Transfer circuit for transferring the microprogram from ROMI to ROM32. A microprogram instruction register (MIR) 5 that fetches a microprogram on the RAMB, a high-speed processor 6 that performs calculations based on the fetched MIR, a lower control unit 7 that operates under the control of the high-speed processor, and an RA.
It is composed of an SC (sequence controller) 5 that provides addresses on the MB.

以上のように構成された本発明の詳細な説明する。The present invention configured as described above will be explained in detail.

ROM1は大容量低速ROMであり、また書換え可能な
メモリである。RAM3は中容量高速RAMであり、R
OM1より移送回路2を通してRAM3ヘマイクロプロ
グラムを編集後移送する。この移送回路2は、ワイヤー
ドロジックで構成してもよく、又汎用マイクロプロセッ
サにて構成されていてもよい。このように移送回路2よ
り移送されたマイクロプログラムは、垂直式から水平式
に変更され、この時点でROMI及び移送回路2は、マ
イクロプログラム制御部8より切り離される。
ROM1 is a large-capacity, low-speed ROM, and is also a rewritable memory. RAM3 is a medium-capacity high-speed RAM, and R
After editing, the microprogram is transferred from OM1 to RAM3 via transfer circuit 2. This transfer circuit 2 may be constructed of wired logic or may be constructed of a general-purpose microprocessor. The microprogram transferred from the transfer circuit 2 in this way is changed from a vertical type to a horizontal type, and at this point, the ROMI and the transfer circuit 2 are separated from the microprogram control unit 8.

以後マイクロプログラム制御部8はRAM3゜MIR5
,高速プロセッサ6、SC4,下位制御部7の結合によ
り通常のマイクロプログラム制御を実行する。
From then on, the microprogram control unit 8 uses RAM 3゜MIR5.
, the high-speed processor 6, the SC 4, and the lower control unit 7 are combined to execute normal microprogram control.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、安価なハードウェアで
マイクロプログラムの変更を容易にする効果がある。
As explained above, the present invention has the effect of making it easy to change microprograms using inexpensive hardware.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を部分的にブロック図で示し
た回路図、第2図は第1図で示したROMの内容構成図
、第3図は第1図で示したRAMの内容構成を示す図で
ある。 1・・・大容量低速書き換えROM、2・・・移送回路
、3・・・中容量高速RAM、4・・・シーケンスコン
トローラ(SC)、5・・・マイクロインストラクショ
ンレジスタ(MIR)、6・・・高速プロセッサ、7・
・・下位制御部、8・・・マイクロプロセッサ制御部。
FIG. 1 is a circuit diagram partially showing an embodiment of the present invention as a block diagram, FIG. 2 is a diagram showing the contents of the ROM shown in FIG. 1, and FIG. 3 is a diagram showing the contents of the RAM shown in FIG. It is a diagram showing the content structure. DESCRIPTION OF SYMBOLS 1...Large capacity low speed rewritable ROM, 2...Transfer circuit, 3...Medium capacity high speed RAM, 4...Sequence controller (SC), 5...Micro instruction register (MIR), 6...・High-speed processor, 7・
...Lower control section, 8...Microprocessor control section.

Claims (1)

【特許請求の範囲】[Claims] 水平マイクロプログラム制御にて制御を実行する制御装
置において、マイクロプログラムを垂直式に記憶する第
一のマイクロプログラムメモリと、水平式に記憶する第
二のマイクロプログラムメモリと、前記第一のメモリか
ら第二のメモリに編集移送する手段とを有し、移送され
た後の第二のメモリ上でマイクロプログラムを実行する
ことを特徴とするマイクロプログラム制御方式。
In a control device that executes control using horizontal microprogram control, there is a first microprogram memory that stores microprograms in a vertical manner, a second microprogram memory that stores microprograms in a horizontal manner, and a second microprogram memory that stores microprograms in a horizontal manner. 1. A microprogram control method, comprising means for editing and transferring the microprogram to a second memory, and executing the microprogram on the second memory after being transferred.
JP15379989A 1989-06-15 1989-06-15 Microprogram control system Pending JPH0318930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15379989A JPH0318930A (en) 1989-06-15 1989-06-15 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15379989A JPH0318930A (en) 1989-06-15 1989-06-15 Microprogram control system

Publications (1)

Publication Number Publication Date
JPH0318930A true JPH0318930A (en) 1991-01-28

Family

ID=15570383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15379989A Pending JPH0318930A (en) 1989-06-15 1989-06-15 Microprogram control system

Country Status (1)

Country Link
JP (1) JPH0318930A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0651976A (en) * 1992-07-30 1994-02-25 Mitsubishi Electric Corp Microprocessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0651976A (en) * 1992-07-30 1994-02-25 Mitsubishi Electric Corp Microprocessor

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