JPH03188670A - Read-only memory - Google Patents

Abstract

PURPOSE:To make the rapid operation of the title memory feasible by a method wherein source.drain regions are connected with one another by impurity regions in the inverse conductivity type to that of a substrate while the conductivity type of gate electrodes including a semiconductor layer is selectively specified to be p or n type. CONSTITUTION:A gate insulating film 4 is formed on the surface of an n type Si substrate 1. On the other hand, word wires as gate electrodes and selective wires in parallel with the word wires are provided on the film 4. At this time, these word wires and selective wires are respectively gate structured of metallic silicide layers 6 laminated on poly Si layers 5. Next, the layers 5 are implanted with a p or n type impurity while an enhancement type MOS transistor and a depletion type MOS transistor are selectively formed depending upon the conductivity type of the impurities. Within these MOS transistors, n type source.drain regions 7a-7g are connected by n type regions 8 while a p type well region 2 is formed on the bottom parts of said regions 7a-7g and 8. Through these procedures, the rapid operation is made feasible to increase the current driving capacity.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an NA in which a plurality of MOS transistors are connected in series.
[Summary of the Invention] The present invention relates to a NAND type read-only memory device in which a plurality of MOS transistors formed on a semiconductor substrate are connected in series, in which the source and drain regions are connected to the substrate. By connecting with an impurity region of the opposite conductivity type and selectively setting the conductivity type of the gate electrode including the semiconductor layer to the first or second conductivity type, shortened turnaround time (TAT) and high-speed operation are realized. It is something to do.

[Prior Art] In a read-only memory device called a mask ROM, information is written during the manufacturing process. Such mask ROMs are broadly divided into NOR type and NA type.
There is an ND type. Among these, the NOR type mask RO
Although M has the advantage of short TAT, it is difficult to integrate it. On the other hand, NAND type mask R
Although OM is easy to achieve high integration, conventional NAND-type mask ROM requires E/ROM, which selectively forms enhancement-type and depletion-type MOS transistors, for example.
In the D configuration, it is necessary to ion-implant impurities into the channel slope before forming the gate electrode, and the TAT becomes long (see, for example, Japanese Patent Application Laid-Open No. 52-30388).

In order to shorten this TAT, a technique is also known in which ions are implanted into the gate electrode after the formation of the gate 74 pole.
After forming the OS transistor, impurities are selectively introduced into the gate electrode using a mask, and the work function thereof is changed to write information.

[Problem to be solved by the invention]

However, with the technology described in Japanese Patent Application Laid-Open No. 63-228745, it is possible to shorten the TAT, but each MO
The operating speed of the S transistor is not sufficient,
Furthermore, when higher integration is attempted, short channel effects and the like also become a problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a read-only memory device that can shorten TAT, operate at high speed, and prevent short channel effects even when highly integrated.

[Means for Solving the Problems] In order to achieve the above-mentioned object, a read-only memory device of the present invention includes a second semiconductor substrate formed on a semiconductor substrate of a first conductivity type.
In a read-only memory device formed by connecting a plurality of conductivity type channel MO3I transistors in series, the source/drain regions of each MO3) transistor are connected by an impurity region of a second conductivity type, and each of the MO3) The gate electrode of the transistor includes at least a semiconductor layer, and the semiconductor layer is selectively of a first conductivity type or a second conductivity type.

[Effect]

In the read-only memory device of the present invention, since the gate electrode is selectively set to the first or second conductivity type, the dark voltage of the MOS transistor changes depending on the conductivity type, and information is transmitted. It will be written. The source and drain regions of the MOS transistor constituting the memory cell are connected to the semiconductor substrate through an impurity region of the opposite conductivity type.

Therefore, since there is no pn junction in the channel region, short channel effects can be suppressed. Further, for example, if the 11th conductivity type is p type and the second conductivity type is n type, a buried channel will be formed in the enhancement type MOS transistor, and its mobility will be close to that of the bulk. .

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

The read-only memory device of this embodiment is a NAND-type mask ROM, in which the source/drain regions of the MOS transistor array are connected to impurity regions of the opposite conductivity type to the substrate, and impurities are selectively introduced with gate 1 as the pole. In this example, information is written.

First, its structure will be explained with reference to FIGS. 1 to 3. A p-type well region 2 is formed on an n-type silicon substrate 1. On the surface of this p-type well region 2,
Element isolation regions 3 are selectively formed. A gate insulating film 4 is formed on the surface of the active region surrounded by the element isolation region 3.
is formed. As shown in Fig. 1, the planar pattern of this active region consists of two rows of strip-shaped patterns whose longitudinal direction is the X direction, one end of these patterns becomes a ground voltage line continuous in the Y direction, and the other The ends are widened and continuous for the common contact of the bit lines.

On the gate insulating film 4, there are word lines WL, ~W, which are a plurality of gate electrodes extending from each other in the Y direction at predetermined intervals.
Selection lines SL, SL are also provided in parallel to word lines WL, -WL. Here, these word lines WL to WL and selection lines SL, SL,
Each has a gate structure in which a metal silicide layer 6 such as a tungsten silicide layer is laminated on a polysilicon layer 5 which is a semiconductor layer. Then, n-type impurities or n-type impurities are ion-implanted into this polysilicon layer 5, and depending on the conductivity type, an enhancement type MOS transistor or a depletion type MOS transistor is formed.
Transistors are selectively formed. Furthermore, by forming the metal silicide layer 6 on the polysilicon layer 5 into which impurities of different conductivity types are introduced, even if a junction occurs in the polysilicon layer 5, the polysilicon 115 of both conductivity types can be Electrical connection is made via the metal silicide layer 6.

These word lines WL, ~WL, and selection lines SL, SL,
In the lower part of the gate insulating film 4 in which the n-type well region 2 is formed, source/drain regions 7a to 7g are formed on the surface of the n-type well region 2 by the word lines WL to WL, the selection lines SL, SL, and the self-alignment lines. It is formed. These source/drain regions 7a to 7g are composed of n-type impurity diffusion regions, and the source/drain region 7a at one end is used as a common ground voltage line for each MOS transistor array, and the source/drain region 7a at the other end is used as a common ground voltage line for each MOS transistor row.
The drain region 7g is used as a common bit line contact region for four MOS transistor arrays. The region between these source/drain regions 73 to 7g is usually MO
S) In the MOS transistor of this embodiment, n-type impurity regions 8 are formed in regions between source and drain regions 7a to 7g, which are regions used as channel formation regions of transistors.

In this embodiment, a plurality of MOS transistors in which impurity regions 8 are formed in the regions between each source/drain region 7a to 7g are connected in series to form a MOS transistor string, and are used as memory cells. Four MOS transistors are connected in series, and two selection transistors are added. Note that the number of MOS transistors connected in series is not limited to four in this embodiment, but can of course be set to any number. As shown in Figure 6, two series M
O3) A transistor array is formed, one series MO5) transistor array is composed of nMOSMOS transistors Ql, T1.
．． T2, and the other series MOS transistor is n
MOsMOS transistor Qs, T3, T-
Consisting of In the equivalent circuit of FIG. 6, MOS transistor Q0. QIQs, Qa, T,.

T4 is a depletion type (normally-on type), and includes MOS transistors Qz, Q4. Q? ,
Qs, Tj, and Tj are enhancement type (normally off type), that is, MOS transistors Q
+, Qz-Qs, Qb, 'r1. The polysilicon layer 5 of the T- gate electrode has n-type ORN properties due to ion implantation of n-type impurities. Further, the polysilicon layer 5 of the gate electrode of the MOS transistors Qz, Q-, Q-, Qs, Tt, and Tx has n-type conductivity because n-type impurities are introduced therein.

FIGS. 4 and 5 are cross-sectional views of such MOS transistors in which the polysilicon layer 5 of the gate electrode has different conductivity types. Figure 4 shows a depletion region type MOS.
This is an example of an l-transistor, and since the polysilicon layer 5 has an n-type conductivity type, its dark value voltage is -0,
It is set to about 5 to -0, IV (volts). Further, FIG. 5 shows an example of an enhancement type MOS transistor, and since the polysilicon layer has an n-type conductivity type, its dark value voltage is 0.6 to 1. Set to OV (volts). In this way, there is a gap of approximately 1.0 mm between the n-type polysilicon layers. There is a work function difference of about IV, and by introducing such impurities of different conductivity types, it is possible to selectively obtain depletion type and enhancement type MOS transistors. In addition, especially in an enhancement type MOS transistor, the polysilicon layer 5 of the gate electrode is of the n-type, the channel region consists of the n-type impurity region 8 formed between the source and drain regions 7, and the bottom Since the P-type well region 2 is formed, the channel does not become a surface channel but becomes a buried channel.

Therefore, electrons passing through the channel are not affected by adverse effects such as surface scattering, and have a mobility close to that of the bulk, which is advantageous in terms of high speed, current drive ability, etc. Furthermore, as shown in FIGS. 4 and 5, in each MO3) transistor, the source and drain regions 7 and 7 are connected by an n-type impurity region 8, and there is no pn junction between them. Therefore, the short channel effect can be suppressed, and the depletion layer spreads on the drain surface, so that the capacitance between the gate and the drain is reduced, and the speed can be increased.

The gate electrode of the MOS transistor array of this embodiment is selectively formed into a depletion type and an enhancement type depending on the work function difference caused by the conductivity type of the impurity applied to the polysilicon layer 5. An aluminum-based interconnection layer 10 functioning as a bit line is formed so as to connect the glabellar insulating film 9 and the gate insulating film 4 to the contact hole 9 opened above the source/drain region 7g. The longitudinal direction of this aluminum-based wiring layer 10 is the X direction in the figure, and two series-connected MO
In the region between the 3I-transistor rows, the structure is such that it overlaps the element bone # region 3 with the glabella insulating film 9 interposed therebetween.

Next, a method for reading information will be briefly explained with reference to FIG. - For example, when reading data from the MOS transistor Q2, the selection line SL becomes "H" level (high level), and the MOS transistor array Q1 to T2 side is selected. At the same time, the word line WL,
is set to the "L" level (low level average OV), and the other word lines WL, , WL, , WL, are set to the "H" level.

If the MOS transistor Q2 is of the depletion type, a current flows even when the potential of the word line W L 2 is at the "L" level, so that the potential of the bit line is lowered to the ground level. On the other hand, MOS transistor Q
If Q2 is of the enhancement type, the Mos transistor Q2 is turned off, so the potential of the bit line is not lowered, and data is read out due to the difference in potential of the bit line.

Next, an example of the method for manufacturing the mask ROM of this embodiment will be explained with reference to FIGS. 7a to 7C.
As shown in FIG. 2, an n-type well region 22 is formed on an n-type silicon substrate 21.

After forming this n-type well region 22, element isolation 8J [Mi23] made of a thick silicon oxide film is formed by selective oxidation. Subsequently, an n-type impurity region 28 is formed on the surface of the active region surrounded by the element isolation region 23. This n-type impurity region 28 functions as a region that electrically connects between the source and drain regions. Also, before and after forming this n-type impurity region 28, a gate insulating film 24 is formed on the n-type impurity region M28.

Next, an n-type polysilicon layer 25 is formed on the entire surface by a method such as CVD, and a metal silicide layer 26 is formed on the entire surface of the n-type polysilicon layer 25. The polysilicon layer 25 and the metal silicide layer 26 are patterned into parallel strip patterns in the memory cell area by etching using a required resist layer, etc. Next, as shown in FIG. As shown, using the patterned metal silicide layer 26 and polysilicon layer 25 as well as the element molecule 11 region 23 as a mask, self-alignment lines are formed.
ion implantation of type impurities. By this ion implantation, source/drain regions 27a to 27g are formed on the surface of the P-type well region 22 for each gate electrode and self-alignment line. Since an n-type impurity region 28 is previously formed on the surface of this n-type well region 22, each source and
The drain regions 27a to 27g are formed under each gate electrode.
The connection is made through the impurity region 28 of the mold.

In this state, or with the interlayer insulating film and the bit line arranged, it enters a standby state for obtaining four programs. When the program is obtained, a mask is formed according to the program, and the resist layer 29 is selectively exposed and developed according to the mask, as shown in FIG. 7C. Then, ion implantation is performed using the resist Ji29 as a mask.

This ion implantation is to selectively implant n-type impurities into the polysilicon layer 25 of the gate electrode. By this ion implantation, the polysilicon layer 25, which was initially of n-type conductivity, is selectively converted to n-type conductivity. In this way, a MOS in which the gate polysilicon R25 is made n-type
) The transistor is of the depletion type, and the n-type impurity is not introduced by the mask of the resist layer 29.) The transistor is of the enhancement type.

Thereafter, the mask ROM is completed according to normal steps.

Note that in the above manufacturing method, n-type polysilicon N25
Although n-type impurities are selectively doped into the n-type polysilicon layer, n-type impurities may also be selectively doped into the n-type polysilicon layer.
The pure polysilicon layer may be selectively bombarded with n-type and n-type impurities.

〔Effect of the invention〕

In the read-only memory 7J of the present invention, since information is written by introducing impurities into the semiconductor layer of the gate electrode, the TAT The time can be shortened.

In addition, since the source and drain regions of multiple MO3I-transistors connected in series are electrically connected through an impurity region of the opposite conductivity type to the substrate, no pn junction is formed in the channel, resulting in a short channel effect. can be suppressed. Further, in each MOS transistor, a depletion layer spreads on the drain surface, and an enhancement type MOS transistor becomes a buried channel, so that high-speed operation is possible and current drive capability is improved.

[Brief explanation of drawings]

1 is a plan view of essential parts of an example of a read-only memory device of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG. 3 is a sectional view taken along the line ■-■ in FIG. FIG. 4 is a cross-sectional view of the depletion type MOS transistor in the above-mentioned example, FIG. 5 is a cross-sectional view of the enhancement-type MOS transistor in the above-mentioned example, and FIG. 6 is an equivalent circuit diagram of the memory cell portion of the above-mentioned example. , and FIGS. 7A to 7C are process cross-sectional views for explaining an example of the method for manufacturing a read-only memory device according to the present invention according to the steps. 1...Silicon substrate 2...Well head mounting 3...Element isolation region 4...Gate insulating film 5...Polysilicon layer 6...Metal silicide layers 7a to 7g...Source/drain Region 8... Impurity region 9... Interlayer insulating film lO... Bit line ■-■ Latitude plane Figure 3

Claims (1)

[Claims] In a read-only memory device formed by connecting in series a plurality of MOS transistors of a second conductivity type channel formed on a semiconductor substrate of a first conductivity type, the source/drain regions of each of the MOS transistors are impurities of the second conductivity type. A read-only memory device characterized in that the gate electrodes of each of the MOS transistors include at least a semiconductor layer, and the semiconductor layer is selectively of a first conductivity type or a second conductivity type.