JPH03187526A - Digital signal processor - Google Patents

Abstract

PURPOSE:To reduce encoding error by using an unused area in a block to be generated in variable length encoding, for which fixed length control is executed, for the encoding error information of the other block. CONSTITUTION:A digital signal processor is composed of a variable length encoding circuit 1, encoding error extracting circuit 2, idle information extracting circuit 3, encoding circuit 4 and encoding error information inserting circuit 5. The information of the encoding error in the small block under the control of a high frequency component are inserted to the unused area of a variable length encoding output in the small block under the control of a low frequency component. Thus, the encoding error can be reduced and over a long range, the same performance as the conventional variable length encoding, for which fixed length control is executed, can be obtained.

Description

[Detailed Description of the Invention] Industrial Application Field of the Invention C-1 Conventional technology related to a digital signal processing device suitable for highly efficient encoding of highly redundant information such as images From the viewpoint of information transmission efficiency Kaita: It is known that variable-length coding is superior to fixed-length coding, and although variable-length coding is often used for high-efficiency coding of images in the transmission field, image signals are generally low-quality. The energy of the frequency component is large, and the energy decreases as the frequency increases. Therefore, in order to utilize this image feature, for example, Hadamard transform is performed to divide the input signal into frequency components. Short code words can be assigned to low-frequency components with high energy, and longer code words can be assigned as the energy decreases.Since the amount of energy is proportional to the frequency of occurrence, the probability of occurrence of short code words is high, and the viscosity of this When the energy distribution is biased, the advantage of using variable length codes is that the overall bit length can be shorter than when code words of the same length are assigned to all frequency components. However, here: Variable-length coding is not an unlimited variable-length code, but a variable-length code that involves control to set the length to a fixed length in units of image frames or fields. Furthermore, the quality of the transmission path is good and the probability of data errors is sufficiently small, so the effect of errors on the transmission path on image quality can be almost ignored.

Problems to be Solved by the Invention In the case of digital VTRs for home use, high-efficiency encoding is essential for recording high-quality images over long periods of time. In contrast, the playback error rate is significantly different from the error rate of the transmission path.In digital VTRs, there are not only random errors but also concentrated large-scale errors called burst errors caused by media defects on the tape. There are many data errors L1 Digital VT where a wide variety of errors occur like this
Regarding R (Part 1) Fixed length control in shorter units is required instead of fixed length control in frame units as in image transmission. Although it is impossible to take full advantage of the advantages of 4F, as shown earlier, the energy of low frequency components in images decreases as the frequency increases. However, this is true for the entire screen. Or, it is a property of several screens, and when the screen is divided into small blocks, it does not mean that the low frequency energy is large for all the small blocks.
Although there are small blocks where high frequency components are dominant, conventional variable length coding is concerned with small blocks where high frequency components are dominant! Tomo: The probability of occurrence of long codewords increases,
It is not possible to fit the variable-length encoded output within a short fixed length while maintaining the accuracy of the input data (1) In other words, when performing fixed-length control over a short range, The variable-length encoded output of all the data in a small block cannot be contained within a fixed length without reducing the accuracy (quality) of the input data.

Continuing to convert conventional variable length coding technology into digital VTR
When applied to (friend), there is a major problem in that it is necessary to shorten the recording time or to tolerate deterioration in image quality in order to secure the recording time.

Means for Solving the Problems The present invention (Part 1) A high-efficiency coding technology that solves the problems in conventional variable-length coding and has a sufficient redundancy removal effect even with fixed-length control over a short range, and is suitable for digital VTRs. The purpose is to provide

This objective will be achieved by the following new means.

variable length encoding means for variable length encoding input data and controlling the data length of the variable length encoded output for a plurality of input data to be kept below a certain value; empty information extraction means for obtaining the difference between values;
encoding error extraction means for extracting the encoding error by the variable length encoding means; encoding error re-encoding means for encoding the output of the encoding error extraction means within the difference; and the variable length encoding A digital signal processing device comprising encoding error signal insertion means for inserting the output of the encoding error re-encoding means into the output of the encoding error re-encoding means. By inserting encoding error information into the unused area of the variable-length encoded output that occurs within a small block where low frequency components are dominant, encoding errors can be reduced and fixed-length control can be performed over a long range. Performance equivalent to conventional variable length encoding can be obtained.

Embodiment FIG. 1 shows a block diagram of an example of a circuit configuration for realizing a digital signal processing apparatus according to a first embodiment of the present invention. In this embodiment, the following assumptions are made.

The variable-length encoded output for l2M input data is always contained within a fixed-length block of length L.

2: The m-th data among the M input data is converted into Am(
1≦m≦M), the variable length encoded output for this Am is C
m, and furthermore, the encoding error regarding this Am is dm(
≧0).

The strain temperature ζ in this case includes, for example, square strain and absolute value strain.

In FIG. 1, the variable length encoding circuit l has input data Am
is subjected to variable length encoding so that the encoded output Cm falls within a predetermined fixed length. The encoding error extraction circuit 2 obtains and holds the input signal Am of the variable length encoding circuit 1 and the encoding error caused by variable length encoding. For example, in the previous example, for an input signal in which high frequency components are dominant (above), a coding error occurs due to variable length coding due to aborting of coding, etc.

On the other hand, the sky information extraction circuit 3
The length F of the unused area of the encoded output is determined and held within a fixed length. For example, in the previous example, for an input signal dominated by low frequency components, the probability of occurrence of a code word shorter than ζ is high, and the variable length encoded output is well within L, so a relatively large unused area is generated. Encoding error re-encoding circuit 4 (like
Based on the unused area length information F held in the empty information extraction circuit 3, the encoding error signal from the encoding error extraction circuit 2 is encoded so that it falls within the unused area F. To illustrate, let the number of fixed-length blocks of length L be N, and the first block among them is Bi (only L
1≦i≦N). Further, let Di be the sum of encoding errors dm regarding block Bi, and let Fi be the length of the unused area. For blocks where coding errors occur, Fi
For the block where =O5Fl>0, Di = 0. Here, the j-th block has an unused area Fj (>O
), and the encoding error of the th block is Dk(〉
0). In this case, even though the sky information extraction circuit 3 holds the values of j and Fj, and the encoding error extraction circuit 2 holds 4L of k, dm, and Dk, the encoding error re-encoding circuit 4 (or Based on the values of j and Fj obtained from the sky information extraction circuit 3, the coding error dm (1≦m≦M) obtained from the coding error extraction circuit 2 is encoded so as to fit within Fj, and the unused area of block Bj is At this time, information indicating that the encoding error belongs to block Bk is also inserted into the unused area of block Bj. The coding error signal (i) of the inserted block Bk is correctly added to the decoded signal of the original block Bk during decoding, and the coding error of block Bk is greatly reduced. If length control can only reduce the L encoding error, then the fixed length control range can be shortened, making it possible to significantly reduce the circuit scale compared to conventional variable length encoding circuits. Now, for the sake of brevity, we assume that a fixed-length block has a variable-length encoded output and a re-encoded output for encoding errors. It goes without saying that a similar effect is obtained when adding L. In this embodiment, only the case where the encoding error information of block Bk is inserted into block Bj is illustrated. If unused areas exist in multiple blocks, the encoding error re-encoding circuit 4 inserts, for example, encoding error information of a block with a large encoding error into a long block of unused areas. If we add a function to do this, we can insert the coding error information into other blocks without any problems, or we can easily insert the coding error information of multiple blocks into the unused area of the l block. FIG. 2 shows a block diagram of an example of a circuit configuration for realizing a digital signal processing apparatus according to an embodiment of the present invention.The following assumptions are also made in this embodiment.

The variable length encoded output for M input data is of length L
The length L must be within the fixed length block.
', this length Lo is used as the block length for the input data. 2: The m-th data of the M input data is Am
(1≦m≦M), let the variable length encoded output for this Am be Cm, and furthermore, let the encoding error regarding this Am be dm
(≧0) and the distortion temperature g1 in this case For example, in FIG.
The coded output Cm is variable-length coded so that the coded output Cm falls within a predetermined fixed length.
When the length of the sum of (1≦m≦M) is less than or equal to L′, the block boundary is placed at the position of “L”. For example, in the previous example, for an input signal in which high frequency components are dominant, (
Coding errors due to variable-length coding may occur due to aborting of coding, etc. The sky information extraction circuit 3 extracts L and L for each block.
For example, in the previous example, for an input signal in which low frequency components are dominant, the probability of generating a short code word is high, and the variable length encoded output is unlikely to be sufficiently within L.
Based on the length information F of the unused area held in the air information extraction circuit 3, the encoding error signal from the encoding error extraction circuit 2 is generated. A new block is generated by encoding it so that it fits within the unused area F. To give a concrete example, let the number of fixed-length blocks of length L be N, and this first block be Bi ( ,,
1≦i≦N). Also, let Di be the sum of coding errors dm for block Bi, and let Fi be the length of the unused area.
= 0, and for the block where Fi > O, Di = O. Here, the unused area Fj (>O
), and the encoding error of the th block is Dk (
〉0) and sum In this case, the sky information extraction circuit 3 uses j and Fj
The encoding error extraction circuit 2 holds the value of k
The coding error blocking circuit 6 (friends) retains the values of j and Fj from the air information extraction circuit 3. The coding error of block Bk obtained from the coding error extraction circuit 2 is the coding error dm (1≦ m≦M) is encoded so that it fits in Fj to generate a new pro-tsuk BN+1. At this time,
Information indicating that the block BN+1 is a coding error of block Bk is also inserted into block BN+1. This resulting coding error signal of block BN+1 is correctly added to the decoded signal of the original block Bk during decoding, greatly reducing the coding error of block Bk.

As shown above, this embodiment can only reduce the k coding error by fixed length control over a short range. In order to simplify the explanation, in this example, parity for error correction is completely omitted. In this embodiment, only the case where a new block BN+1 is generated from the encoding error information of block Bk has been exemplified. There may be cases where an unused area exists in a block. In this case, a function is added to the encoding error blocking circuit 6 to preferentially encode encoding error information of a block with a large encoding error, for example. Although the encoding error information can be encoded without any problems, it is unnecessary from the perspective of reducing encoding errors.When actually recording data, it is better to also insert the length information of the block into the block concerned. There are cases where it is good
Zunawa board When it is impossible to detect block synchronization due to errors that occur during the playback process of a digital VTR.
Even when attempting to supplement this undetected block synchronization from a preceding block, digital data is generally transmitted and recorded using a block configuration as shown in FIG. 3. In FIG. 3, the synchronization pattern section is necessary to find the break between blocks and ensure block synchronization by detecting a special pattern inserted here during reproduction of recorded data.

For example, the block number of the block concerned is inserted in the additional information section, but the encoded data and parity for error correction of the encoded data are inserted in the data section. Since there is no advantage in making it variable, it is fixed at a constant value.Therefore, there is no need to insert block length information into a block, and it is not necessary to insert block length information into a block. However, in this embodiment, the length of each block is different, and this block data with non-constant block lengths can be recorded as a recording block of a digital VTR, for example. On the other hand, the feature of this embodiment is that the block length is not fixed.However, when the block length is not fixed like this, it is impossible to supplement block synchronization using a conventional counter. , the block length information of the preceding block is not required to supplement the block synchronization of the subsequent block. This block length information can be inserted into the additional information section of the relevant block (1
If synchronization supplementation is not performed during playback, the length information on C is not required and there is no need to insert it into the block.
%Effects of the Invention The present invention (Friends) Coding errors can be greatly reduced by using the unused area within a block for coding error information of other blocks, which occurs in fixed-length controlled variable-length coding. Furthermore, the present invention has the advantage of being able to reduce the circuit scale compared to conventional variable-length coding (1) It can be used in digital VTRs, etc., and has a very large practical effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a main part of a digital signal processing device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a main part of a digital signal processing device according to a second embodiment of the present invention. The figure shows the constituent countries of the blocked data.

Claims (6)

[Claims] (1) Variable-length encoding means for variable-length encoding input data, encoding error extraction means for extracting encoding errors caused by this variable-length encoding means, and encoding the output of this encoding error extraction means. The method is characterized by comprising a coding error re-encoding means, and a re-blocking means for dividing the output of the variable length coding means and the output of the coding error re-encoding means into mutually different data blocks. Digital signal processing equipment. (2) In place of the encoding error re-encoding means, a parity generation addition means is provided for generating parity for error correction on the output of the variable length encoding means and adding it to the output of the variable length encoding means. 2. Digital signal processing according to claim 1, wherein the reblocking means divides the output of the parity generation addition means and the output of the parity generation addition means with respect to the output of the encoding error extraction means into mutually different data blocks. Device. (3) Blocking means for forming one block from a non-constant number of data, synchronization information insertion means for inserting synchronization information for block synchronization, and inserting length information of one block into the output of the blocking means. length information insertion means for
A digital signal processing device comprising: synchronization information supplementing means for supplementing synchronization information of a subsequent block using the synchronization information and the length information. (4) In place of the length information insertion means, additional information insertion means inserts additional information consisting of length information of at least one block into the output of the blocking means, and generates parity for error correction with respect to the additional information. additional information parity generation and insertion means for inserting into the output of the blocking means, and the synchronization information supplementing means includes additional information error correction means for correcting errors in the additional information using the parity; 4. The digital signal processing apparatus according to claim 3, wherein the synchronization information of a subsequent block is supplemented by using the length information of the additional information in which the error is corrected. (5) variable-length encoding means for variable-length encoding input data and controlling the data length of the variable-length encoded output for a plurality of input data to be equal to or less than a certain value; and an output of the variable-length encoding means empty information extraction means for obtaining the difference between the length and the value; encoding error extraction means for extracting the encoding error by the variable length encoding means; and encoding the output of the encoding error extraction means within the difference. and encoding error information insertion means for inserting the output of the encoding error re-encoding means into the output of the variable-length encoding means. Device. (6) A claim comprising parity generation and addition means for generating and adding parity for error correction to the output of the variable length encoding means, the output of the encoding error re-encoding means, and the output of the encoding error information insertion means. Item 5. Digital signal processing device according to item 5.