JPH03187519A - Programmable logic device - Google Patents

Abstract

PURPOSE:To prevent a chip size from being enlarged and to prevent a delay time from being prolonged between an input and an output by sharing a circuit constituting part common for flip-flop circuits in the plural flip-flop circuits. CONSTITUTION:A T type flip-flop circuit is constituted by operating transmission gates 4, 8, 12 and 13 according to the signal level of a T signal, and a D type flip-flop circuit is composed of constituting parts 4, 5, 7, 8 and 10-13. A JK type flip-flop circuit is constituted by adding a constituting part 21 to the D-type flip-flop circuit, and an RS type flip-flop circuit is composed of a constituting part 27. Thus, by sharing the common constituting part, the plural types of the flip-flop circuits are provided and can be made selectable. Thus, a programmable logic device can be obtained so that the delay time can not be prolonged between the input and output, and the chip size can not be enlarged as well.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable logic device incorporating a flip-flop circuit.

[Prior art and its problems] Flip-flop circuits include D type, JK type, T type, and R3 type.
There are several types of flip-flop circuits, but conventional programmable logic devices with built-in flip-flop circuits only have one type of flip-flop circuit built-in.

Therefore, if a user changes the circuit after purchasing such a programmable logic device, there is a problem that the purchased device may become unusable and wasted due to the different type of built-in flip-flop circuit. be.

Also, even if the above four types of flip-flop circuits are simply built in and a multiplexer is used to select them,
There are problems in that the delay time between input and output increases (and the chip size also increases).

The present invention was made in order to solve these problems, and it is a programmable logic device that is equipped with various types of flip-flop circuits, does not have a large delay time between input and output, and does not have a large chip size. The purpose is to provide.

[Means for Solving the Problem] The present invention is characterized in that it includes a plurality of types of flip-flop circuits that share a common circuit component and a circuit for selecting the type of the flip-flop circuit. do.

[Function] In a plurality of flip-flop circuits, the common circuit components are shared, so even if a plurality of flip-flop circuits are provided, the chip size does not become larger than 4, and the input This works to prevent the delay time from increasing between outputs.

[Embodiment] In FIG. 1 showing an embodiment of the programmable logic device of the present invention, a data input terminal 1 to which data is supplied has a low active transmission gate 2.3 and a high active transmission gate 4. It is connected to the input side of the NAND circuit 5 via.

An inverted reset signal input terminal 6 to which the inverted reset signal is supplied is connected to the input sides of the NAND circuit 5 and the NAND circuit 10. Further, the inverted set signal input terminal 9 to which the inverted set signal is supplied is connected to the input side of the NAND circuit 7 to which the output side of the NAND circuit 5 is connected, and to the input side of the NAND circuit 11 to which the output side of the NAND circuit 10 is connected. be done.

The output side of the NAND circuit 5 is connected to the input side of the NAND circuit 10 via a low active transmission gate 8. The output side of the NAND circuit 7 is connected to the NAND circuit via the low active transmission gate 12.
Connected to the input side of circuit 5. N A'N D circuit 11
The output side of is connected to the input side of the NAND circuit 10 via the high active transmission gate 13, to the input side of the high active transmission gate 4 via the high active transmission gate 14, and to the input side of the high active transmission gate 4 via the low active transmission gate 15. and are respectively connected to an inverted Q signal output terminal 16 which is an output terminal of this device. Moreover, the output side of the NAND circuit 10 is
It is connected to a Q signal output terminal 18 which is an output terminal of the present device via a low active transmitter 17, and is also connected to the input side of a NOR circuit 19 and an AND circuit 24.

The transmission gate 4.8.12.13 is turned on and off by the clock signal supplied to the clock signal input terminal 20.
When an H level clock signal is supplied to , transmission gates 8 and 12 are on, transmission gates 4 and 13 are off,
When an L level clock signal is supplied, transmission gates 4 and 13 are turned on, and transmission gates 8 and 12 are turned off. still,
When operating as a T-type flip-flop circuit, a T signal is supplied to the clock signal input terminal 20,
The transmission gate 4.8.12.13 operates according to the signal level of the T signal.

The above-mentioned components 4.5.7.8.10 to 13 constitute a D-type flip-flop circuit.

The JK type flip-flop circuit is constructed by adding a component 21 to the configuration of the above-described D type flip-flop circuit. That is, the output side of the NOR circuit 19 to which the J signal input terminal 22 is connected to the input side is connected to the NOR circuit 23, and the output side of the AND circuit 24 to which the K signal input terminal 25 is connected to the input side is connected to the NOR circuit 23. The output side of the NOR circuit 23 is connected to a high active transmission gate 26.

Further, the RS type flip-flop circuit is constituted by a component 27 having a known circuit configuration, and is added to the above-described circuit device. That is, the inverted set signal input terminal 9 is connected to the input side of the NAND circuit 28, and the inverted reset signal input terminal 6 is connected to the input side of the NAND circuit 29. The output side of the OR circuit 30 to which the S signal input terminal 31 and the G signal input terminal 32 are connected is connected to the NAND circuit 28, and the output side of the OR circuit 34 to which the R signal input terminal 33 and the G signal input terminal 32 are connected. is connected to the NAND circuit 29. The output sides of the NAND circuits 28 and 29 are fed back to the input side of one of the NAND circuits. NAN
The output side of the D circuit 28 is connected to the Q signal output terminal 18 via a high active transmission gate 35, and the output side of the NAND circuit 29 is connected to the inverted Q signal output terminal 16 via a high active transmission gate 36. connected to.

Among the memories 37 to 39 for selecting one of the above four types of flip-flop circuits, the memory 37 is
Transmission gate 2 via sense amplifier 40
The memory 38 is connected to the enable terminals of the transmission gates 3 and 14 via the sense amplifier 41, and the memory 39 is connected to the enable terminals of the transmission gates 15.
17.35.36 is connected to the enable terminal.

Each memory 37 to 39 includes fuse, EPROM, E
Various types of memory elements such as EPROM can be used, and when these memories are programmed, the sense amplifiers 40 to 42 send out H level signals, and when they are not programmed, they send out L level signals. do. Therefore, when an L level signal is sent from the sense amplifier 40, the transmission gate 2 is turned on and the transmission gate 26 is turned off.On the other hand, when an H level signal is sent, the transmission gate 2 is turned on and the transmission gate 26 is turned off. 2 is turned off, and the transmission gate 26 is turned on. Further, when an L level signal is sent from the sense amplifier 41, the transmission gate 3 is turned on, the transmission gate 14 is turned off, and, on the other hand,
When an H level signal is sent, the transmission gate 3 is turned off and the transmission gate 14 is turned on. Further, when an L level signal is sent from the sense amplifier 42, the transmission gates 15.17 are turned on, the transmission gates 35.36 are turned off, and the D type,
An output signal from one of the JK type and T type flip-flop circuits is sent to output terminals 16 and 18. On the other hand, when an H level signal is sent from the sense amplifier 42, transmission gates 15 and 17 are turned off, transmission gates 35 and 36 are turned on, and R
The output signal of the S-type free-flop circuit is delivered to the output terminal 16.18.

The operation of the programmable logic device configured in this way will be described below.

The memories 37 to 39 are programmed to select which of the four types of flip-flop circuits to select.

Note that these memories 37 to 39 may contain EPROM or E
If a memory element consisting of an EP ROM is used, it is possible to once select one of the flip-flop circuits and then select it again even if a change occurs.

In these memories, if none of the memories 37 to 39 are programmed, all the sense amplifiers 40 to 42 send out L level signals.
Transmission gate 2.3.15.17 is on, transmission gate 14.26.35.36
is turned off, and the circuit device operates as a D-type flip-flop circuit. Therefore, data input terminal 1
The data supplied to the inverted Q signal output terminal 16 and the Q signal output terminal 18 are sent out in accordance with the clock signal supplied to the clock signal input terminal 20.

Also, if only the memory 37 is programmed,
Since the sense amplifier 40 sends out an H level signal, the transmission gate 2 is turned off and the transmission gate 26 is turned on. The other transmission gates are open and closed in the same manner as in the above case, so the present circuit device operates as a JK type flip-flop circuit. Therefore, the data supplied to the J signal input terminal 22 and the signal input terminal 25 is sent out from the inverted Q signal output terminal 16 and the Q signal output terminal 18 in accordance with the clock signal supplied to the reverse signal input terminal 20. Ru.

Also, when the memory 38 is programmed and the memory 39 is not programmed, the sense amplifier 41 outputs an H signal.
The transmission gate 3 is in the off state, the transmission gate 14 is in the on state, the transmission gates 15 and 17 are in the on state, and the transmission gate 1- 35 and 36 are in the off state, and the circuit device operates as a T-type free-y bflop circuit. Therefore, the clock signal input terminal 20
According to the T signal supplied to the inverted Q signal output terminal 16 and the Q signal output terminal 18, signals are sent out.

In this case, it does not matter whether the memory 37 is programmed or not.

Furthermore, when the memory 39 is programmed, the sense amplifier 42 sends out an H level signal, so the transmission gates 15 and 17 are off, and the transmission gates 35 and 36 are on. Therefore, in this case, the present circuit device operates as an RS type flip-flop circuit. Therefore, S signal input terminal 3
The data supplied to the 1 and R signal input terminals 33 are sent out from the inverted Q signal output terminal 16 and the Q signal output terminal I8 in accordance with the signal supplied to the G signal input terminal 32. still,
In this case, memories 37 and 38 may be programmed or not.

Further, signal input terminals for unused flip-flop circuits are maintained at either the Vcc or GND potential.

In this way, this circuit device has four types of flip-flop circuits, so if changes occur after purchasing the programmable logic device and you end up using a different flip-flop circuit than originally planned, Even a suitable flip-flop circuit can be selected.

In addition, since each flip-flop circuit shares commonly used circuit parts, the chip size is smaller than simply providing four types of flip-flop circuits, and increases in delay time are prevented. be able to.

Furthermore, since this circuit device is provided with an inverted reset signal input terminal 6 and an inverted set signal input terminal 9, the flip-flop circuit can be initialized, and the desired output can be obtained from the first pulse of the supplied clock signal. I can get a signal.

Furthermore, as described above, by using the memories 37 to 39 as selection circuits for each flip-flop circuit, the designer does not need to always know the signal level supplied to the enable terminal of the transmission gate 2, etc. By determining the memory contents at the time of final design, it is possible to automatically set the signal level to be supplied to the enable terminal of the transmission gate in order to obtain the desired type of flip-flop circuit, which is convenient for circuit design. be.

Further, the selection circuit of each flip-flop circuit is not limited to a memory as in this embodiment, but may be an appropriate selection switch.

[Effects of the Invention] As detailed above, according to the present invention, common circuit components are shared so that multiple types of flip-flop circuits are provided and these can be selected. It is possible to provide a programmable logic device in which flip-flop circuits can be selected, the delay time between input and output is not large, and the chip size is not large.

[Brief explanation of drawings]

Figure m1 is a logic circuit diagram showing the configuration of one embodiment of the present programmable logic device. l...Data input terminal, 2.3.14.15...Transmission gate, 16...Inverted Q signal output terminal, 17...Transmission gate, l8...Q signal output terminal, 26...・Transmission gate, 35 and 36・
...Trans Mitsushiran Gate, 37 to 39...
memory.

Claims (3)

[Claims] (1) A programmable logic device comprising a plurality of types of flip-flop circuits that share a common circuit component and a circuit for selecting the type of the flip-flop circuits. 2. The programmable logic device according to claim 1, comprising: (2) D, JK, T, RS type flip-flop circuits. (3) The programmable logic device according to claim 1 or 2, wherein the flip-flop circuit is provided with a signal input terminal for initializing the flip-flop circuit.