JPH03187263A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent writing failure and read failure due to leakage current by providing source lines of memory cells so as to run perpendicularly to bit lines and by selecting transmission source lines as well as bit lines and word lines in accordance with selection bits. CONSTITUTION:Selection of bit lines 51a-54a, word lines 21-24, and source lines 51b-53b in accordance with selection bits allows selection of memory transistors M11-M41, M12-M42, M13-M43, and M14-M44 equivalent to selection bits. At this time memory transistors of nonselection bits reject potential differences in their sources and drains, so that leakage current can be inhibited from flowing through the source-drains of memory transistors of nonselection bits. This process can prevent writing failure and read failure due to leakage current.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) This invention relates to a semiconductor memory device, particularly a semiconductor ROM (
(Read Only Memory).

(Prior Art) FIG. 3 shows a conventional semiconductor memory formed on a substrate, such as an EPROM (Erasable and Pro
FIG. 4 is a plan view of the memory cell array of the EPROM of FIG. 3 in the form of a circuit diagram. Figures 3 and 4
In the figure, (1) is an isolation oxide film, (21), (22)
... are formed in rows on a semiconductor substrate with an insulating film interposed therebetween, and are memory transistors (Mll) to (Purchase 41), (Mll) that constitute memory cells arranged in the corresponding rows.
]2) ~(M42), (M13) ~(M4:l),
Each control gate (I) of (1114) to (M44)
IG) ~ (41G), (12G) ~ (42G),
(1:lG) ~ (43G), (14G) ~ (44
G) , word line connected to (3)
, (3)... are floating gates of memory transistors, (4a), (4a)... are train contacts for connecting to the train of each memory transistor, (4b), (4b)...・ is the source of the memory transistor on the same column (IIS) ~ (143),
(21S) ~ (24S) , (:1IS)
~(34S) , (41S) ~(44S)
Source contact l-1 for commonly connecting the
(51a), (52a)... are Al□ wiring bit lines arranged in rows on the semiconductor substrate with an insulating film interposed therebetween, and L train contacts (4a) are arranged in each row.
The train of each memory transistor (IID) ~ (
+4D), (21D) ~ (24D), (3]D
) to (34D) and (41D) to (44D), respectively. (5b) is the tool l of the memory cell array.
- Lines (21), (22), etc. are connected to the source contacts (4b
), the semiconductor layer is connected to the source region of each memory transistor via diffusion chips formed in rows on the board.

In the 40th section in which the memory cell array of the EPROM of 3.A is arranged in the form of an FIj circuit diagram, a case will be described in which, for example, a memory transistor (M: 12) is written.
A voltage Vnp is applied to the bit line (53a) connected to
(For example, in the case of a 1M bit EPROM, 7 to 9V)
is applied, and the gate (
A pulse voltage Vpp of a predetermined width tp (approximately 12.5 V in the case of a 1 Mbit EFROM) is applied to the word line (22) connected to the memory transistor (M32G) to write data into the memory transistor (M32). In this case, the source (IIS) ~ (+43) of the memory transistor in each column,
(21S) ~ (24S) , (:1IS) ~ (34
S), (41S) to (44s) are source lines (5
b) are commonly connected to ground.

Also, unselected bit lines (51a), (52a), (
54aJ"... are oven or grounded, and unselected word lines (21), (23L (24)...
・is grounded.

Pulse @1I to the gate of memory transistor (M32)
Ip pulse'r! .
32) is in a written state.

When reading, a voltage of about IV is applied to the bit line (5:la). Apply a voltage V,c of approximately 5V to the word line (22), and connect the reference bit line (always in a blank state) and the above hit line (5) to the word line (22).
: Compare the current values flowing through Ia). and,
If the current flowing through the bit line (53a) is smaller than the current flowing through the line to reference pin 1, it is determined to be a block state (data or written state;) at t1, and the current flows from pin 1 to line (53a). 'If the current is DC or about the same as the reference bit line, it is determined to be a flank state.

[Invention or problem to be solved]

Since the conventional EPROM memory cell array is configured as described above, the memory transistor (M
Other memory transistors (M31), (M:+3), (M3) in the same column whose drains are connected to the source (320) of
'l)...and other memory transistors in the same row whose control gates are connected to the word line (22) to which the control gate (32G) of the memory transistor (M32) of the l- selection bit is connected. (old 2),
For (M22), (M42)..., -) is included. When P and Vpp are read, V. , VCC, respectively.

In recent years, as memory cell arrays have become increasingly finer, it has become difficult to adjust or control the initial rA voltage Vtho and the source-to-train breakdown voltage BV,t due to variations in the gate length of each memory transistor. The voltage applied to the train causes the memory transistors (M31), (M33), (M
34)... may also have a considerable amount of source current flowing through its source-train.

Figure 6 shows the memory transistors of unselected bits (10).
FIG. 2 is a diagram showing the overall state of each part. In the figure, CI is the capacitance between the control gate (12) and the floating gate (13), C2 is the capacitance between the floating gate -1-(+3) and the channel, and C3 is the floating gate (13). and train (6). As is clear from the figure, the control gate (
12) is grounded to the word line (2) by 8 (va = O), and the source region (7)
is also grounded via the source line (5b).

The potential of the floating gate (13) is the bit line (
5a) applied to the train region (6) via
It rises due to DP, and the voltage vFG has a value expressed by the following equation.

Therefore, even if the breakdown voltage between the source and the train is equal to or higher than VD, leakage current may flow. Further, as the memory array cells become smaller, the thickness of the insulating film layer formed on the semiconductor substrate becomes thinner, so the capacitance C2 becomes relatively large, and the leakage current also tends to increase.

As described above, when a current flows through the memory transistor of an unselected bit, the train voltage VDP decreases during writing, resulting in a decrease in writing speed and depth. Even if the power supply capacity is large and voltage drop does not occur, for example, in a 1M bit level EPROM, hundreds to dozens of memory transistors are connected to the same bit line, so leakage from each memory transistor occurs. Even if the current is at a level of several gA, a total current of several mA will flow. Therefore, it is necessary to increase the capacitance of the select transistor, which goes against the trend of miniaturization. Also, when a leak current flows to the memory transistor of the unselected bit during reading, even if the memory transistor of the selected bit is set so that no current flows in the programmed state, the judgment will be made because of the current flowing to the unselected bit. may be mistakenly read as a blank state.

The purpose of this invention is to solve the above-mentioned drawbacks of conventional semiconductor memories.
M (Electrica eyes Erasable a
ndProgrammable Read 0nly M
An object of the present invention is to obtain a semiconductor memory device including a mask ROM or a mask ROM.

(Means for Solving the Problems) A semiconductor memory device according to the present invention includes a plurality of memory cells formed in a matrix in a plurality of rows and a plurality of columns on a semiconductor substrate, each including a memory transistor, and a plurality of memory cells on the semiconductor substrate. A plurality of bit lines are formed in columns with an insulating film interposed therebetween, and are connected to trains of memory transistors arranged in corresponding columns, and are formed in rows on the semiconductor substrate with an insulating film interposed therebetween. a plurality of word lines to which control electrodes of memory transistors arranged in corresponding rows are connected; and sources of memory transistors arranged perpendicularly to the bit lines and each arranged in adjacent rows. and a source line to which a control potential for selection is applied when selecting a bit.

[Function] In the semiconductor memory device of the present invention, the memory transistor corresponding to the selected bit is selected by selecting the bit line, word line, and source line corresponding to the selected bit. At this time, since no potential difference occurs between the source and the train of the memory transistor of the unselected bit, leakage current can be suppressed from flowing between the source and train of the memory transistor of the unselected bit. Preventing defects and read failures.

(Embodiment) The semiconductor memory device of the present invention will be described below with reference to FIGS. 1 and 2.
This will be explained with reference to the figures. FIG. 1 is a plan view of a memory cell array of a semiconductor memory device of the present invention formed on a substrate, and FIG. 2 is a diagram showing the memory cell array of FIG. 1 in the form of a circuit diagram. In Figures 1 and 2, (
1) is an isolation oxide film, (21), (22), etc. are formed in rows on a semiconductor substrate with an insulating film interposed therebetween, and memory transistors forming memory cells arranged in the corresponding rows. (Mll) ~ (M41) , (Ml2) ~ (M4
2), (Ml:I)~(M43), (Ml4)~(
M44) each control gate (IIG) ~ (41G
) , (12G) ~ (42G) , (13G) −
(43G), (14G)~(44G),...
Word line connected to (3), (3)...
is the floating gate of the memory transistor, (4a
), (4a)... are train contacts for connecting to the train of each memory transistor, (4b),
(4b)... are the sources of memory transistors (IIS) ~ (41S), (12S) - (
42S), (13S)~(433), (14S)~
a source contact for connecting (443) in common;
(51a), (52a)... are aluminum wiring bit lines arranged in a row on a semiconductor substrate with an insulating film interposed therebetween, and in each row, the train contact (4a)
The train of each memory transistor (110) to (
14D), (210)~(24D), (31D)~
(34D) and (41D) to (44D). (51b), (S2b)... are formed on the semiconductor substrate via an insulating film, and the word lines (21
), (22), etc. are conductor layers constituting the two-layer aluminum wiring source line arranged in parallel, and perpendicular to the bit lines (51a), (52a), and so on. The memory transistors are arranged on a common source region of each memory transistor arranged in an adjacent row. These conductor layers (51
b), (52b) . . . are the source contacts (4b), (4b) .
It is connected via...

In the circuit diagram of the memory cell array shown in FIG. 2, for example, when writing to the memory transistor (M:12), each memory transistor train (31D) to (:14D) in the column that includes the memory transistor (0132) is
)... is connected to the bit line (53a), for example, a voltage VDP of 7 to 9V is applied to the control gate (12G) of each memory transistor in the row that also includes the memory transistor (M:12). ~(42G)
For example, a pulse voltage VPP of approximately 12.5 V is applied to the word line (22) connected to Transistor (M12
) ~ (M42), (old 3) ~ (purchase 43) sources (
The source line (52b) to which 12S) to (42S) and (135) to (43S) are connected is grounded. Other bit lines, i.e. unselected bit lines (51a
), (52a), (S4a)... and unselected source lines (51b), (S:lb)...
Either apply the voltage VDP to all of them, or open the unselected source lines and ground or open the unselected bit lines.

Also, unselected word lines (21), (23), (2
4) All... are grounded.

In the write state shown in J-, the source-train of the adjacent memory transistor (M33) which is in the same column as the selected memory 1 to transistor (M32) and whose source is connected to the common source line (52b) In between are the above 7~
A voltage of 9V DP is applied to the bit lines (51a), (52a), (54a) and source lines (51b), (5:Ib) to which the sources and trains of other memory transistors are connected. Since the same potential is applied to the memory transistors (M32) and (
No potential difference occurs between the source and train of memory transistors other than 133). Therefore, even if a leakage current flows, it is due to the memory transistor (M3:
There is only the leakage current of l), which is extremely small in quantity, and there is no concern that it will adversely affect the write operation.

Similarly, when reading the memory transistor (M32), the train (32D) of the memory transistor (M:12)
For example, approximately l
A voltage VD of v is applied, and the control gate 1- (32
G) is connected to the word line (22), for example, about 5V.
voltage VCC is applied, and the source line (52b) to which the source (32S) is connected is grounded. Here, the reference bit line (always in a blank state) and the current flowing through the bit line (53a) are compared, and as in the conventional case, the current flowing through the bit line (53a) is smaller than the current flowing through the reference line. If so, it is determined to be a program state (a state in which data has been written), and if the current flowing through the bit line (53a) is about the same as the current flowing through the reference line, it is determined to be a blank state.

Also during this read, the unselected bit lines (51a) and (52
a), (54a) and unselected source line (51b)
, (53b), apply voltage VD to all, or
Alternatively, the unselected source line is set as an oven, and the unselected bit line is grounded or set as an oven. In addition, all unselected word lines (21), (23), etc. are grounded. Therefore, in this state, the read memory transistor (M32)
The other transistors in which a potential difference occurs between the source and the train are in the same column as the read memory transistor (M32), and are connected to the source or the common source line (52b).
) is connected only to the memory transistor (133), so even if a leakage current were to flow, the amount would be extremely small.
There is no possibility that a reading error will occur.

Although the present invention has been explained with respect to the EFROM of the illustrated embodiment, even if the present invention is applied to a normal NOR type mask ROM or a NOR type EEPROM, a potential difference occurs between the source and the train of the unselected memory transistor when the memory transistor is selected. Since the number of is reduced, it is possible to obtain the same effect as described above in that the leakage current at the time of selection can be significantly reduced.

(Effects of the Invention) As described below, according to the present invention, the source line of the RO- memory cell is provided perpendicular to the bit line,
The configuration is such that the source line is selected in the same way as the bit line and word line in response to the selection bit.
When a predetermined memory transistor is selected, substantially no voltage is applied between the source and train of the memory transistor of the unselected bit, and therefore, it is assumed that there is substantially no leakage current of the memory transistor of the unselected bit. write failure due to leakage current.
The occurrence of reading failures can be completely prevented.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view showing the entire configuration of a ROM memory cell array according to an embodiment of the present invention formed on a substrate, and FIG. 2 is a circuit diagram of the RO-memory cell array configuration of FIG. 1. Figure 3 shows a conventional ROIil formed on substrate-E.
4 is a top view showing the structure of the memory cell array; FIG. 4 is a diagram showing the entire circuit diagram of the ROM memory cell array shown in FIG. 3;
FIG. 5 is a diagram generally showing the write characteristics of a memory transistor in an EFROM, and FIG. 6 is a diagram explaining the interelectrode capacitance of a memory transistor in an ERROM and its effect. (21) ~(24)---word line, (51a
) ~(54a)...bit line, (51b)~
(53b)... Source line, (old l) ~ (M41
), (12)~(M42), (Ml:l)~
(M43) (Ml4) ~ (M44)...Memory transistor, (IIG) ~ (41G), (12G)
~(42G) , (1:lG) ~(43G) , (
14G)~(44G)...Control electrode, (IIS)~
(41S), (12S)~(42S), (
13S) ~ (43S) , (14S) ~ (4flS
) ... Source, (110) ~ (41D)
, (120) ~ (42D) , (+3D) ~
(43D), (14D) ~ (44D)...
・Train. Agent Masu Oiwa%3 Enko4 Figure 5b: ~/=1 line 5th 61!1 3 70-body ink °lf'J

Claims (1)

[Claims] (1) A plurality of memory cells formed in a matrix in multiple rows and multiple columns on a semiconductor substrate, each including a memory transistor, and a plurality of memory cells formed in a row on the semiconductor substrate with an insulating film interposed therebetween, and corresponding to each other. a plurality of bit lines to which drains of memory transistors arranged in columns are connected, and memory transistors formed in rows on the semiconductor substrate with an insulating film interposed therebetween, and control memory transistors arranged in corresponding rows. A plurality of word lines to which electrodes are connected are arranged orthogonally to the bit lines, each of which is connected to the sources of memory transistors arranged in adjacent rows, and when a bit is selected, a control potential for selection is applied. A semiconductor memory device comprising a source line to which voltage is applied.