JPH03185983A - Video recording and reproducing device - Google Patents

Abstract

PURPOSE:To ensure the reproduction of a control signal and to obtain a reproduced video image with high picture quality stable even at special reproduction by recording the control signal onto plural tracks of a recording medium. CONSTITUTION:A control signal from a control memory 30 is fed to a contact (b) of a switch 36 and the switch 36 is switched so as to locate the same control signal to plural tracks by a timing signal 24d from a clock generating circuit 22 and the control signal is recorded to plural recording areas of one field of the recording medium. Thus, even at the special reproduction such as search or slow reproduction, the control signal is surely reproduced and a reproduction video image with stable and excellent quality is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video recording and reproducing device, and more specifically,
The well-known MUSE (Multiple 5
ub-Nyquist Sampling Encod
Compressed video signal (hereinafter referred to as MU
This is called the SE signal. ) related to a recording/reproducing device.

[Prior Art] FIG. 4 shows a transmission signal for one frame of a MUSE signal. The transmission signal for the king frame of the MUSE signal consists of 1125 lines, and is transmitted sequentially for each line. Fourth
In the figure, Y is a luminance signal obtained by analogizing sample values, C is a color signal obtained by analogizing sample values, A is an audio signal converted from a digitized audio signal into a ternary signal, and F
P/VIT is a signal containing information such as transmission path equalization (VIT
) and frame pulse (FP), GU is a guard space, CON is a control signal to be described later, BL is empty data, and CP is a symbol corresponding to clamp level information. The numerical values shown in FIG. 4 indicate the number of data in the digital domain before converting the transmission signal to analog.

The control signal CON has 32 bits per field. Since this is very important when decoding on the receiving side, a total of 64 bits (Hamming code) with 32 bits of parity added are sent three times in consideration of errors during transmission. For example, in the first field, 559 to 5
12 to 106 samples of 63 lines, 3 shipments. Movement information is expressed by three bits consisting of the 16th, 17th, and 18th bits of the control signal, where O is normal,
l is a completely still image, 2 is a semi-still image, 3 is a scene change,
4 to 7 indicate the degree of movement. The 19th bit is a signal for controlling the reception mode, and 0 indicates the standard method and 1 indicates the non-standard method. The 20th bit is AM/FM, and l is A.
M indicates no emphasis.

For other contents of the control signal and detailed structure of other symbols, please refer to the NH issue published on November 25, 1986.
It is explained in detail in Chapter 3 of ``High Vision Technology'' edited by K Broadcasting Technology Research Institute.

When recording a MUSE signal as shown in FIG. 4 on a magnetic tape using a helical scan VTR, conventionally, for example, as shown in FIG. 5, a pair of two-channel heads IOA, 10B, 12A, and 12B is arranged 180 degrees opposite to the rotating drum 14, and the rotating drum 14
was rotated at 3.60 rpm to record on the magnetic tape 16.

In this case, one field is recorded on four tracks,
A track pattern as shown in FIG. 6 is formatted.

Since the control signal CON exists for only five lines in one field, it is only locally included in one track out of four tracks constituting one field on the magnetic tape.

There is no problem when reproducing the recorded signal of the track pattern shown in Figure 6 at normal speed (same speed as when recording), but for example, when performing triple speed reproduction, the diagonal lines in Figure 6 Only a portion of the signal is reproduced, and therefore the reproduction rate of the control signal COH decreases rapidly. In other words, the number of fields in which the control signal is not reproduced increases.

In other words, information related to the decoding method, such as the 19th and 20th bits of the control signal, cannot be reproduced, and the image quality of even the search image is extremely degraded.

Furthermore, since slow playback generally requires high image quality, it is a problem that the motion information of the control signal CON is lost.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a video recording and reproducing apparatus that can reproduce control signals even during special reproduction such as search and slow reproduction.

[Means for Solving the Problems] A video recording and reproducing device according to the present invention records a signal including a compressed video signal and a control signal for restoration on a recording medium, and restores and reproduces the video according to the control signal. The present invention is a video recording and reproducing apparatus, and is characterized in that the control signal is recorded at a plurality of locations in a predetermined recording area of one field of a recording medium.

[Function] With the above means, the control signal can be reliably reproduced even during special reproduction. Therefore, it is possible to obtain stable and high-quality reproduced video even during special playback.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of a recording system according to an embodiment of the present invention. The MUSE signal is input to the input terminal 20, and the synchronization signal 5YNC is input to the input terminal 22.

The clock generation circuit 24 generates clock signals 24a, 24b, 24c of a predetermined frequency according to the synchronization signal from the input terminal 22.
, 24d. A/D converter 26 uses clock 24
a (16,2MHz), MU of input terminal 20
The SE signal is converted into an 8-bit digital signal of the format shown in FIG. The output of the A/D converter 26 is an unnecessary HD
Except for the period, it is written to the buffer memory 28. The write address for the buffer memory 28 is generated by the address generation circuit 32 in response to the clock 24c of the clock generation circuit 24. Further, the control signal CON is written into the control memory 30 according to the clock 24b from the clock generation circuit 24.

Reading from buffer memory 28 and control memory 30 is performed as follows.

Oscillator 34 generates a clock with a frequency corresponding to the recording bit rate, and address generation circuit 32 generates a read address for buffer memory 28 in accordance with the output clock of oscillator 34. Two tracks of data are read from the buffer memory 28 every half rotation of the drum and output to the a contact of the switch 36. The data for these two tracks is not read out in line order from the first line, but in shuffled form in consideration of special playback, but the format of shuffling is not directly related to the present invention. Therefore, the explanation will be omitted.

A control signal from the control memory 30 is supplied to the b contact of the switch 36. The switch 36 is switched by the timing signal 24d from the clock generation circuit 22 so that the same control signal is placed at a plurality of locations on each track, as shown in FIG. That is, in the example shown in FIG. 3, three identical control signals are inserted into one track, and the same control signal is recorded at 12 locations in one field.

In this way, the immediate SE data in which control signals are inserted at multiple locations per track by the switch 36 is
Error detection and correction codes (ECC) are added by FCC encoders 38A and 38B, and 5YNC-ID addition circuit 40
5YNC code and ID code are added by A and 40B, modulated by modulation circuits 42A and 42B, and then sent to amplifier 44.
A and 44B are amplified, and channels A and B are respectively amplified.
The signal is applied to the magnetic head and recorded on the magnetic tape in the format shown in FIG.

FIG. 2 shows a tank bottom block diagram of a regeneration system according to an embodiment of the present invention. The output of the magnetic head of channel A is input to the input terminal 46A, and the output of the magnetic head of channel B is input to the input terminal 46B.

The respective signals are amplified by reproduction amplifiers 48A and 48B, and digitally demodulated by demodulation circuits 50A and 50B. This demodulation process is performed using a clock generated by a PLL (not shown) in synchronization with a clock component including jitter included in the reproduced signal.

The outputs of the demodulation circuits 50A and 50B are first-in/first-out (FI
FO) are written into the memories 52A and 52B, but read out using a stable constant frequency clock from the oscillator 53. Thereby, a digital signal with jitter removed can be obtained. FIFO memory 52A, 52B
The signals read from the ECC decoders 54A, 54
B, where code errors occurring in the magnetic recording/reproducing system are corrected. The ECC decoders 54A, 54B output an error-corrected data signal 54a and an error detection signal 54b indicating the presence of an uncorrectable error.

Of the outputs of the ECC decoders 54A and 54B, the MUSE signal excluding the control signal is written into the buffer memory 56. A plurality of control signals reproduced from one field are written into the control memory 58 as error-free control signals (64 bits) by the error detection signal 54b.

The data in the buffer memory 56 is read out according to the address signal generated by the address generation circuit 60 using the clock of the oscillator 53 according to the bit rate of the MUSE signal, and the data of the two channels is read out according to the format shown in FIG. 62 is supplied to the a contact point.

The control signal is similarly read out from the control memory 58 and supplied to the b contact of the switch 62. The switch 62 is switched by the output of the timing generation circuit 64 so that the control signal is inserted at a position corresponding to the format shown in FIG.

The output of the switch 62 is converted to an analog signal by the D/A converter 66, and becomes the original analog MIJSE signal.
It is output to the output terminal 68.

In this embodiment, since the control signal data is inserted in three places on each track, when performing a triple search, the control signal data can be reliably reproduced at least once in one field, and therefore the desired You can obtain playback video with a picture quality of . Of course, in order to support faster search or slow playback, the number of control signals inserted per track may be increased. Control signal data is 64 bits (including parity).
8 symbols), which is extremely small, so the increase in redundancy can be ignored.

Although the case of a digital VTR has been described, it is of course applicable to an analog VTR as well. Although a buffer memory for data and a memory for control signals are provided separately, it goes without saying that one memory can be shared by address control.

Moreover, although the case of the high-definition system has been described as an example, the present invention can be applied to general video signals that transmit information for video restoration together with video information, and is not limited to the high-definition system.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, control signals can be reliably reproduced even during special playback such as search and slow playback, and stable and high-quality playback images can be obtained. Now you can get it.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a recording system according to an embodiment of the present invention.
Fig. 2 is a block diagram of the playback system, Fig. 3 is a track pattern diagram according to this embodiment, Fig. 4 is the format of the MUSE signal, Fig. 5 is a schematic block diagram of the drum section, and Fig. 6 is a block diagram of the playback system.
The figure shows a conventional track pattern. 24: Clock generation circuit 28, 56: Buffer memory 30.58: Control memory 32゜60 Near address generation circuit 34゜53: Oscillator control control 10A IOB 12A 12B 10A 10B 12A I2B 0A

Claims (1)

[Claims] A video recording and reproducing device that records a signal including a compressed video signal and a control signal for restoration on a recording medium, and restores and plays back the video according to the control signal,
A video recording and reproducing apparatus characterized in that the control signal is recorded at a plurality of locations in a predetermined recording area of one field of a recording medium.