JPH03185490A - Tone display system and liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain a multilevel display without reducing display brightness and also without deteriorating the quality of the display even in the case that a display area for a half tone display is enlarged by using a system for thinning out frames and a system for modulating a pulse width jointly. CONSTITUTION:A data 15 for thinning out the frames is generated in accordance with a lower display data 14, and a control for modulating the pulse width is performed based on the thinning out data 15 and an upper display data 13. Then, the data of two bits which are transferred to a display with one dot is rearranged with reference to the dots in adjacent X directions and Y directions by a phase inversion circuit 9. By rearranging the data, the phase of an impressed pulse is inverted and also the noise caused by a rise and an fall counterbalances each other, the reduction of the display brightness caused by the enlargement of the half tone display area is eliminated. And also, the processing of thinning out the frames is performed by a frame thinning out circuit 4 in an oblique line dot pattern state. Thus, a counterbalancing effect by a phase inversion is effectively used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device, and particularly to a liquid crystal display device capable of displaying gradations.

[Conventional technology] What is the gradation display method used in conventional liquid crystal display devices?

As the first method, Hitachi HD66840 LVI
There is a frame thinning method as described in the C application note.
In the frame thinning method, which is the first pulse width modulation method as described in Japanese Patent No. 9393, one period is m frames for displaying one dot on the liquid crystal, and on-display is performed for n frames during that period. This method visually realizes gradation display by performing off-display in the remaining (m−n) frames. The value n/m obtained by dividing this value of n by m is called the thinning rate.When this value is O, the 1 display brightness level is 0%, and when it is 1, the 1 display brightness level is 10%.
It becomes 0%.

The frame thinning method will be explained using FIGS. 2 to 4. FIG. 2 is a block diagram of a liquid crystal display system that performs 8-gradation display using 3-bit display data, FIG. 3 is a block diagram of a frame thinning circuit, and FIG. 4 is a diagram showing an example of frame thinning data. It is.

In FIG. 2, the 3-bit display data 14 is:

The frame thinning circuit 4 shown in FIG. 3 converts the data into frame thinning data FD15. According to this FD 15, a liquid crystal display pulse Poff (pulse at OFF level for one horizontal period) or Pan (pulse at ON level for one horizontal period) is output from the XH open circuit 2 to the liquid crystal panel 1.

The frame thinning circuit 4 shown in FIG.
Select according to bit display data 14 and output as FD15. Each of the thinning circuits 25 to 32 generates thinning data according to a thinning rate of 1 using a first line clock 16, a line clock 1f, and a data latch clock 19. In the Hitachi layer HD66840 LVIC, in order to prevent flickering on one screen of the liquid crystal panel, all the dots that make up the liquid crystal panel l are not thinned out at the same timing, but a method is used in which n lines out of m lines are thinned out, with m horizontal lines as one unit. The first line clock 16 and the line clock 17 are used to generate thinned-out data.

Figure 4 shows the thinning data of 1 Hitachi HD66840 LVIC with a thinning rate of 415. The shaded area indicates the display is on. At the thinning rate of 415, 5 horizontal lines are taken as 1 unit, and 4 horizontal lines are set to be display on. , gradation display is achieved by shifting display on and display off for each frame.

Next, the second method, the pulse width modulation method, will be explained using FIGS. 5 and 6.

FIG. 5 shows an example of the configuration of a liquid crystal display device that displays three gray levels using the pulse width of a voltage pulse applied to the liquid crystal during one horizontal period. One of the two types of display information XA and XB for displaying one dot on the liquid crystal display in one horizontal period is selected by the data select signal 21 in the data selector 12, and the selected data becomes one type of data XD. xl [is supplied to the dynamic circuit 2. The X waste circuit 2 takes in data XD from the data selector 12 using the data latch clock 19. This taking in is repeated, and display data for one line is taken in. Thereafter, the signal #X1. of the liquid crystal panel 1 is activated by the pulse clock 18. X2
．． ..., outputs a liquid crystal application pulse to Xi. The pulse clock 18 is a clock that equally divides the line clock 17 for each horizontal period into two. The Y vertical movement circuit 3 takes in the first line clock 16 using the line clock 17, and
1 is set to "high", and then "high" is shifted from Y2 to Yj according to the line clock 17. Pf! The i-product panel 1 is a matrix-type panel consisting of i rows and j columns, and
Liquid crystal application pulses Xi, X2 .
..., Xi is the output Yl of the Y drive circuit 3, ..., Yj
It is applied to the liquid crystal cell of the line that is "high" and displayed.

FIG. 6 is a diagram showing liquid crystal application pulses output from the X@ dynamic open circuit 2. During one horizontal period, one type of display data XD is selected from two types of display data XA and XB from the data selector 12 and sent to the X rotation circuit 2 every 1/2 horizontal period, and the data XD One of the four types of pulses from pulse 1 to pulse 4 is selected and output from the X drive circuit 2.

Figure 7 shows the display data XD and Xll! 11 shows the correspondence of drive pulses output from stepping.

In FIG. 7, the display data is (XA, XB) = (0
,O), X#! The liquid crystal application pulse outputted from the dynamic circuit 2 becomes pulse 1, and 1 display becomes OFF display. (XA
, XB)=(1,1), the pulse applied to the liquid crystal becomes pulse 4, and the 5 display becomes an on display. Also, (XA, XB)
The liquid crystal application pulses of = (0,1) and (1°0) are respectively pulse 2. Pulse 3 and 1 display are both halftone displays of brightness between off and on. The display brightness (transmittance) of a liquid crystal depends on the effective value of the voltage applied to the liquid crystal. Since the pulse clock 18 is obtained by equally dividing the line clock 17 into two, the "H" periods of pulses 2 and 3 are equal, and the effective amplitudes of pulses 2 and 3 are equal. Therefore, the liquid crystal display due to pulses 2 and 3 The display brightness of the display is equal,
As a result, the brightness is intermediate between the off display and the on display, and 3
Gradation display becomes possible.

Therefore, the liquid crystal display device of FIG. 5 has display data XA,
By changing the effective value of the voltage applied to the liquid crystal panel 1 by combining B, it is possible to realize gradation display.

[Problems to be Solved by the Invention] In the frame thinning method of the prior art, when the thinning cycle, that is, the value of m, is increased, flickering and display flow occur, which makes it possible to visually see the thinning timing, and the display quality of gradation display deteriorates. is decreasing.

For this reason, it is practical #! The number 1 is around 10#,
For example, multi-gradation display such as 16 gradations and 32 gradations cannot be performed.

On the other hand, in the conventional pulse width modulation method, when the display area of halftone display is large in the X direction (horizontal direction of the screen), noise is generated due to the rising or falling edge of the pulse that changes simultaneously during one horizontal period. There was a problem in that the display brightness was lowered.

Further, when the display area for halftone display is large in the Y direction (vertical direction of the screen), there are problems in that the frequency component of the pulse applied to the liquid crystal becomes high, the display brightness decreases, and crosstalk increases.

An object of the present invention is to use a voltage pulse with a pulse intensity that divides one horizontal period into two, so that even if the display area of halftone display is expanded in the X and Y directions, the display brightness does not decrease, and the display quality is improved. An object of the present invention is to provide a liquid crystal display device capable of displaying multiple gradations without deterioration.

[Means for Solving the Problems] In order to achieve the above object, the gradation display method according to the present invention converts one line data taken into the X@ dynamic circuit into YI
In the gradation display method of a matrix type display panel that displays on horizontal lines that are sequentially instructed by a drive circuit, frame thinning that controls on/off of the display tod in frame units and pulses applied to each Xl flow line during one horizontal period are used. Pulse width modulation for modulating the width is used in combination, and the frame thinning is performed by thinning out each frame in the form of a diagonal dot pattern, and shifting the diagonal dot pattern to be thinned out each time the frame changes. It is.

In this method, preferably each of the Xl! Reduce the number of pulse changes applied to the flow line.

Display data corresponding to the first and second pulses applied within one horizontal period to each X* drive line are exchanged.

Alternatively, the first and second The display data corresponding to the second pulse is replaced.

In addition, the liquid crystal display device according to the present invention includes an XrR circuit that captures one line of display data and outputs it to the liquid crystal panel, and a Y drive circuit that sequentially instructs the horizontal line on which the data output from the X drive circuit should be displayed. and a frame thinning means for generating frame thinning data for controlling on/off a display dot in units of frames according to a lower data portion of display data constituting one dot.

a first line memory that stores one line of upper-order data of the display data constituting the one dot; a second line memory that stores one line of frame thinning data output from the frame thinning circuit; Said first
The upper data for one line in the line memory of
means for sequentially supplying the frame thinning data in the line memory to the X drive circuit within one horizontal period, and the frame thinning data and the upper data corresponding to the dot in the frame according to the position of the dot, and means for replacing the Xs drive circuit at the latest before applying the Xs drive circuit.

In this apparatus, the frame thinning means is, for example, 2N lines in the Y direction and m dots (N) in the X direction.

(m is an integer) is thinned out as one unit.

[Function] In the present invention, a frame thinning method and a pulse width modulation method are used together for multi-gradation display, and.

Measures are taken to prevent display brightness from decreasing.

That is, in the frame thinning method, frame thinning data is generated according to lower-order data of display data of one dot and a plurality of bits.

Furthermore, pulse width modulation control is performed based on this frame thinning data and the upper data of the two types of display data. Regarding this control, the phase of the liquid crystal applied voltage pulse that realizes halftone display is changed in the X direction. A phase inversion circuit that modulates the phase of adjacent dots is provided to modulate the phase of the liquid crystal additional voltage pulse. In order to provide display data to the X@ drive circuit twice within one horizontal period, it is necessary to perform reading at twice the writing speed, and for this purpose, first and second line memories are provided. This first
Preferably, two second line memories are provided so that writing and reading can be performed simultaneously.

The phase inversion circuit rearranges the 2-bit data sent for 1-dot display with respect to adjacent dots in the X and Y directions, and adjusts the liquid crystal display corresponding to the rearranged 2-bit display data. Apply pulses to X#! The voltage is applied to the liquid crystal panel via the dynamic circuit. By rearranging this data, the phase of the pulse applied to the liquid crystal is reversed, and the noise caused by the rising edge and the noise caused by the falling edge are canceled out.

The so-called offset effect is used to eliminate the decrease in display brightness due to the expansion of the halftone display area.

The frame thinning circuit performs thinning processing in the form of a diagonal dot pattern. For example, one unit is 2N horizontal lines and m vertical dots (where N is an integer and 1 m is the thinning period), and vertical line thinning is performed. This makes it possible to effectively utilize the cancellation effect due to phase inversion.

(Hereinafter, blank space) [Example] Below, a liquid crystal display system according to one embodiment of the present invention will be described.
This will be explained using figures. This system receives input data of 4 bits per display dot and displays 16 gradations.

FIG. 1 is a block diagram showing one embodiment of the present invention,
13 and 14 are the upper display data respectively.

4 is a frame thinning circuit that converts the lower 3-bit display data 14 into frame thinning data FD15, and 5.6 is the upper display data 1.
Line memories LA, 2A, 7, and 8 that store frame data 15 are line memories IB that store frame thinning data 15 for one line.

It is 2B. 10 is a data select signal generating circuit that generates data select signals 2o and 21 using the pulse clock 8 and the line clock 17, and the generated data select signal 20 is a signal that repeats "high" and "low" according to the line clock 17. The data select signal 21 is a signal that repeats high and low according to the pulse clock 18 with twice the frequency of the line clock 17.11.12 is a data select circuit, and 9 is a phase inverter that rearranges two types of data. circuit, 1 is a liquid crystal panel, 2,
Reference numerals 3 denote an X drive circuit and a Y@ drive circuit that respectively drive the liquid crystal panel l.

In FIG. 1, upper display data 13 is taken into the line memory IA or line memory 2A alternately line by line, and read from the line memory that is not being read. It runs twice as fast and the same data in line memory is read twice. Read data MIA or M
2A is selected as MA by the data select circuit 11. Regarding frame thinning data 15, similar operations are performed by line memory IB and line memory 2B, and data MB is selected by data select circuit 11.

The phase inversion circuit 9 rearranges the data MA and MB sent from the data selection circuit 11 dot by dot in the X direction (horizontal direction of the screen),
Output as . The dots subject to this sorting are
For example, when rearranging the data of the phase inverting circuit 9, the dots displayed as "-" do not rearrange the input data MA, Mu, and do not rearrange the data. x drive data XA.

For dots that are output as XB and displayed as 'O', input data MA and MB are rearranged.

Output as X drive data XA and XB. That is,
In the phase inversion circuit 9, input data (MA, MB)
If = (0, 1) or (1, O), the data is rearranged using the dots displayed as "○" and output to XA and XH. (M.A.

MB) = (0, O) or (1, 1), the data remains the same even if rearranged, so it is output as is to XA and XB. Of course, for processing reasons.

Rearrangement may also be performed in these cases, and XA and XB are sent to the data select circuit 12 by a data select signal 21 that equally divides one line into two.
One of XA or XB is selected and output as XD24.

FIG. 9 shows the output data (XA) at each dot when the input data (MA, MB) = (0, 1).

XB).

Similar to the prior art shown in FIG. The display information instructed by XA) is output from Xl to Xi.

Furthermore, while the XIK motion circuit 2 is outputting the display information of the upper data XD (=XA), the data latch clock 19 captures one line of lower data XD (=XB), and the subsequent pulse clock 18 rises. XD on the way down (
=XB) is output from xl to Xi. Display information X1 to Xi applied from this Xu drive circuit 2
is the output Y of the Y drive circuit 3 which is “high” at that time.
The light is applied to the liquid crystal on one line of l-yj, and an amount of light proportional to the displayed information is transmitted. Furthermore, Y1! ! The dynamic circuit 3 is
Take in the first line clock 16 and line clock 17, set Yl to "high'", then line clock 17
, "high" is sequentially shifted from Y2 to Yj.

In the liquid crystal display circuit of FIG. 1 described above.

(upper display data, frame thinning data) = (0, 1
) is input to the i-th row and j-column display as shown in FIG. The display pulse shown in FIG. 11 is output.

According to FIG. 11, the output pulses of the adjacent X dots are different, and when the pulse of one dot rises, the pulses of the adjacent dots fall simultaneously. In this way, the change edges of the display pulses of adjacent dots become rising and falling edges, which cancels out each noise and eliminates or reduces the brightness drop in the liquid crystal display, that is, the canceling effect. is born.

Also, one line of display pulse at a certain X dot,
The display pulse of the next line or the display pulse of the previous line is 1
By combining the display pulses into one line, the rise or fall of the display pulse during one line is eliminated, and the fluctuation of the display pulse during one frame period is halved. This reduces one frequency component by half, resulting in the effect of reducing crosstalk occurring in the liquid crystal panel 1.

Next, the frame thinning circuit 4 will be explained.

The frame thinning circuit 4 has eight types of thinning circuits 25 to 32, as in the conventional example shown in FIG.

8 types of thinned data 33 output from these circuits
This is a selection port NI41 for selecting one of .about.40. As described above, each of the one-thinning circuits 25 to 32 receives the first line clock 16. Line clock 17. The data latch clock 19 generates thinned data according to each thinning rate.

FIG. 12 shows thinning data in the form of a diagonal dot pattern according to the present invention (showing the case of a thinning rate of 1 as an example of 415) (the shaded area indicates "1" (display on)),
Unlike the conventional technology shown in the figure, the screen Y
2 lines in the direction (vertical direction) and 1 m dot (m is the thinning period of m frames) in the X direction (horizontal direction).
This is data that has been thinned out as a unit. The Y direction of one unit of thinned data, that is, two lines, are the same data. or.

In order to prevent flickering on both sides of the liquid crystal panel 1, the thinned-out data is shifted in units of two lines in the Y direction for each frame.

FIG. 20 shows a circuit example of a thinning circuit that generates the thinning data shown in FIG. 12. This circuit corresponds to one thinning circuit included in the frame thinning circuit as shown in FIG.

This thinning circuit includes a quinary frame counter 201 that counts the first line clock 16, a value of the frame counter 201 that is loaded by the first line clock 16, and counts the output of the line clock 17 divided by 172 using this value as an initial value. 5 line counters 202 that perform this frequency division, a divider 205 that performs this frequency division, and a quinary data counter 2 that loads the output value of the line counter 202 with a line clock and counts data latch clocks using this value as an initial value.
03, and a bit halftone signal generating port 8204 that outputs a predetermined dot pattern according to the output value of the data counter 203. Frame counter 201
The reason why the data counter 203 is a quinary counter is to correspond to the denominator value (frame period) of the thinning rate 415, and can change depending on the thinning rate. Also,
The reason why the line counter 202 is a quinary counter is because
The thinning pattern in Figure 2 corresponds to the fact that there are 5 different line patterns out of 10 lines, and the fact that the line clock is divided by 2 corresponds to the line pattern changing in units of 2 lines. . The line pattern is '01111' in this example.

'10111', '11011', '11101',
The contents of the '1111G' pattern and the conoline pattern vary depending on the thinning rate.

The bit halftone signal generation circuit 204 is a data counter 20
It generates different line patterns in response to the output values of 3, and can be configured with a decoder or a memory table.

According to this thinning circuit, within one frame, the phase of the line pattern is shifted horizontally by one dot every two lines, and also shifted by one dot every frame. Therefore, a thinning pattern in the form of a diagonal dot pattern as shown in FIG. 12 is generated.

Note that in this thinning circuit configuration, parallel data is output from the selector 41 in FIG. 3. Therefore, a line memory with a width of multiple bits is used. If the line memory inputs serial data, it is necessary to perform parallel-to-serial conversion.

The details of each block in FIG. 1 have been described above.

Next, a display example using the liquid crystal display system of FIG. 1 will be explained using FIGS. The opening electrodes are designated Yl to Y6 from the top.

FIG. 13 shows the xm driving pulse and the display brightness level (1
6.7%) in the upper display data MA and frame thinning data MB indicates "O1" in the display off state.
1, a○" indicates "1" in the display on state, and
The numbers of the X driving pulses refer to pulses 1 to 4 shown in FIG. 7, respectively.

In FIG. 13, all upper display data MA is “0”
Therefore, for a dot whose frame thinning data MB is "O", the X driving pulse becomes pulse l, and for a dot whose frame thinning data MB is "1", the operation shown in FIG. 8 is performed. The X@ motion pulse becomes pulse 2 or pulse 3 through the phase inversion circuit 9 . Therefore, the brightness level of the entire screen is 16.7% for each frame.

The waveform of the Xl @ motion pulse in Fig. 13 is shown in Fig. 14.
The frame is a combination of "Pulse 2. Pulse 3" or "Pulse 3. Pulse 2" every two lines in the Y direction, and "X1→
Display pulses are applied to each X electrode in the order of X2→X3J and rX4→X5→X6J. 2 frames are rX3→
Display pulses are applied to each X electrode in the order of X1→X2J and rX6→X4→X5J, and in the third frame, rX2→
Display pulses are applied to each X electrode in the order of "X3→X1" and rX5→X6→X4J. Since the Malam thinning data MB in FIG. 13 has a thinning rate of 1/3, the frames from the 1st frame to the 3rd frame are repeated from the 4th frame onward. In the two lines Yl and Y2 of the l-th frame, "pulse 2. pulse 3" is applied to the X1 electrode, and
"Pulse 3. Pulse 2" is applied to the electrodes, and the changing points of the pulses cancel each other out between these two electrodes.

Similarly, in the two lines Y3 and Y4, "Pulse 3. Pulse 2" is applied to the X2 electrode, and "Pulse 2. Pulse 3" is applied to the X5 electrode.

The changing points of the pulses cancel each other out between these two electrodes. Furthermore, in the two lines Y5 and Y6, the points of change of the pulses between the two electrodes are canceled out by the X3 electrode and the X6 electrode.

After the second frame, the two electrodes similarly cancel out the change points of the pulses, and this effect prevents a decrease in brightness due to an enlargement of the display area.

FIG. 15 shows the X driving pulse and the display brightness level (66.7%) when the upper display data MA is all l'' and the frame thinning data MB is thinning data with a thinning rate of 1/3. Display data MA is all “
1'', the frame thinning data MB is “1”.
For the dot, Xl! For the dots where the operating pulse is pulse 4 and the frame thinning data MB is "On,"
The X* motion pulse becomes pulse 2 or pulse 3. Therefore, the brightness level of the entire screen is the same for each frame.

It becomes 66.7%. The waveform of the xg motion pulse in FIG. 15 is shown in FIG. 16. As in the case of FIG. 14, Xl and X4. X
2 and X5. The pulse change points are canceled out between each of the two electrodes X3 and X6. Also, the change point that is not canceled out between the two electrodes (for example, the rising change point of the 1st frame, the X2 electrode, and the Y3 line).

The changing points of the X electrodes other than the paired electrode (in this case, the X5 electrode) are used to cancel each other out (in this case, the falling changing point at the X4 electrode). In other words, the number of rising changes in each line and the number of falling changes are the same, thereby canceling out the changing points of the pulses and preventing a decrease in brightness due to an enlargement of the display area.

As described above, the thinning method of the frame thinning circuit 4 in FIG.
It can be considered in the same way even when 2N lines and m dots in the X direction are taken as 1 unit, such as 8 lines (
N is an integer).

Also, without controlling the Y direction of the screen, m dots in the X direction are taken as one unit, and n out of m dots in the X direction (m lines in the vertical direction)
A method of thinning out dots (n lines in the vertical direction) can be similarly considered, and will be explained using FIGS. 17 to 19.

FIG. 17 shows the frame thinning data of each frame, taking the 1 thinning rate of 415 as an example, and the shaded area is
Represents “1” when the display is on.

In FIG. 18, the upper display data MA is all "O", and the frame thinning data MB is all lines in the Y direction of the screen,
FIG. 7 is a diagram showing the Xa driving pulse and the display brightness level (16.7%) when the data is thinned out at a thinning rate of 1/3 with three dots in one direction as one unit. As in FIG. 13, since the upper display data MA is all "0", for the dot whose frame thinning data MB is "O",
The rotation pulse becomes pulse l, and for the dot '1'', it is processed through the phase inversion circuit 9 whose operation is shown in FIG.
xll! The active pulse becomes pulse 2 or pulse 3.

Therefore, the brightness level for one display is 16.7 for each frame.
%. The waveform of this Xt1 driving pulse is shown in FIG.

In Figure 19, in the first frame, pulses are applied in the order of pulse 2 → pulse 3 → pulse 2 → pulse 3 at the X1 electrode, and pulses are applied in the order of pulse 3 → pulse 2 → pulse 3 → pulse 2 at the X4 electrode. is applied, and the changing points of the pulses cancel each other out between these two electrodes. Other X2.
X3. Pulse 1 is applied to all the X5° and X6 electrodes.

Similarly, in the second frame, between the X2 and X5 electrodes.

In the third frame, the pulse change points cancel each other out between the X3 and X6 electrodes.

Above, we have explained the X* dynamic pulse and the brightness level using the thinning rate of 1/3 as an example, but the same can be said for other thinning rates. It is possible to prevent a decrease in display brightness due to this phenomenon, and to achieve multi-gradation display with stable display brightness.

Furthermore, although the above embodiments have been described only regarding liquid crystal panels, the present invention is also applicable to other flat display panels such as plasma and EL panels.

Furthermore, when creating colors, by applying the present invention to each of red, blue, and green, it becomes possible to create pseudo multicolors.

[Effects of the Invention] According to the present invention, it is possible to display gradations in finer stages, which could not be achieved using the frame thinning method.

This has a great effect when displaying multiple gradations. For example, if you simply use the frame thinning method to obtain a gradation display with a brightness level of 10%, the thinning rate will be 1/1 with poor display quality.
However, according to the present invention, by setting the upper display data to O'' and setting the frame thinning data to a thinning rate of 115, it is possible to display gradations with good display quality.

In addition, by using a thinning method of 2N lines in the Y direction of the screen and m dots in the X direction as a unit, X#!
The canceling effect of the change point of the dynamic pulse can be effectively utilized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a 16-gradation display system according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional frame thinning gradation display system, and FIG. 3 is a frame thinning circuit structure aZ, FIG. 5 is a block diagram of a conventional pulse width modulation gradation display system; FIGS. 6 and 7 are illustrations of pulse width modulation display pulses; FIG. 11 to 11 are explanatory diagrams of the phase inversion circuit in FIG. 1, and FIGS. 12 to 16 are explanatory diagrams in the case where the thinning method in the present invention is set to two lines in the Y direction and m dots in the X direction as one unit, Figures 17 to 19 are explanatory diagrams of the thinning method in the present invention when all lines in the Y direction and m dots in the FIG. 2 is a block diagram of an example circuit. 1...Liquid crystal panel, 2...xg motion circuit, 3...Y
D-operation open circuit 4...Frame thinning circuit, 5-8...
Line memory, 9... Phase inversion circuit, 10... Data selector signal generation circuit, 11.12... Data selector. 13.14... Upper and lower display data, 15... Frame thinning data, 16... First line clock,
17...Line clock, 18...Pulse clock, 19...Data latch clock.

Claims (1)

[Claims] 1. In a gradation display method of a matrix display panel in which one line of data taken into an X drive circuit is displayed on horizontal lines sequentially instructed by a Y drive circuit, display dots are displayed in units of frames. A combination of frame thinning to control on/off of the X drive line and pulse width modulation to modulate the width of the pulse applied to each X drive line in one horizontal period is used. A gradation display method characterized in that the diagonal dot pattern to be thinned out is shifted every time a frame changes. 2. Swapping the display data corresponding to the first and second pulses applied to each X drive line within one horizontal period so as to reduce the number of changes in the pulse applied to each X drive line. The gradation display method according to claim 1, characterized in that: 3. The first and second pulses are sequentially applied to each X drive line within one horizontal period so that the number of positive direction changes and the number of negative direction changes of the pulses applied to all the X drive lines are approximately the same. 2. The gradation display method according to claim 1, wherein display data corresponding to the second pulse is replaced. 4. A liquid crystal display device comprising an X drive circuit that captures one line of display data and outputs it to a liquid crystal panel, and a Y drive circuit that sequentially instructs horizontal lines on which the data output from the X drive circuit should be displayed. Frame thinning means for generating frame thinning data for controlling display dots on/off in units of frames according to lower data portions of display data constituting one dot; and storing upper data portions of the display data constituting one dot for one line. a second line memory that stores one line of frame thinning data output from the frame thinning circuit; one line of upper-order data in the first line memory and the second line memory; means for sequentially supplying the frame thinning data in the line memory of the frame to the X drive circuit within one horizontal period; and the frame thinning data and the upper data corresponding to the dot in accordance with the position of the dot in the frame; A liquid crystal display device characterized in that the liquid crystal display device is further provided with a means for exchanging the voltage at the latest before applying it to the X drive circuit. 5. The frame thinning means includes 2N lines in the Y direction,
5. The liquid crystal display device according to claim 4, wherein m dots in one direction (N, m are integers) are thinned out as one unit.