JPH03184097A - Method and device for adaptive conversion encoding - Google Patents

Abstract

PURPOSE:To compress auxiliary information and to improve encoding quality by varying block length by using the difference between blocks of a normalized signal obtained by normalizing an input signal. CONSTITUTION:The best block length is selected by using the difference between blocks of the normalized signal obtained by normalizing the input signal with different block length and the normalized signal corresponding to the best block length is converted linearly and quantized to transmit information. Namely, a linear converting circuit 3 performs discrete linear conversion by using the best block length supplied from a selector 27 and supplies the obtained conversion coefficient to a quantizer 4 and a bit distributing circuit 6. The bit distributing circuit 6 distributes bits by using the conversion coefficient supplied from the linear converting circuit 3 and the quantizer 4 quantizes the conversion coefficient supplied from the linear converting circuit 3 by using the bit distribution information. The quantized conversion coefficient and bit distribution information are multiplexed by a multiplexing circuit 15 with the optimum block length and the dispersion value of the input signal and sent out to a transmission line 8. Consequently, the auxiliary information is compressed to improve the encoding quality.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to band compression technology for signals such as voice/music, and in particular to band compression technology that performs band compression after linearly converting an input signal obtained in the time domain to another domain. Regarding technology.

(Prior art) Bandwidth compression is the process of reducing the amount of information contained in signals such as voice/music in order to efficiently transmit the information contained in signals such as voice/music using lines with limited transmission capacity. Differential Pulse Code Modulation [ADPCM] (Digital Coding on Waveforms)
italCoding of Waveforms)
, Prentice Hall Co.
-Ha l l), 1984, p. 308;
(hereinafter referred to as “Reference 1”) and adaptive transform coding [ATC]
(IEEE TRANSACTIONS on ANISP)
ON ASSP) Volume 27, No. 1, 1979, 89-9
See page 5; hereinafter referred to as "Reference 2") is known.

The outline of ATC will be briefly explained below according to Document 2.

FIG. 4 is a block diagram showing an example of the configuration of the ATC. In an encoder comprising linear transformation, bit allocation, and quantization, an input signal is supplied to a linear transformation circuit 3 via an input terminal 1. In general, discrete values are supplied to the input terminal 1, and a linear transformation circuit 3 performs N-point discrete linear transformation in units of input samples equal to a predetermined integer N. N is called the block length. As this N-point discrete linear transformation,
A Walsh-Hadamard transform (WATL discrete Fourier transform (DFT), discrete cosine transform (DCT), KL inverse transform (KLT), etc.) is used. The total number N of transform coefficients output from the linear transform circuit 3 are each quantized by a quantizer 4 according to a bit allocation to be described later, and then supplied to a multiplexing circuit 5. The quantizer 4 includes a number of quantizers equal to the block length N, and each transform coefficient is quantized by a dedicated quantizer. The bit allocation circuit 6 calculates the quantization bit allocation corresponding to the amplitude of the transform coefficient and supplies it to the quantizer 4. The multiplexing circuit 5 multiplexes the quantized transform coefficients supplied from the quantizer 4 and the information used for bit distribution supplied from the bit distribution circuit 6, and transmits them to the transmission path 8.
Send to.

In the decoder, which consists of bit allocation, inverse quantization, and linear inverse transformation, the multiplexed signal from the transmission line 8 is separated by a separation circuit 9, and the signal from the quantizer 4 is sent to the inverse quantizer 10, which performs bit allocation and linear inverse transformation. The signal from circuit 6 is supplied to bit allocation circuit 11. The bit allocation circuit 11 determines the bit allocation for each transform coefficient in exactly the same manner as the bit allocation circuit 6 of the encoder.

The transform coefficients dequantized by the dequantizer 10 according to the bit allocation determined by the bit allocation circuit 11 are converted again into a total number N of time domain signal samples by the linear inverse transform circuit 12, and are sent to the output terminal 14. Supplied.

There are several types of allocation methods in bit allocation circuits, but here we will use the method described in Document 2 as the fifth method.
This will be explained with reference to Figures (a) and (b).

This method minimizes the squared quantization error when dequantized in the decoder. In order to reduce the amount of auxiliary information regarding bit allocation, the transform coefficients are thinned out once, and then the interpolated values are Optimize the number of bits using The bit allocation circuitry shown in FIG. 4 is as shown in FIG.
). The conversion coefficients obtained by the linear conversion circuit 3 in FIG. 4 are supplied to the thinning circuit 42 via the input terminal 41 in FIG. 5(a). The decimation circuit 42 squares each of the N conversion coefficients, and performs 1/H decimation using the average value for each integer value M (M is a divisor of N) as a representative value. The obtained L=N/H sample values are each quantized by a quantizer 43 and supplied to an output terminal 44 and an inverse quantizer 45. The quantizer 43 and inverse quantizer 45 may be omitted in some cases. In the interpolation circuit 46, after taking the base-2 logarithm, M times linear interpolation is performed in the logarithm domain. Using the interpolated signal, the quantizer 4 in FIG.
The bit allocation in is performed by the bit number optimization circuit 47 according to the following equation.

Here, R2 is the first conversion coefficient (i=1.2...
. The result is transmitted to the output terminal 48 and fed to the quantizer 4. IEE Transactions on AnisSP (IEE Transactions on ANISP) has shown that the squared quantization error can be minimized by allocating bits using equation (1).
IEEE TRANSACTIONS ON AS
SP) Vol. 25, No. 4, 1977, pages 299-309; (hereinafter referred to as "Reference 3"). The thinned signal obtained at the output terminal 44 is sent to the transmission line 8 as auxiliary information via the multiplexing circuit 5 shown in FIG. On the other hand, the bit allocation circuit 11 shown in FIG. 4 is configured as shown in FIG. 5(b). The signal from the separation circuit 9 of FIG. 4 is supplied to the interpolation circuit 46 via an input terminal 49. The bit allocation circuit 6 in the encoder includes a quantizer 43 and an inverse quantizer 45
, the bit allocation circuit 11 in the decoder also has a corresponding inverse quantizer 45. The interpolation circuit 46 and the bit number optimization circuit 47 perform the same interpolation and bit number optimization as the interpolation circuit 46 and the bit number optimization circuit 47 in the encoder described above.

Therefore, signals for completely equal bit allocation are obtained at the output terminal 48 in FIG. 5(a) and the output terminal 50 in FIG. 5(b), and corresponding signals are obtained on the encoder and decoder sides. quantization/inverse quantization is performed.

In the explanation so far, the signal supplied from the bit allocation circuit 6 to the multiplexing circuit 5 as auxiliary information is the square value of the thinned-out transform coefficient obtained at the output terminal 44 in FIG. 5(a). However, the purpose of transmitting this signal to the decoder is to share approximate values of transform coefficients used for bit allocation between the encoder and the decoder. As methods for transmitting auxiliary information for this purpose, methods using PARCOR coefficients, ADPCM, vector quantization, and the like are known in addition to the square value of thinned-out transform coefficients.

In the encoder, the input signal can also be normalized for the purpose of obtaining transform coefficients whose amplitude does not depend on the power of the input signal at the output of the linear transform circuit 3 of FIG. In this case, as shown in FIG. 6, the input signal is normalized through the normalization circuit 2 and then supplied to the linear conversion circuit 3. In the decoder, the output of the linear inverse transform circuit 12 is subjected to processing opposite to that of the normalization circuit 2 in the inverse normalization circuit 13, and then sent to the output terminal 1.
4. The reference value used for normalization is the multiplexing circuit 5
The signal is multiplexed with the signals from the quantizer 4 and the bit allocation circuit 6, and is transmitted to the decoder via the transmission path 8.

On the decoder side, the signal is separated from the signal supplied to the dequantizer 10 and bit allocation circuit 11 by the separation circuit 9, and then transmitted to the denormalization circuit 13. FIGS. 7(a) and 7(b) show the configurations of the normalization circuit 2 and the denormalization circuit 13, respectively.

The input terminal 61 in FIG. 7(a) has the input terminal 1 in FIG.
The input signal samples are provided by

After the input signal samples are temporarily stored in buffer 62,
The N samples are collectively scaled by a multiplier 63 and supplied to an output terminal 65. The output signal from the output terminal 65 is supplied to the linear conversion circuit 3 shown in FIG. The multiplier of the multiplier 63 is the reciprocal of the average value of the input sample power for one block. This value is the reciprocal of the variance for an input signal with an average of zero, and can be calculated from the variance value determined by the variance calculation circuit 64. The variance value determined by the variance calculation circuit 64 is used by the multiplier 63 to normalize the input sample, and at the same time is supplied to the multiplexing circuit 5 in FIG. 6 via the output terminal 66, and after multiplexing, It is conveyed to the decoder as auxiliary information. On the other hand, in the inverse normalization circuit shown in FIG. 7(b), the signal from the linear inverse transform circuit 12 shown in FIG. 6 is supplied to a multiplier 68 via an input terminal 67. The multiplier 68 denormalizes the output signal using the dispersion value obtained through the input terminal 69 and stores it in the buffer 70 . The dispersion value obtained at the input terminal 69 is obtained by the multiplexing circuit 5 in FIG.
The signal is transmitted from the encoder via the transmission path 8 and the separation circuit 9. Buffer 70 sequentially transmits the N decoded sample values via output terminal 71 to output terminal 14 of FIG.

(Problem to be Solved by the Invention) The number of blocks N affects the resolution of calculations performed in the linear transformation circuit 3 and linear inverse transformation circuit 12 shown in FIGS. 4 and 6, and the larger N is, the higher the resolution is. Errors caused by encoding and decoding are reduced. Further, the auxiliary information regarding bit allocation is inversely proportional to the number of blocks included in a certain period of time, and the larger N is, the more the amount of auxiliary information is reduced. This means that more main information can be sent for a given transmission capacity, leading to improved encoding quality. On the other hand, for non-stationary signals, a large N does not necessarily give a small error. This is because although the same processing is performed on input samples within the same block, if the block is long, the characteristics of a non-stationary signal may change within the same block.

Therefore, for signals with strong non-stationarity, it is better to perform encoding that follows changes in the properties of the input signal using a small block length N. In conventional ATC, block length N
Since the resolution was fixed, it was not possible to meet the conflicting demands of resolution and ability to follow changes in the properties of the input signal.

An object of the present invention is to provide an adaptive transform encoding method and apparatus that can improve encoding quality by compressing the amount of auxiliary information while satisfying the conflicting demands of resolution and tracking changes in the properties of input signals. There is a particular thing.

(Means for Solving the Problems) The present invention performs linear transformation using the specified block length when the block length is specified, and otherwise stores input signal samples in a buffer. , normalize the input sample with a plurality of block lengths, use the obtained normalized signal inter-block differences to determine the optimal block length, apply linear transformation to the normalized signal using the optimal block length, and obtain the quantizing the transform coefficient by a bit allocation calculated using the transform coefficient, and transmitting/storing the bit allocation, the value used for the normalization, and the optimal block length as auxiliary information together with the quantized output. Features.

The present invention also provides a buffer that accumulates input samples, a normalization circuit that normalizes the samples accumulated in the buffer with a plurality of block lengths and outputs a normalized signal, and a normalization circuit that normalizes the samples accumulated in the buffer with a plurality of block lengths, and a difference detection circuit that receives a normalized signal and outputs an optimal block length using the inter-block difference of the normalized signal; and an optimal block length supplied from the difference detection circuit and a block length designation signal supplied from the outside. a first selector that receives the output and selects an output according to the block length designation signal; and a linear conversion circuit that receives the output of the normalization circuit and performs linear conversion with a block length corresponding to the output of the first selector. , a bit allocation circuit that calculates bit allocation for the transform coefficients obtained by the linear conversion circuit, a quantizer that quantizes the transform coefficients according to the bit allocation obtained by the bit allocation circuit, and the first selector. The present invention is characterized by comprising a multiplexing circuit that multiplexes and transmits/stores the output of the quantizer, the output of the bit allocation circuit, and the value used for the normalization.

(Operation) The correlation between sample values of a signal is one of the parameters representing the characteristics of the signal, and signals with similar characteristics have similar correlations between signal sample values. This is also true between sample values taken from different blocks of the same signal. That is, two sets of sample values having inter-block correlation in the time domain have similar distributions of transformation coefficients after being subjected to linear transformation. Therefore, by monitoring the difference in time-domain sample values between adjacent blocks and adaptively selecting a block length that reduces the difference, it is possible to improve the resolution in the transform domain and the properties of the input signal as described above. It is possible to satisfy the contradictory demands of following changes in

The adaptive transform encoding method and apparatus of the present invention can accommodate changes in resolution and properties of input signals by making the block length N variable using inter-block differences of normalized signals obtained by normalizing input signals. It is possible to improve the encoding quality by compressing the amount of auxiliary information while satisfying the conflicting demands of tracking the auxiliary information.

(Example) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, if the block length is specified, encoding is performed with the specified block length, and in other cases, the normalized signal obtained by normalizing the input signal is used to optimize the Determine the block length and perform encoding using the optimal block length. For this purpose, storage devices 25, 26, selectors 27, 28, 29, a difference detection circuit 36, and a block length designation signal input terminal 17 are provided.

When no input signal is supplied to the block length designation signal input terminal 17, the input signal supplied to the input terminal 1 is stored in the buffer 37, and then output to one block length candidate N1.
The normalization circuit 2 uses the input signal to be normalized by the dispersion value. The normalized signal is stored in the storage device 25 and simultaneously supplied to the difference detection circuit 36. Further, the variance value used for normalization is stored in the storage device 26. Next, the samples equal to the second block length N2 are normalized in the same way as for N1, and the result is stored in the memory 25.2.
6 and is supplied to the difference detection circuit 36. In the same manner as in the case of N1 and N2 explained above, normalization using input signals is performed for the cases of multiple block lengths N3, N4, ...Nn, and the corresponding normalized signals and variance values are stored in the memory circuit. 25 and 26, and the normalized signal (also supplied to the difference detection circuit 36. However, normally N1 and N2
kuN3 kuN4...kuNn, 2N.

=N, 1 (1≦1nn). Block length N1, N
2, N3, N4,... When all calculations of normalized signals for Nn are completed, the difference detection circuit 36 calculates normalized signals yJ(N+) for each block length candidate value N1 (1≦i<n).
) (j=1...N,) and the value z one block before that
The sum δ(N1) of squared differences between blocks of normalized signals is calculated for j(N+). Optimal block length N using δ(N;)
m is selected and supplied to the selector 27. Selector 2
7 is also supplied with a block length selection signal. When the block length selection signal is supplied, the selector 27 selects the block length selection signal, and otherwise selects the optimal block length Nm supplied from the difference detection circuit 36, and outputs the selected signal.

The output signal of the selector 27 causes the selectors 28 and 29 to
The normalized signal and auxiliary information corresponding to the optimal block length Nm are selected, and the normalized signal is sent to the linear conversion circuit 3, where the auxiliary information is the dispersion value of the input signal and the optimal block length Nm.
m are respectively supplied to the multiplexing circuit 15. The optimal block length N, . . . may be transmitted to the multiplexing circuit 15 after being quantized.

The optimal block lengths N, T are also supplied to the linear transformation circuit 3. The linear transformation circuit 3 performs Nm-point discrete linear transformation using the optimum block length supplied from the selector 27, and the obtained transformation coefficients are supplied to the quantizer 4 and the bit allocation circuit 6. The bit allocation circuit 6 performs bit allocation using the transform coefficients supplied from the linear transform circuit 3, and the quantizer 4 uses the obtained bit allocation information to perform quantization of the transform coefficients supplied from the linear transform circuit 3. .

The quantized transform coefficients and the bit allocation information are multiplexed with the optimum block length Nm and the dispersion value of the input signal in the multiplexing circuit 15, and sent to the transmission line 8.

When an input signal is supplied to the block length designation signal input terminal 7, the selector 27 selects the supplied block length N, and sets it to the optimum block length Nm. Therefore, subsequent linear transformation and quantization are performed based on the supplied block length N3. Next, referring to FIG. 2, an actual procedure for selecting an optimum block length will be described, taking as an example a case where an optimum block length is determined from n types of block lengths. Here, in order to simplify the explanation, it is assumed that n=3 (the optimum block length is selected from three different block lengths) as shown in FIG.

Let time 1=0 be the time when the encoder starts operating. At time N1T (T is the sampling period), N1 input signal samples are accumulated in the buffer 37 in FIG. This state is shown in (A) of FIG. 2(a). In the same figure, N
, (1), that is, the hatched portion indicated by I, is normalized by the block length N1, and the normalized signal is stored in a storage device. At time N2T, samples equal to the second block length N2 (N1<N2) are accumulated in the buffer 37. This situation is shown in FIG. 2(a)-(B). At this time,
In the same figure, the input signal sample indicated as N1(2), that is, the hatched part indicated as ■, is normalized by the block length N1, and then N2(1
), that is, the hatched part marked I and the hatched part marked ■, are normalized by the block length N2, and the respective normalized signals are is stored in the storage device.

At time (N t + N 2) T, there is N1 in the buffer.
Samples equal to +N2 are accumulated. This situation is shown in the second
It is shown in (C) of Figure (a). At this time, in the same figure, N,
(3) Normalization is performed on the input signal sample indicated as , that is, the hatched portion indicated as ■, using the block length N1, and the normalized signal is stored in the storage device. Furthermore, at time N3T, samples equal to the third block length Na (N, <N2<N3) are completely stored in the buffer. This state is shown in (D) of FIG. 2(a).

At this time, the input signal sample shown as N 1 (4) in the same figure, that is, the hatched part shown as ■, is normalized by the block length N1, and is also shown as N2 (2). The input signal sample, that is, the hatched part marked with ■ and the hatched part marked with ■ is normalized by the block length N2, and is further displayed as N5(1). The input signal samples, that is, the hatched portions indicated by I, II, ■, ■, are normalized by the block length N3, and the respective normalized signals are stored in a storage device. Hereinafter, N,(t) stored in the storage device
, N 1 (2), N 1 (3), N 1 (4), normalized signals corresponding to N2(1) and N2(2), and normalized signals corresponding to N5(1). Using the normalized signal, the inter-block differences δ(N1), δ(N2), δ(N3
) to determine the optimal block length Nm.

The above processing procedure is summarized in FIG. 2(b). N
Taking the case of 5=2N2=4N as an example, the maximum block length N3 can be expressed by the four minimum block lengths N of ■, ■, ■, and ■. Normalization using the block length N1 for the input data of blocks 2, 2, 2, and 2 is performed in blocks 2, 2, IV, and I', respectively. I
Normalization using block length N2 for input data of blocks +n and I+IV is performed in blocks ■ and ■'', respectively. Furthermore, normalization using block length N3 for input data of blocks I+n+III+]V is performed for blocks I ’ block.

Therefore, for block I゛, which has the largest amount of processing, normalization is performed using block length N1 for ■, normalization using block length N2 for ■10■, and block length N3 for ■+■+■+■. In addition, it is necessary to perform normalization, calculate the inter-block differences δ(N, ), δ(N2), and δ(N3) of the normalized signals, and determine the optimal block length Nln using these.

That is, the time required for all these processes is N.

It is assumed that it is shorter than T.

As is clear from FIG. 2(b), the buffer 37 must have a capacity of at least N3T and is reset every N3T. A normal signal corresponding to the selected optimal block length is taken out from the storage device in N3 samples at a time, subjected to linear transformation in the linear transformation circuit 3, and then quantized in the quantizer 4 to form the transmission line shown in FIG. Sent on 8th. Therefore, transmission line 8
The data sent to N is as shown in Figure 2 (C).
The same block length continues in units of 3. Hereinafter, this block length will be referred to as a unit block. Next, the operation of the difference detection circuit 36 will be explained in detail with reference to FIG.

FIG. 3 shows details of the difference detection circuit 36. A signal supplied from the linear conversion circuit 3 in FIG. 1 is supplied to the input terminal 301, and a signal from the output terminal 314 is transmitted to the selector 27. The conversion coefficients supplied to input terminal 301 are input to switch 302, selector 304, and subtracter 305. Storage devices 3031, 3032, . . . , 303n are connected to each output terminal of the switch 302, respectively. Storage device 3031.303°,...
303n corresponds to block lengths N0, N2,...Nn, and 303n corresponds to the normalized signal z of the previous block.
J (N+-t) (J=l...N,) is stored. The selector 304 selects these storage devices 303
One of the outputs of 1.303°, . . . , 303n is selected and transmitted to the subtracter 306.

Both the switch 302 and the selector 304 are connected to the input terminal 30.
1. The output of the selector 304 is subtracted from the normalized signal supplied to the input terminal 301 by a subtracter 305, and the result is sent to a multiplier 306.
is supplied to That is, when a normalized signal corresponding to a certain block length N1 is supplied to the input terminal 301, the normalized signal two blocks before corresponding to N1 is selected by the selector 304, and the current signal supplied to the input terminal 301 is selected by the selector 304. A subtracter 305 subtracts it from the normalized signal of the block. At the same time, the current normalized signal is stored in the storage device 3031 connected by the switch 302. Multiplier 306 squares the inter-block difference of the normalized signal supplied from subtracter 305. The previous operations are performed for each normalized signal sample. The obtained inter-block difference square values are accumulated in an accumulator 307, and the sum of the inter-block difference square values of the normalized signal samples for all normalized signal samples is determined. Hereinafter, this will simply be referred to as the inter-block difference of the normalized signal. The inter-block difference of the normalized signal, which is the output of the accumulator 307, is calculated for each unit block and stored in the storage device 308.

The maximum value detection circuit 309 detects the maximum value of the inter-block difference of the normalized signal corresponding to each block length candidate value for each unit block, and stores it in the storage device 310. That is, the maximum inter-block difference values of normalized signals are stored in the storage device 310 for each unit block as many times as there are block length candidate values. Optimal block length selection circuit 31
1 is the maximum value m of these supplied from the storage device 310
The optimal block length is determined using ax (δ(Ni)) and transmitted to the selector 313. max (·) is the maximum value operator.

In the optimal block length selection circuit 311, max (δ(N
, )) and max (δ(Ni, t)) with l≦i<n-2
max (δ(hh))≧max (
Let the minimum N, y, that satisfies δ(Ni, t)) be the optimal block length Nm. If the corresponding N i+1 does not exist, N is set as the optimal block length Nff1.

Furthermore, in parallel, a sudden change detection circuit 312 detects a sudden change in the input signal characteristics using the inter-block difference of the normalized signal, and unconditionally selects the minimum block length when a sudden change is detected. This is performed by the selector 313 selecting a signal supplied to the selector 313 from the sudden change detection circuit 312 and transmitting the selected signal to the output terminal 314.

A sudden change in the input signal characteristics is detected by comparing the values of δ(N1) obtained from the storage device 308. Storage device 30
8, δ(N
1) is stored, all adjacent δ(N1)
The ratio of δp+1(Nt)/δp(N, ) and δ1)(N
, )/δp+1(N1), 1≦p<N.

/N1, and if even one exceeds a predetermined threshold Th, it is determined that a sudden change has been detected. The threshold value Th is determined empirically.

(Effects of the Invention) As described in detail above, according to the present invention, the optimum block length is selected using the inter-block difference of normalized signals obtained by normalizing with different block lengths, and In order to transmit information by linearly converting and quantizing the corresponding normalized signal, it is possible to compress the amount of auxiliary information and improve the encoding quality while satisfying the conflicting demands of resolution and tracking changes in the properties of the input signal. An improved adaptive transform encoding method and apparatus can be provided.

[Brief explanation of drawings]

Figure 1 is a block diagram showing one embodiment of the present invention, Figure 2 is a diagram showing an example of the state of a buffer that stores input samples and the procedure for selecting the optimal block length, and Figure 3 is a difference between Figure 2. FIG. 4 is a block diagram showing the details of the detection circuit; FIG. 4 is a block diagram showing a conventional example; FIGS.
Fig. 6 shows another conventional example, Fig. 7 (a), (b)
7 is a diagram showing details of the normalization circuit and the denormalization circuit in FIG. 6. FIG. In the figure, 1.17 is an input terminal, 2 is a normalization circuit, and 3
is a linear conversion circuit, 4 is a quantizer, 6 is a bit allocation circuit,
8 is a transmission path, 15 is a multiplexing circuit, 25, 26 is a storage device, 27, 28, 29 is a selector, 36 is a difference detection circuit, 37 is a buffer, and 16 is an output terminal. Figure (8) (b) (C) Figure 5 (b) - Figure 1

Claims (2)

[Claims] (1) When adaptively converting an input signal to compress and transmit/storage the information content of a signal such as voice/music, if a block length is specified, the specified block length is used. Perform a linear transformation; otherwise, store the input signal samples in a buffer, normalize the input samples with multiple block lengths, and use the resulting normalized signal block-to-block differences to determine the optimal block length. , linearly transform the normalized signal using the optimal block length, quantize the transform coefficient by a bit allocation calculated using the obtained transform coefficient, and calculate the bit allocation and the value used for normalization. A method of adaptive transform encoding, characterized in that the optimum block length is transmitted/stored as auxiliary information together with the quantized output. (2) a buffer that accumulates input samples; a normalization circuit that normalizes the samples accumulated in the buffer with a plurality of block lengths and outputs a normalized signal; and the normalized signal corresponding to the plurality of block lengths. a difference detection circuit that receives the signal and outputs an optimal block length using the inter-block difference of the normalized signal; and a difference detection circuit that receives the optimal block length supplied from the difference detection circuit and a block length designation signal supplied from the outside. The first selects the output according to the block length designation signal.
the first selector in response to the output of the normalization circuit;
a linear conversion circuit that performs linear conversion with a block length corresponding to the output of the selector; a bit allocation circuit that calculates bit allocation for the conversion coefficient obtained by the linear conversion circuit; and a bit allocation circuit that calculates the bit allocation obtained by the bit allocation circuit. a quantizer that quantizes the transform coefficient according to the method, and multiplexes and transmits/stores the output of the first selector, the output of the quantizer, the output of the bit allocation circuit, and the value used for the normalization. An adaptive transform encoding device comprising a multiplexing circuit.