JPH03184099A - Method and device for adaptive conversion encoding - Google Patents

Abstract

PURPOSE:To compress auxiliary information and to improve the encoding quality by varying block length by using the difference between blocks of a normalized signal obtained by normalizing an input signal. CONSTITUTION:The difference between blocks of the normalized signal corresponding to plural block length values is found and the best block length is determined by using the ratio of the difference between blocks corresponding to two adjacent block length values when plural block length values are arranged in order and the difference between blocks. Then, a linear converting circuit 3 performs discrete linear conversion by using the best block length and the obtained conversion coefficient is supplied to a quantizer 4 and a bit distributing circuit 6. The bit distributing circuit 6 performs bit distribution by using the conversion coefficient supplied from the circuit 3 and the quantizer 4 quantizes the conversion coefficient supplied from the linear converting circuit 3 by using the bit distribution information. The quantized conversion coefficient and bit distribution information are multiplexed by a multiplexing circuit 15 with the best block length and the dispersion value of the input signal and sent out to a transmission line 8. Thus, the auxiliary information is compressed to improve the encoding quality.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to band compression technology for signals such as voice/music, and in particular to band compression technology that performs band compression after linearly converting a human signal obtained in the time domain to another domain. Regarding technology.

(Prior art) Bandwidth compression is the process of reducing the amount of information contained in signals such as voice/music in order to efficiently transmit the information contained in signals such as voice/music using lines with limited transmission capacity. Differential pulse code modulation [AD PCM] (digital
Coding on Waveforms, (Di
Digital Coding of Waveforms
), Prentice Hall Co.
e-Hal 1), 1984, p. 308 (hereinafter referred to as "Reference 1") and adaptive transform coding [ATC]
(IEEE TRANSACTIONS on ANISP)
ON ASSP) Volume 27, No. 1, 1979, 89-9
See page 5; hereinafter referred to as "Reference 2") is known.

The outline of ATC will be briefly explained below according to Document 2.

FIG. 4 is a block diagram showing an example of the configuration of the ATC. In an encoder comprising linear transformation, bit allocation, and quantization, an input signal is supplied to a linear transformation circuit 3 via an input terminal 1. In general, discrete values are supplied to the input terminal l, and a linear transformation circuit 3 performs N-point discrete linear transformation in units of input samples equal to a predetermined integer N. N is called the block length. As this N-point discrete linear transformation,
A Walsh-Hadamard transform (WATL discrete Fourier transform (DFT), discrete cosine transform (DCT), KL transform (KLT), etc. is used.The total number N of transform coefficients, which is the output of the linear transform circuit 3, is determined according to the bit allocation described later. Each transform coefficient is quantized by a quantizer 4 and supplied to a multiplexing circuit 5.The quantizer 4 includes a number of quantizers equal to the block length N, and each transform coefficient is quantized by a dedicated quantizer. The bit allocation circuit 6 calculates the quantization bit allocation corresponding to the amplitude of the transform coefficient and supplies it to the quantizer 4.The multiplexing circuit 5 The quantized transform coefficients and the information used for bit allocation supplied from the bit allocation circuit 6 are multiplexed and sent to the transmission line 8.

In the decoder, which consists of bit allocation, inverse quantization, and linear inverse transformation, the multiplexed signal from the transmission line 8 is separated by a separation circuit 9, and the signal from the quantizer 4 is sent to the inverse quantizer 10, which performs bit allocation and linear inverse transformation. The signal from circuit 6 is supplied to bit allocation circuit 11. The bit allocation circuit 11 determines the bit allocation for each transform coefficient in exactly the same manner as the bit allocation circuit 6 of the encoder.

The transform coefficients dequantized by the dequantizer 10 according to the bit allocation determined by the bit allocation circuit 11 are converted again into a total number N of time domain signal samples by the linear inverse transform circuit 12, and are sent to the output terminal 14. Supplied.

There are several types of distribution methods in the distribution circuit, and here the method described in Document 2 will be explained with reference to FIGS. 5(a) and 5(b).

This method minimizes the squared quantization error when dequantized in the decoder. In order to reduce the amount of auxiliary information regarding bit allocation, the transform coefficients are thinned out once, and then the interpolated values are Optimize the number of bits using The bit allocation circuit I shown in FIG.
). The conversion coefficients obtained by the linear conversion circuit 3 of FIG. 4 are supplied to the interpolation circuit 42 via the input terminal 41 of FIG. 5(a). The decimation circuit 42 squares each of the N conversion coefficients, and performs 1/H decimation using the average value for each integer value M (M is a divisor of N) as a representative value. The obtained sample value of L=N/H is sent to the quantizer 43
are respectively quantized by the output terminal 44 and the inverse quantizer 45.
supplied to The quantizer 43 and inverse quantizer 45 may be omitted in some cases. In the interpolation circuit 46, after taking the base-2 logarithm, M times linear interpolation is performed in the logarithm domain. Using the interpolated signal, the bit allocation in the quantizer 4 of FIG. 4 is determined by the bit number optimization circuit 47 according to the following formula.
It will be held in

Here, R1 is the i-th conversion coefficient (i=1.2...
. The result is transmitted to the output terminal 48 and fed to the quantizer 4. By allocating bits using Equation (1), it is possible to minimize the squared quantization error, as shown by FEE Transactions on Anyspi (
IEEE TRANSACTIONS ON AS
SP) Vol. 25, No. 4, 1977, pages 299-309; (hereinafter referred to as "Reference 3"). The thinned signal obtained at the output terminal 44 is sent to the transmission line 8 as auxiliary information via the multiplexing circuit 5 shown in FIG. On the other hand, the bit allocation circuit 11 shown in FIG. 4 is configured as shown in FIG. 5(b). The signal from the separation circuit 9 of FIG. 4 is supplied to the interpolation circuit 46 via an input terminal 49. The bit allocation circuit 6 in the encoder includes a quantizer 43 and an inverse quantizer 45
, the bit allocation circuit 11 in the decoder also has a corresponding inverse quantizer 45. The interpolation circuit 46 and the bit number optimization circuit 47 perform the same interpolation and bit number optimization as the interpolation circuit 46 and the bit number optimization circuit 47 in the encoder described above.

Therefore, signals for completely equal bit allocation are obtained at the output terminal 48 in FIG. 5(a) and the output terminal 50 in FIG. 5(b), and corresponding signals are obtained on the encoder and decoder sides. quantization/inverse quantization is performed.

In the explanation so far, the signal supplied from the bit allocation circuit 6 to the multiplexing circuit 5 as auxiliary information is the square value of the thinned-out transform coefficient obtained at the output terminal 44 in FIG. 5(a). However, the purpose of transmitting this signal to the decoder is to share approximate values of transform coefficients used for bit allocation between the encoder and the decoder. As methods for transmitting auxiliary information for this purpose, methods using PARCOR coefficients, ADPCM, vector quantization, and the like are known in addition to the square value of thinned-out transform coefficients.

In the encoder, the input signal can also be normalized for the purpose of obtaining transform coefficients whose amplitude does not depend on the power of the input signal at the output of the linear transform circuit 3 of FIG. In this case, as shown in FIG. 6, the input signal is normalized through the normalization circuit 2 and then supplied to the linear conversion circuit 3. In the decoder, the output of the linear inverse transform circuit 12 is subjected to processing opposite to that of the normalization circuit 2 in the inverse normalization circuit 13, and then sent to the output terminal 1.
4. The reference value used for normalization is the multiplexing circuit 5
The signal is multiplexed with the signals from the quantizer 4 and the bit allocation circuit 6, and is transmitted to the decoder via the transmission path 8.

On the decoder side, the signal is separated from the signal supplied to the dequantizer 10 and bit allocation circuit 11 by the separation circuit 9, and then transmitted to the denormalization circuit 13. FIGS. 7(a) and 7(b) show the configurations of the normalization circuit 2 and the denormalization circuit 13, respectively.

The input terminal 61 in FIG. 7(a) has the input terminal 1 in FIG.
The input signal samples are provided by

After the input signal samples are temporarily stored in buffer 62,
The N samples are collectively scaled by a multiplier 63 and supplied to an output terminal 65. The output signal from the output terminal 65 is supplied to the linear conversion circuit 3 shown in FIG. The multiplier of the multiplier 63 is the reciprocal of the average value of the input sample power for one block. This value is the reciprocal of the variance for an input signal with an average of zero, and can be calculated from the variance value determined by the variance calculation circuit 64. The variance value determined by the variance calculation circuit 64 is used by the multiplier 63 to normalize the input sample, and at the same time is supplied to the multiplexing circuit 5 in FIG. 6 via the output terminal 66, and after multiplexing, It is conveyed to the decoder as auxiliary information. On the other hand, in the inverse normalization circuit shown in FIG. 7(b), the signal from the linear inverse transform circuit 12 shown in FIG. 6 is supplied to a multiplier 68 via an input terminal 67. The multiplier 68 denormalizes the output signal using the dispersion value obtained through the input terminal 69 and stores it in the buffer 70 . The dispersion value obtained at the input terminal 69 is obtained by the multiplexing circuit 5 in FIG.
The signal is transmitted from the encoder via the transmission path 8 and the separation circuit 9. Buffer 70 sequentially transmits the N decoded sample values via output terminal 71 to output terminal 14 of FIG.

(Problem to be Solved by the Invention) The number of blocks N affects the resolution of calculations performed in the linear transformation circuit 3 and linear inverse transformation circuit 12 shown in FIGS. 4 and 6, and the larger N is, the higher the resolution is. Errors caused by encoding and decoding are reduced. Further, the auxiliary information regarding bit allocation is inversely proportional to the number of blocks included in a certain period of time, and the larger N is, the more the amount of auxiliary information is reduced. This means that more main information can be sent for a given transmission capacity, leading to improved encoding quality. On the other hand, for non-stationary signals, a large N does not necessarily give a small error. This is because although the same processing is performed on input samples within the same block, if the block is long, the characteristics of a non-stationary signal may change within the same block.

Therefore, for signals with strong non-stationarity, it is better to perform encoding that follows changes in the properties of the input signal using a small block length N. In conventional ATC, block length N
Since the resolution was fixed, it was not possible to meet the conflicting demands of resolution and ability to follow changes in the properties of the input signal.

An object of the present invention is to provide an adaptive transform encoding method and apparatus that can improve encoding quality by compressing the amount of auxiliary information while satisfying the conflicting demands of resolution and tracking changes in the properties of input signals. There is a particular thing.

(Means for Solving the Problems) The present invention performs linear transformation using the specified block length when the block length is specified, and otherwise stores input signal samples in a buffer. , normalize the input samples with multiple block lengths to obtain the normalized signal,
Calculate the inter-block differences of the normalized signals corresponding to the plurality of block lengths, and calculate the ratio of the inter-block differences corresponding to two adjacent block lengths when the plurality of block lengths are arranged in order of size and the block. determining an optimal block length using the difference between the blocks, performing a linear transformation on the normalized signal using the optimal block length, quantizing the transform coefficient according to a bit allocation calculated using the obtained transform coefficient, and It is characterized in that bit allocation, the value used for the normalization, and the optimal block length are transmitted/stored as auxiliary information together with the quantized output.

The present invention also provides a buffer that accumulates input samples, a normalization circuit that normalizes the samples accumulated in the buffer with a plurality of block lengths and outputs a normalized signal, and a normalization circuit that normalizes the samples accumulated in the buffer with a plurality of block lengths, and a difference detection circuit that receives a normalized signal and outputs an optimal block length using the inter-block difference of the normalized signal; and an optimal block length supplied from the difference detection circuit and a block length designation signal supplied from the outside. a first selector that receives the output and selects an output according to the block length designation signal; and a linear conversion circuit that receives the output of the normalization circuit and performs linear conversion with a block length corresponding to the output of the first selector. , a bit allocation circuit that calculates bit allocation for the transform coefficients obtained by the linear conversion circuit, a quantizer that quantizes the transform coefficients according to the bit allocation obtained by the bit allocation circuit, and the first selector. a multiplexing circuit that multiplexes and transmits/stores the output of the quantizer, the output of the bit allocation circuit, and the value used for the normalization; a switch that switches signals according to a plurality of block lengths, a plurality of storage devices connected to the plurality of output terminals of the switch, a fourth selector that selects one of the outputs of the plurality of storage devices; a subtracter that subtracts the fourth selector output from the input normalized signal; a multiplier that squares the subtracter output; an accumulator that accumulates the output of the multiplier; a third storage device for storing the output of;
a maximum value detection circuit that calculates the maximum value from a plurality of outputs of the third storage device; and a fourth storage device that stores the output of the maximum value detection circuit.
a storage device, a divider that calculates the ratio of two data among the plurality of outputs of the fourth storage device, a fifth storage device that stores the output of the divider, and the fifth storage device. an optimal block length selection circuit that determines an optimal block length using the output of the third storage device; a sudden change detection circuit that receives a plurality of outputs from the third storage device and detects a significant change among the plurality of outputs; It is characterized by comprising a fifth selector that selects and outputs either the output of the optimum block length selection circuit or the output of the sudden fluctuation detection circuit according to the output of the sudden fluctuation detection circuit.

(Operation) The correlation between sample values of a signal is one of the parameters representing the characteristics of the signal, and signals with similar characteristics have similar correlations between signal sample values. This is also true for sample values taken from different blocks of the same signal. In other words, two sets of sample values that have inter-block correlation in the time domain have similar transformation coefficient distributions after linear transformation. Therefore, by monitoring the difference in time-domain sample values between adjacent blocks and adaptively selecting and using a block length that reduces the difference,
It is possible to satisfy the contradictory requirements of resolution in the conversion domain and ability to follow changes in the properties of the input signal as described above.

The adaptive transform encoding method and apparatus of the present invention can accommodate changes in resolution and properties of input signals by making the block length N variable using inter-block differences of normalized signals obtained by normalizing input signals. It is possible to improve the encoding quality by compressing the amount of auxiliary information while satisfying the conflicting demands of tracking the auxiliary information.

(Example) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, if the block length is specified, encoding is performed with the specified block length, and in other cases, the normalized signal obtained by normalizing the input signal is used to optimize the Determine the block length and perform encoding using the optimal block length. For this purpose, storage devices 25, 26, selectors 27, 28, 29, a difference detection circuit 36, and a block length designation signal input terminal 17 are provided.

When no input signal is supplied to the block length designation signal input terminal 17, the input signal supplied to the input terminal 1 is stored in the buffer 37, and then one block length candidate N,
The normalization circuit 2 uses the input signal to be normalized by the dispersion value. The normalized signal is stored in the storage device 25 and simultaneously supplied to the difference detection circuit 36. Further, the variance value used for normalization is stored in the storage device 26. Next, the samples equal to the second block length N2 are normalized in the same way as in the case of N, and the result is stored in the storage device 25.2.
6 and is supplied to the difference detection circuit 36. In the same manner as in the cases of N1 and N2 explained above, normalization using input signals is performed for the cases of multiple block lengths N3, N4%...Nn, and the corresponding normalized signals and variance values are stored in the memory circuit. 25 and 26, the normalized signal is also supplied to the difference detection circuit 36. However, normally N, <N2 × N3 × N4...<Nn, 2N.

"Ni+1 (1≦i<n). Block length N1,
When the calculation of the normalized signals for N2, N3, N4, . . . N is completed, the difference detection circuit 36 calculates the normalized signal yJ(N
i) The sum δ(N,) of the squared differences between blocks of the normalized signal is calculated for (j=1...N,) and the value zz(Ni) one block before the normalized signal. The optimal block length Nm is selected using δ(N, ) and is supplied to the selector 27. The selector 27 is also supplied with a block length selection signal. The selector 27 selects the block length selection signal when the block length selection signal is supplied, and otherwise selects the optimum block length NIn supplied from the difference detection circuit 36, and outputs the selected signal.

The output signal of the selector 27 causes the selectors 28 and 29 to
The normalized signal and auxiliary information corresponding to the optimal block length Nm are selected, and the normalized signal is sent to the linear transformation circuit 3, where the auxiliary information is the dispersion value of the input signal and the optimal block length Nm.
m are respectively supplied to the multiplexing circuit 15. The optimal block lengths N, , l may be quantized and then transmitted to the multiplexing circuit 15.

The optimum block length Nm is also supplied to the linear transformation circuit 3. In the linear transformation circuit 3, Nff one-point discrete linear transformation is performed using the optimum block length supplied from the selector 27, and the obtained transformation coefficients are supplied to the quantizer 4 and the bit allocation circuit 6. The bit allocation circuit 6 performs bit allocation using the transform coefficients supplied from the linear transform circuit 3, and the quantizer 4 uses the obtained bit allocation information to perform quantization of the transform coefficients supplied from the linear transform circuit 3. .

The quantized transform coefficients and the bit allocation information are multiplexed with the optimum block length Nm and the dispersion value of the input signal in the multiplexing circuit 15, and sent to the transmission line 8.

When an input signal is supplied to the block length designation signal input terminal 17, the selector 27 selects the supplied block length N, and sets it to the optimum block length Nm. Therefore, subsequent linear transformation and quantization are performed based on the supplied block length N. Next, referring to FIG. 2, an actual procedure for selecting an optimum block length will be described, taking as an example a case where an optimum block length is determined from n types of block lengths. Here, in order to simplify the explanation, it is assumed that n=3 (the optimum block length is selected from three different block lengths) as shown in FIG.

Let time 1=0 be the time when the encoder starts operating. At time N1T (sampling period from T4), the first
N1 input signal samples are stored in the buffer 37 shown. This state is shown in (A) of FIG. 2(a). The input signal sample labeled N1(1) in the figure, i.e. I
The hatched portion indicated by is normalized by the block length N1, and the normalized signal is stored in the storage device. At time N2T, samples equal to the second block length N2 (N1<N2) are accumulated in the buffer 37. This situation is shown in FIG. 2(a)-(B). At this time, the input signal sample indicated as N (2) in the same figure, that is, the hatched part indicated as ■, is normalized by the block length N, and further N2
(1) Normalization is performed on the input signal samples indicated as I, that is, the hatched portion indicated as I, and the hatched section indicated as ■, and the respective normalized and store the converted signal in a storage device. At time (N, 10N2) T, there are N, 10N2 in the buffer.
Samples equal to are accumulated. This situation is shown in Figure 2 (a
) is shown in (C). At this time, N 1 (3
), that is, the hatched portion indicated by ■, is normalized by the block length N1, and the normalized signal is stored in the storage device. Furthermore, at time N3T, samples equal to the third block length N3 (Nt<N2<N3) are accumulated in the buffer. This situation is shown in Figure 2 (a) (D).
Shown below. At this time, the input signal sample shown as N (4) in the same figure, that is, the hatched part marked with ■, is normalized by the block length N1, and is also shown as N2 (2). input signal samples,
In other words, the hatched portion marked with ■ and the hatched portion marked with ■ are normalized by the block length N2, and the input signal sample labeled N5(1), i.e. Block length N3 for the hatched parts indicated as ■, ■, ■, ■
The normalized signals are normalized according to the following, and each normalized signal is stored in a storage device. Hereinafter, N,(
i), normalized signals corresponding to N 1 (2), Nt (3), N 1 (4), normalized signals corresponding to N2 (1) and N 2 (2), and normalized signals corresponding to N5 (1). The inter-block differences δ(N1), δ(N2), δ(
N3) and determine the optimal block length NlTl.

The above processing procedure is summarized in FIG. 2(b). N
Taking the case of 5=2N2''4Nt as an example, the maximum block length N3 can be expressed by the four minimum block lengths N of 1, ■, ■, ■.Inputs of blocks I, II, ■, ■ Normalization using block length N1 for data is performed in blocks ■, ■, ■, and 《', respectively. Normalization using block length N2 for input data of blocks I+II and I+IV is performed for blocks ■ and ■'', respectively. It is done in a block. Furthermore, I+n+II[+
Normalization using the block length N3 for the input data of the block IV is performed in the block I'.

Therefore, for the block ■'', which has the largest amount of processing, normalization is performed using block length N1 for ■, normalization using block length N2 for ■10■, and block length N3 for I+■10■10■. It is necessary to perform normalization, calculate inter-block differences δ(N, ), δ(N2), and δ(N3) of the normalized signals, and determine the optimal block length Nm using these.

That is, it is assumed that the time required for all these processes is shorter than N1T.

As is clear from FIG. 2(b), the buffer 37 must have a capacity of at least N3T and is reset every N3T. A normal signal corresponding to the selected optimal block length is taken out from the storage device in N3 samples at a time, subjected to linear transformation in the linear transformation circuit 3, and then quantized in the quantizer 4 to form the transmission line shown in FIG. Sent on 8th. Therefore, transmission line 8
The data sent to N is as shown in Figure 2 (C).
The same block length continues in units of 3. Hereinafter, this block length will be referred to as a unit block. Next, the operation of the difference detection circuit 36 will be explained in detail with reference to FIG.

FIG. 3 shows details of the difference detection circuit 36. A signal supplied from the linear conversion circuit 3 in FIG. 1 is supplied to the input terminal 301, and a signal from the output terminal 314 is transmitted to the selector 27. The conversion coefficients supplied to input terminal 301 are input to switch 302, selector 304, and subtracter 305. Storage devices 3031, 3032, . . . , 303n are connected to each output terminal of the switch 302, respectively. Storage device 3031.3032,...
303. are block lengths N1, N2,..., Nn
It corresponds to the normalized signal z of l block before in 303.
j(Nt-t) (j=l...N,) is stored. The selector 304 selects these storage devices 3031
．． One of the outputs of 3032, . . . , 303n is selected and transmitted to the subtracter 306.

Both the switch 302 and the selector 304 are connected to the input terminal 30.
1. The output of the selector 304 is subtracted from the normalized signal supplied to the input terminal 301 by a subtracter 305, and the result is sent to a multiplier 306.
is supplied to That is, when a normalized signal corresponding to a certain block length N is supplied to the input terminal 301, the normalized signal one block before corresponding to N is selected by the selector 304, and the current signal supplied to the input terminal 301 is selected by the selector 304. A subtracter 305 subtracts it from the normalized signal of the block. At the same time, the current normalized signal is stored in storage device 303 . connected by switch 302 . is stored in Multiplier 306 is subtracter 3
The inter-block difference of the normalized signal supplied from 05 is squared. The previous operations are performed for each normalized signal sample. The obtained inter-block difference square value is stored in accumulator 3.
07, and the sum of the inter-block difference square values of the normalized signal samples for all normalized signal samples is determined. Hereinafter, this will simply be referred to as the inter-block difference of the normalized signal. The inter-block difference of the normalized signal, which is the output of the accumulator 307, is calculated for each unit block and stored in the storage device 30.
It is stored in 8.

Maximum value detection circuit 309 detects the maximum value of inter-block differences of transform coefficients corresponding to each block length candidate value for each unit block, and stores it in storage device 310. That is, for each unit block, the storage device 310 stores as many maximum inter-block differences of transform coefficients as there are block length candidate values.

The division circuit 316 uses these maximum values max Cδ (Nt)) supplied from the storage device 310 to calculate adjacent maximum values max (δ (Ni)) and max (δ (Ni, -
t)) ratio δR(i) = max(δ(N;-t))/
max(δ(Ni)) ・−・(3) as 1≦i≦n
-1 is calculated and stored in the storage device 315. ma
x (·) is the maximum value operator.

The optimal block length selection circuit 311 determines the optimal block length using these ratios δR(i) supplied from the storage device 315 and transmits it to the selector 313. The optimum block length selection circuit 311 searches for i giving m1n(δR(i)) for 1≦i<n−1, and determines the optimum block length N, 11 by setting m=i.

min (·) is the minimum value operator.

Furthermore, in parallel, a sudden change detection circuit 312 detects a sudden change in the input signal characteristics using the difference between transform coefficient blocks, and unconditionally selects the minimum block length when a sudden change is detected. This is performed by the selector 313 selecting a signal supplied to the selector 313 from the sudden change detection circuit 312 and transmitting the selected signal to the output terminal 314. A sudden change in the input signal characteristics is detected by comparing the values of δ(N,) obtained from the storage device 308. The storage device 308 stores N data for one unit block. /N1's δ(N,)
is stored, the ratios of all adjacent δ(N,), δ, )+1(Nt)/δpfit) and δp(Nt
)/δp+t(Nt) 1≦p N. /N, and if even one exceeds a predetermined threshold Th, it is determined that a sudden change has been detected. The threshold value Th is determined empirically.

(Effects of the Invention) As described in detail above, according to the present invention, the optimum block length is selected using the inter-block difference of normalized signals obtained by normalizing with different block lengths, and In order to transmit information by linearly converting and quantizing the corresponding normalized signal, it is possible to compress the amount of auxiliary information and improve the encoding quality while satisfying the conflicting demands of resolution and tracking changes in the properties of the input signal. An improved adaptive transform encoding method and apparatus can be provided.

[Brief explanation of drawings]

Figure 1 is a block diagram showing one embodiment of the present invention, Figure 2 is a diagram showing an example of the state of a buffer that stores input samples and the procedure for selecting the optimal block length, and Figure 3 is a difference between Figure 2. A block diagram showing details of the detection circuit, FIG. 4 is a block diagram showing a conventional example, and FIGS.
Fig. 6 shows another conventional example, Fig. 7 (a), (b)
7 is a diagram showing details of the normalization circuit and the denormalization circuit in FIG. 6. FIG. In the figure, 1.17.301 is an input terminal, 2 is a normalization circuit, 3 is a linear conversion circuit, 4 is a quantizer, 6 is a bit allocation circuit, 8 is a transmission line, 15 is a multiplexing circuit, 25.26 ．．
3034,..., 303n, 308.310.
315 is a storage device, 27.28.29.304.313
is a selector, 36 is a difference detection circuit, 37 is a buffer, 3
02 is a switch, 305 is a subtracter, 306 is a multiplier, 3
07 is an accumulator, 309 is a maximum value detection circuit, 316 is a divider, 311 is an optimum block length selection circuit, 312 is a sudden change detection circuit, and 16.314 is an output terminal. (2 Luojin dialect!=Shinaihara 2nd Figure N5 (1) (8) (b) (C) Figure (b) Figure 7

Claims (2)

[Claims] (1) When adaptively converting an input signal to compress and transmit/storage the information content of a signal such as voice/music, if a block length is specified, the specified block length is used. perform a linear transformation, otherwise accumulate the input signal samples in a buffer, normalize the input samples with multiple block lengths to obtain a normalized signal, and calculate the normalized signal corresponding to the multiple block lengths. Find the difference between blocks,
When the plurality of block lengths are arranged in order of size, an optimal block length is determined using the ratio of the inter-block differences corresponding to two adjacent block lengths and the inter-block difference, and the optimal block length is used. linearly transform the normalized signal, quantize the transform coefficient by a bit allocation calculated using the obtained transform coefficient, and supplement the bit allocation, the value used for the normalization, and the optimal block length. A method of adaptive transform encoding characterized in that information is transmitted/stored together with the quantized output. (2) a buffer that accumulates input samples; a normalization circuit that normalizes the samples accumulated in the buffer with a plurality of block lengths and outputs a normalized signal; and the normalized signal corresponding to the plurality of block lengths. a difference detection circuit that receives the signal and outputs an optimal block length using the inter-block difference of the normalized signal; and a difference detection circuit that receives the optimal block length supplied from the difference detection circuit and a block length designation signal supplied from the outside. The first selects the output according to the block length designation signal.
the first selector in response to the output of the normalization circuit;
a linear conversion circuit that performs linear conversion with a block length corresponding to the output of the selector; a bit allocation circuit that calculates bit allocation for the conversion coefficient obtained by the linear conversion circuit; and a bit allocation circuit that calculates the bit allocation obtained by the bit allocation circuit. a quantizer that quantizes the transform coefficient according to the method, and multiplexes and transmits/stores the output of the first selector, the output of the quantizer, the output of the bit allocation circuit, and the value used for the normalization. The difference detection circuit includes a multiplexing circuit, a switch that switches the input normalized signal according to a plurality of block lengths, a plurality of storage devices connected to the plurality of output terminals of the switch, and a plurality of storage devices connected to the plurality of output terminals of the switch; a fourth selector that selects one of the outputs of the storage device; a subtracter that subtracts the output of the fourth selector from the input normalized signal; and a multiplier that squares the output of the subtracter; an accumulator that accumulates the output of the multiplier;
a third storage device that stores the output of the accumulator; a maximum value detection circuit that determines a maximum value from a plurality of outputs of the third storage device; and a fourth storage device that stores the output of the maximum value detection circuit. a storage device, a divider that calculates the ratio of two data among the plurality of outputs of the fourth storage device, a fifth storage device that stores the output of the divider; an optimal block length selection circuit that determines an optimal block length using the output; an abrupt change detection circuit that receives a plurality of outputs from the third storage device and detects a significant change between the plurality of outputs; Adaptive transform coding characterized by comprising a fifth selector that selects and outputs either the output of the optimum block length selection circuit or the output of the sudden fluctuation detection circuit according to the output of the fluctuation detection circuit. Device.