JPH03180037A - Manufacture of quantum thin wire - Google Patents
Manufacture of quantum thin wireInfo
- Publication number
- JPH03180037A JPH03180037A JP31787389A JP31787389A JPH03180037A JP H03180037 A JPH03180037 A JP H03180037A JP 31787389 A JP31787389 A JP 31787389A JP 31787389 A JP31787389 A JP 31787389A JP H03180037 A JPH03180037 A JP H03180037A
- Authority
- JP
- Japan
- Prior art keywords
- quantum
- etching
- thin wire
- quantum well
- fluctuation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000609 electron-beam lithography Methods 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 19
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 7
- 238000001459 lithography Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000003486 chemical etching Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 2
- 238000003754 machining Methods 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、光デバイスおよび電子デバイス等に適用可能
な一次元量子細線構造の製作方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a one-dimensional quantum wire structure applicable to optical devices, electronic devices, and the like.
(従来の技術)
近年、一次元量子細線構造の製作手段として、いくつか
の方法が提案され、また試行されている。(Prior Art) In recent years, several methods have been proposed and tried as means for producing one-dimensional quantum wire structures.
特に、量子井戸構造に電子ビーム露光を用いて加工を施
して量子細線を形成する方法が、近年リソグラフィ技術
の進歩に伴い勢力的に研究されている。この方法は、分
子線エピタキシャル成長法などを用いて製作した、半導
体の量子井戸構造の上に、電子ビーム露光によって線幅
300人程度のレジストのストライプパターンを形威し
、これを反応性イオンエツチング等を用いて量子井戸構
造に転写することによって量子細線を形成するものであ
る。In particular, methods of forming quantum wires by processing quantum well structures using electron beam exposure have been intensively researched in recent years as lithography technology has progressed. In this method, a resist stripe pattern with a line width of approximately 300 mm is formed by electron beam exposure on a quantum well structure of a semiconductor fabricated using molecular beam epitaxial growth, etc., and this is etched by reactive ion etching, etc. Quantum wires are formed by transferring them onto a quantum well structure.
しかし、前記の方法では、電子ビーム露光によって、形
成されるレジストパターンの線幅に揺らぎが生じること
、加工限界が現段階では300人程度であること、また
レジストパターンを量子井戸に転写する際に、量子井戸
構造に損傷が加わることなどが問題となっていた。However, with the above method, fluctuations occur in the line width of the resist pattern formed due to electron beam exposure, the processing limit is currently about 300 people, and there are problems when transferring the resist pattern to the quantum well. , damage to the quantum well structure was a problem.
(発明が解決しようとする課題)
本発明は、レジストパターンを量子井戸構造に転写する
際に、線幅の揺らぎを減少させ、かつ電子ビーム露光に
よって形成させるレジストパターンよりも細い量子細線
を、損傷を低く抑えて製作する量子細線の製作方法を提
供することにある。(Problems to be Solved by the Invention) The present invention reduces fluctuations in line width when transferring a resist pattern to a quantum well structure, and prevents damage to quantum wires that are thinner than the resist pattern formed by electron beam exposure. It is an object of the present invention to provide a method for manufacturing quantum wires that can be manufactured while keeping the amount of wires low.
(課題を解決するための手段)
本発明の量子細線の製作方法は、レジストパターンを量
子井戸に転写する方法として、従来用いられていた反応
性イオンエツチング等のようなドライエツチングの代わ
りに異方性を有する化学エッチャントを用いて、逆メサ
エツチングを行うという方法をとる。異方性化学エツチ
ングを用いることにより、レジストのパターンを縮小し
て量子井戸構造に転写することが可能となり、かつその
際に逆メサ形状に現れた面取外の方位を持つレジストパ
ターンの揺らぎを減少させることができ、また加工の際
の損傷を少なく抑えることができる。(Means for Solving the Problems) The quantum wire manufacturing method of the present invention uses anisotropic etching instead of conventionally used dry etching such as reactive ion etching as a method for transferring a resist pattern to a quantum well. The method is to perform reverse mesa etching using a chemical etchant that has properties. By using anisotropic chemical etching, it is possible to reduce the resist pattern and transfer it to the quantum well structure, and at the same time, it is possible to reduce the fluctuation of the resist pattern with an orientation outside the chamfer that appears in the inverted mesa shape. It is also possible to reduce damage during processing.
(実施例)
以下図面を用いて本発明の量子細線の製作方法について
詳細に説明する。第1図は、本発明の一実施例における
量子細線の製作手順を示す。まず、分子線エピタキシー
法などの原子層オーダの膜厚制御可能な薄膜成長法を用
いて、第1図(a)に示すように、(100) InP
基板基板上にInPバッファ層2、InGaAs量子井
戸層3、InPキ+7プ層4の順に成長する。次に電子
ビームリソグラフィなどの方法を用いて、第1図(b)
に示すように、<011>方向にレジストストライプパ
ターンを形成する。その後に、化学エツチングを用いて
、第1図(C)に示すように、InPキャップ層4およ
びInGaAsfi子井戸層3を逆メサエツチングする
。第1図(C)のエツチングの際には、サイドエツチン
グが問題となるので、誘電体マスク(窒化珪素膜など)
に転写してからInPキャップ層4をエツチングする方
法や、半導体極薄膜(上記の場合ではInGaAs薄膜
)に転写してから選択エツチング液を用いてInPキャ
ップ層4をエツチングする方法(参考文献: H,Te
mkinet al、^pplied Physics
Letters、 vol、52+ page147
8 (1988) )が有効である。(Example) The method for manufacturing a quantum wire of the present invention will be explained in detail below using the drawings. FIG. 1 shows a procedure for manufacturing a quantum wire in an embodiment of the present invention. First, as shown in FIG. 1(a), (100) InP was grown using a thin film growth method that allows film thickness control on the order of atomic layers, such as molecular beam epitaxy.
An InP buffer layer 2, an InGaAs quantum well layer 3, and an InP cap layer 4 are grown in this order on a substrate. Next, using a method such as electron beam lithography, the image shown in FIG. 1(b) is
As shown in , a resist stripe pattern is formed in the <011> direction. Thereafter, the InP cap layer 4 and the InGaAsfi child well layer 3 are subjected to reverse mesa etching using chemical etching, as shown in FIG. 1(C). During the etching shown in FIG. 1(C), side etching becomes a problem, so a dielectric mask (such as a silicon nitride film) is used.
A method in which the InP cap layer 4 is etched after being transferred to a semiconductor film (InGaAs thin film in the above case), or a method in which the InP cap layer 4 is etched using a selective etching solution after being transferred to an ultra-thin semiconductor film (InGaAs thin film in the above case) (Reference: H ,Te
mkinet al,^pplied Physics
Letters, vol, 52+ page 147
8 (1988)) is valid.
この時、逆メサエツチングの際に現れる面が、(111
)面の場合、メサ斜面の角度は、第2図に示すように、
54.74度になる。従って、レジストストライプの幅
が500人でInPキャップ層4の膜厚が200Åだと
すると、できるInGaAs量子細線の幅は200Å程
度になる。製作される量子細線の幅は、現れる逆メサ面
の面方位およびInPキャンプ層4の膜厚によって制御
することが可能であり、電子ビーム露光によるレジスト
パターンのサイズによって制限されない。At this time, the surface that appears during reverse mesa etching is (111
) surface, the angle of the mesa slope is as shown in Figure 2.
It becomes 54.74 degrees. Therefore, if the width of the resist stripe is 500 and the thickness of the InP cap layer 4 is 200 Å, the width of the resulting InGaAs quantum wire will be about 200 Å. The width of the produced quantum wire can be controlled by the plane orientation of the appearing reverse mesa plane and the film thickness of the InP camp layer 4, and is not limited by the size of the resist pattern formed by electron beam exposure.
また第3図に示すように、レジストストライプパターン
が、ある揺らぎを持っていたとすると、(111)面取
外の方向を持った揺らぎに対してはエツチングが速く進
行するので、エツチングが進むに従ってリソグラフィの
揺らぎが減少する。理想的な異方性エツチングが行われ
ると、はじめのりソグラフィによるレジストパターンが
<O1b方向に対して揺らぎを持っていたとしても、逆
メサエツチングによって現れる面は、厳密に(111)
面のみになるので、レジストパターンの描らぎは消える
。Furthermore, as shown in FIG. 3, if the resist stripe pattern has a certain fluctuation, etching progresses quickly for fluctuations in a direction other than (111) chamfering, so as the etching progresses, the lithography fluctuation is reduced. When ideal anisotropic etching is performed, even if the resist pattern formed by the initial lithography has fluctuations in the <O1b direction, the surface that appears by reverse mesa etching will be strictly (111).
Since only the surface is covered, the gaps in the resist pattern disappear.
以上の実施例においては、(100)基板上の<011
>方向のストライプを利用して、(111)面のファセ
ットが現れる場合について説明したが、本発明はエツチ
ングにおいて逆メサの現れる場合一般に適用可能である
。例えば、(111)基板を用いる場合、(411)面
など高次のファセット面が現れる場合などにも、上記の
説明はそのまま当てはまる。In the above embodiment, <011 on the (100) substrate
Although the case where (111) facets appear using stripes in the > direction has been described, the present invention is generally applicable to cases where inverted mesas appear in etching. For example, when using a (111) substrate, the above explanation also applies when a high-order facet surface such as a (411) plane appears.
また以上の実施例においては、InGaAs / In
P系の材料において述べたが、GaAs /^1GaA
s系やInGaAs/1nAIAs系などの材料におい
ても可能である。Furthermore, in the above embodiments, InGaAs/In
As mentioned in P-based materials, GaAs /^1GaA
This is also possible with materials such as s-based and InGaAs/1nAIAs-based materials.
(発明の効果)
本発明の量子細線の製作方法によれば、電子ビーム露光
などのりソグラフィ技術に制限されない細い量子細線が
、加工による損傷を受けることなく製作可能であり、ま
た同時にリソグラフィによるストライプの揺らぎを、逆
メサエツチングの特性により消すことができる。従って
、本発明の方法により、大きな量子効果の期待できる極
小サイズで、かつサイズ揺らぎの少ない量子細線を製作
することができる。(Effects of the Invention) According to the method for manufacturing quantum wires of the present invention, thin quantum wires that are not limited to lithography techniques such as electron beam exposure can be manufactured without being damaged by processing, and at the same time, stripes can be formed by lithography. Fluctuations can be eliminated by the characteristics of reverse mesa etching. Therefore, by the method of the present invention, it is possible to produce a quantum wire of extremely small size and with little size fluctuation, which can be expected to have a large quantum effect.
第1図(a)、 (b)、 (C)は本発明の実施例に
おける量子細線の製作手順を示す図、
第2図は製作される量子細線のサイズを説明するための
図、
第3図は本発明の方法により、リソグラフィパターンの
揺らぎが消える機構を説明する模式図である。
l・・・InP基板 2・・・InPnシバ9
フフ
5・・・レジストFIGS. 1(a), (b), and (C) are diagrams showing the steps for manufacturing a quantum wire in an embodiment of the present invention. FIG. 2 is a diagram for explaining the size of the quantum wire to be manufactured. The figure is a schematic diagram illustrating a mechanism in which fluctuations in a lithography pattern disappear by the method of the present invention. l...InP substrate 2...InPn substrate 9
Fufu 5...Resist
Claims (1)
に、電子ビームもしくは光リソグラフにより微細加工を
施して量子細線を製作する方法において、該量子井戸構
造の加工を結晶面方位依存性を有するエッチング液を用
いて行い、かつ逆メサ構造が出現する方位にリソグラフ
パターンを形成することにより、リソグラフパターンよ
り寸法が小さく、かつリソグラフパターンよりもサイズ
揺らぎの小さな細線を製作可能とする量子細線の製作方
法。1. In a method of fabricating quantum wires by subjecting a semiconductor single quantum well structure or multiple quantum well structure to fine processing using an electron beam or optical lithography, the processing of the quantum well structure is performed using an etching solution that has crystal plane orientation dependence. A method for producing a quantum thin wire that is smaller in size than a lithographic pattern and has smaller size fluctuation than a lithographic pattern by forming a lithographic pattern in a direction in which an inverted mesa structure appears.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31787389A JPH03180037A (en) | 1989-12-08 | 1989-12-08 | Manufacture of quantum thin wire |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31787389A JPH03180037A (en) | 1989-12-08 | 1989-12-08 | Manufacture of quantum thin wire |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03180037A true JPH03180037A (en) | 1991-08-06 |
Family
ID=18093013
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31787389A Pending JPH03180037A (en) | 1989-12-08 | 1989-12-08 | Manufacture of quantum thin wire |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03180037A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100485498B1 (en) * | 2002-11-29 | 2005-04-28 | 한국과학기술원 | Fabrication method for a quantum wire on the quantum wire FETs |
-
1989
- 1989-12-08 JP JP31787389A patent/JPH03180037A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100485498B1 (en) * | 2002-11-29 | 2005-04-28 | 한국과학기술원 | Fabrication method for a quantum wire on the quantum wire FETs |
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