JPH03179573A - Picture storage - Google Patents

Abstract

PURPOSE:To take out the continuous picture element data on a specific row or column in a short period by dividing a two-dimensional picture address space by an n-row X n-column picture element matrix and storing the picture element data on each divided block into each memory part. CONSTITUTION:A block address, a picture element address, an X/Y switch flag, etc., are supplied to an address control part 6. Based on these supplied signals, an address of a picture memory 2 is designated and at the same time the circuits are switched at a data input part 1 and a data output part 4 respectively. Then the memory parts 3a, 3b,... form a memory bank, and the picture element data are produced for each row or column of a block in a two-dimensional picture address space as shown in a diagram. When the picture element data are taken out, the picture element data are read out of those memory parts in a block unit (16 bytes). Then the continuous picture element signals of a specific row or column are selectively taken out of a block by means of the picture element address and the X/Y switch flag.

Description

[Detailed Description of the Invention] [Summary] Regarding an image storage device, for the purpose of speeding up image processing, an image space represented by two-dimensional addresses is divided into n rows and n columns (n is an integer of 2 or more). means for dividing into a pixel matrix of the image space, and creating a block address for each divided block using the upper bits of the two-dimensional address, and writing or reading pixel data in the image space in units of blocks using the block address. and a memory capable of writing write pixel data to the n row x n column memory when writing access to the memory is performed.
means for assembling Ux in rows or columns and writing in rows or columns to a predetermined area of the memory using the block address; means for selectively extracting pixel data in units of rows or columns.

[Industrial application field]

The present invention relates to an image storage device, and particularly to an image storage device used in an image control device that requires processing of a large amount of data.

[Conventional technology]

Generally, when reading an image signal from the memory of an image storage device (image memory), unlike the memory of a computer, reading/writing must be performed not only in the increasing direction of addresses but also in the decreasing direction. Furthermore, since a large amount of data is to be processed, high-speed address selection is also required. Conventionally, speeding up has been attempted by widening the bus width in the direction of increasing addresses. However, as shown in Figure 7,
An image memory corresponding to, for example, the pixel address (0, 1° 2.3) in the X direction for the pixel in the 1st row in a two-dimensional image address space consisting of a pixel matrix of k rows x m columns (k, m are integers). The addresses (0, 1, 2, 3) are continuous, but for example, the image memory address (0, m , 2m, 3m) are not continuous.

Therefore, the access speed when retrieving pixel data from the image memory is fast in the X direction, but much slower in the Y direction.

[Problem to be solved by the invention]

As described above, in the conventional image memory, the access speed to the Y-direction address in the two-dimensional image address space is extremely slow, which is a bottleneck in increasing the speed of image processing. Therefore, in the present invention, the image space is divided into a pixel matrix of n rows by n columns (n is an integer of 2 or more), a block address is created for each divided block, and this block address is used to divide the image space. An image in which pixel data is written to an image memory in blocks, and when pixel data is retrieved, it is first read out from the image memory in blocks, and then pixel data in predetermined rows or columns are selectively retrieved from this read data. It is an object of the present invention to provide a storage device and increase the access speed to Y-direction addresses in a two-dimensional image address space, thereby speeding up image processing.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. Also, Figure 2 shows 2
FIG. 2 is an explanatory diagram showing the blocking and address structure of the present invention in a dimensional image address space, and is an explanatory diagram showing the blocking and address structure of the present invention in a dimensional image address space,
X of each block (A, B, C...) consisting of bytes)
Block address (
upper bits), and the X direction and Y direction of each pixel in the block
The address has a pixel address (lower two bits) indicating the position in each direction.

In FIG. 1, 1 is a data input unit which packs, for example, 1 byte of pixel data into 4 bytes (4 pieces) of pixel data, and uses the packed pixel data as a block address which is an output signal of the address control unit 6. etc., is written to the memory unit 3 according to the following.

Reference numeral 2 denotes an image memory, which has a plurality of memory sections 3.

3 is a memory unit, for example, 4 in each direction of the X direction and the Y direction.
It is constructed by arranging memory elements two-dimensionally, and
Stores the pixel data (16 bytes) of the ■ block in the dimensional image address space.

4 is a data output unit that reads pixel data (16 bytes) in units of blocks stored in the memory unit 3, and selectively outputs pixel data in units of predetermined rows or columns from this read data through subsequent processing. I'm taking it out.

Reference numeral 5 denotes an input/output control section which controls the operations of the data manual section 1 and the data output B4.

6 is an address control unit to which block addresses, pixel addresses, X/Y switching flags, etc. are supplied. and,
These signals specify the address of the image memory 2, and also switch the circuits of the data input section 1 and the data output section 4, respectively.

Here, each memory section 3a, 3b, . . . constitutes a memory bank, and pixel data in the two-dimensional image address space shown in FIG. 4 pieces) are written in sequence. When taking out pixel data, the pixel data is read out in blocks (16 bytes) from the memory section, and then a specific row or column in the block is selected using the pixel address and the X/Y switching flag. Continuous pixel signals are selectively extracted. For example, one of each block in the two-dimensional image address space in FIG.
In order to extract continuous pixel signals in the row, at least Y
It is necessary to select (00) as the direction address.

[Effect]

As mentioned above, the two-dimensional image address space is defined as n rows x n columns (
The pixel matrix (n is an integer of 2 or more) is divided, and the divided pixel data in units of blocks is stored in each memory section. On the other hand, since one block consists of a small number of pixels, continuous pixel data in a specific row or column within the block can be selectively retrieved from the pixel data stored in each memory section in a short time. be able to.

Note that the image memory 2 is simply for storing all the pixel data of a certain block in the two-dimensional image address space, and therefore does not need to be a physical memory with two-dimensional addresses as shown in FIG. Further, it is not necessary to match the address order of the image memory 2 with the pixel address order in the two-dimensional image space.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIGS. 3 to 6. In the following description, the configuration of the image memory is assumed to be such that the contents of the image memory 2 shown in FIG. 1, that is, the address order of the image memory and the pixel address order of the two-dimensional image space match.

FIG. 3 is an explanatory diagram of the operation when writing pixel data in the two-dimensional image address space to the image memory.

That is, for example, each byte of pixel data 21 supplied via a serial line is sequentially written into the first buffer 22 by the distribution pulse 27, and assembled into data for each row or column of the block (in units of 4 bytes). ), then multiplexer 23
is supplied to Here, the distribution pulse 27 is a signal from the address increment/decrement counter, and the pixel data 21 [a,
When writing b, c, dl in the direction of decreasing pixel address, the pixel data 21 [a, b, c, dl
The operation order of the distribution pulses 27 for each of them is reversed and the states [d, c, b, a] are written into the first buffer 22. On the other hand, the multiplexer 23 has an X/Y
It is switched by the direction switching flag 29 and the pixel address 28 (lower 2 bits), and when writing in the X direction of the memory section (memory sections 3a, 3b, . . . , hereinafter referred to as 3 in FIG. 1), each of the multiplexers 23 Group (23
-1) to (23-4) operate one by one, and the pixel data 21 [a, b, c, dl are transferred to the second buffer 24
．． The data is written to the first row (X direction) of the memory element 26 of the memory unit 3 via the third buffer 25 as shown in the figure, and when writing to the Y direction of the memory unit 3, the multiplexer group (23-1 ) to (23-4>) operates, and the pixel data 21 [a, e, i
, m] are stored in the second buffer 24 . The data is written to the first column (Y direction) of the memory element 26 via the third buffer 25 as shown. Here, for example, which 4 bytes of the 16 bytes to write to is selected by the pixel address 28 (lower 2 bits). Then, by repeating such a write operation in either the X direction or the Y direction, pixel data in the two-dimensional image address space can be stored in the memory unit 3 in units of blocks.

FIG. 4 is an explanatory diagram showing a time chart of the above writing operation (in the X direction). That is, the pixel data 21 (a, b
, c, d) are transferred to the buffers y24 and 25, and written into the memory section 3 by the write control signal.

Note that the pixel data 21 (a, b, c, d)
is transferred to the buffer 25, the buffer 24 contains the pixel data 21 (a, b, c,
d) is being transferred. FIG. 5 is an explanatory diagram of operations when pixel data in units of predetermined rows or columns are selectively extracted from pixel data in units of blocks written in the memory. That is, one block (16 bytes) of pixel data read simultaneously from the memory section 3 is transferred to a buffer 41, 42, and a multiplexer group 43 for extracting pixel data in the row direction in units of 4 bytes.
The signal is supplied to each multiplexer group 44 for taking out pixel data in the column direction in 4-byte units as shown. Each of the multiplexer groups 43 is switched by the pixel address 48 (lower 2 bits) in the Y direction, and pixel data of a specific row, for example [a
, b, c, and dl are sent to the multiplexer 45. Further, each of the multiplexer groups 44 is switched by the pixel address 49 (lower 2 bits) in the X direction to select pixel data of a specific column, e.g.
] to multiplexer 46. Each multiplexer 45
．． 46 is switched by a distribution pulse 50 of an address increment/decrement counter that specifies whether to take out the pixel data in units of 4 bytes in the increasing direction of the pixel address or in the decreasing direction of 1 pixel address, and the output side of the multiplexer is ( (When extracting in the increasing direction of address) [a, b, c, dl, [a, e, i,
m] pixel data is obtained. Then, this pixel data is sent to the multiplexer 47, where the X/Y direction switching flag 51 selects the pixel data in one of the row and one column directions (in the case shown, the pixel data in the row direction [a, b, c,
dl> is taken out as an output signal 52.

FIG. 6 is an explanatory diagram showing a time chart of the above pixel data extraction operation (in the row direction).

That is, the read control signal 55 causes the memory section 3 to
The pixel data 40 of block A (16 bytes) read simultaneously from the buffer 41.42 is transferred to the buffer 41.42, and the pixel signals of a specific row (X direction), for example, [a, b, c, dl, are , and then the pixel signals of the same row of the next block are taken out as the output signal 52.

〔Effect of the invention〕

The present invention divides a two-dimensional image address space into a pixel matrix of n rows by n columns (n is an integer of 2 or more), creates a block address for each divided block, and
Using this block address, pixel data in the image space is written to the image memory in blocks, and when retrieving pixel data, it is first read out from the image memory in blocks, and then simple data in a predetermined row or column is extracted from this read data. Since the configuration is such that selective extraction is performed, the X direction of the two-dimensional image address space.

It is possible to speed up access to pixel signals in any direction in the Y direction, and it is possible to speed up image processing.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram showing the blocking and address structure of the present invention in a two-dimensional image address space, and Fig. 3 is an explanation of the operation when writing pixel data to the image memory. 4 is an explanatory diagram showing a time chart of the write operation in FIG. 3, FIG. 5 is an explanatory diagram of the operation when pixel data is taken out from the image memory, and FIG.
1! FIG. 7 is an explanatory diagram showing a time chart of an operation for taking l. FIG. 7 is an explanatory diagram showing the relationship between addresses of a conventional image memory and pixel addresses in a two-dimensional image address space. In FIG. 1, l...Data input section 2...Image memory 3...Memory section, data output section, input/output control section, address control section

Claims (2)

[Claims] (1) The image space represented by the two-dimensional address is divided into n rows x
means for dividing into a pixel matrix of n columns (n is an integer of 2 or more) and creating a block address using the upper bits of the two-dimensional address for each divided block; A memory capable of writing or reading pixel data in block units; and a memory for selectively extracting pixel data in predetermined row or column units from the block unit pixel data read from the memory at the time of read access to the memory. An image storage device comprising: means. (2) The image space represented by the two-dimensional address is divided into n rows
means for dividing into a pixel matrix of n columns (n is an integer of 2 or more) and creating a block address using the upper bits of the two-dimensional address for each divided block; A memory in which pixel data can be written or read in blocks, and when the memory is accessed for write, the write pixel data is assembled in rows or columns of the n-row by n-column matrix, and the memory is read out according to the block address. An image storage device comprising: means for writing data into a predetermined area in units of rows or columns.