JPH03178169A - Field-effect transistor having plurality of inputs - Google Patents

Abstract

PURPOSE:To reduce a necessary chip area by individually leading out input terminals from each of the gate parts of a gate, and applying one power supply potential to an isolation part of the gate, and applying the other power supply potential to a substrate region. CONSTITUTION:Only one polycrystalline silicon gate is arranged as a gate 5 and subjected to local doping, thereby dividing the inside into a plurality of gate parts with an isolation part 5i. Said parts are utilized as independent gates of a circuit. For the purpose of the above, a plurality of parts in the polycrystalline silicon gate 5 are doped with a conductivity type, and turned into each gate part, the residual parts are left in an undoped state, or doped with the opposite conductivity type, thereby forming the isolation part 5i isolating the gate parts from each other. One power supply potential V is applied to the isolation part 5i, and the other power supply potential E is applied to a substrate region 2. Thereby one gate only is required for a field-effect transistor having a plurality of inputs, so that the necessary chip area can be reduced by at least 30%.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS or MIS having a plurality of input terminals.
A transistor in the form of a CMO5 in the form of a logic gate.
The present invention relates to multiple input field effect transistors suitable for incorporation into integrated circuits.

[Conventional technology]

Since the input impedance of a field effect transistor's gate is extremely high, conventional multi-input field effect transistors have been created in which multiple gates each receiving an input are built in to function as logic gates that form the bottom of an integrated circuit. known from.

Fig. 2 shows a conventional example of this type of field effect transistor with two insulated gates. Fig. 2 (a) shows an n-channel type field effect transistor, and Fig. 2 (b) shows a p-channel type multi-input field effect transistor. FIG. 2 is a cross-sectional view of a transistor.

In this example, the reference numeral 1 in the figure is an n-type substrate or an epitaxial layer grown on it, and in the p-channel type shown in (c) of the same figure, this is the substrate! In the same figure (in Kawa's n-channel type, a p-type well 2 is used as a substrate region for diffusion from the surface of the substrate 1). A thin gate oxide film 4 is applied within the area covered with the gate oxide, and two gates 5 made of polycrystalline silicon or the like are provided thereon in this example.

Next, by ion implantation using these gates 5 as a mask as usual, a pair of source/drain layers 8 and an intermediate source/drain layer 81 are formed as n-type in the narrow channel type shown in FIG. The p-channel type in the same figure (b) has a pair of sources.
The drain layer 6 and the intermediate source/drain layer 6i@p type are diffused, and at the same time, the substrate connection layers 7 and 9 are
It diffuses into the channel type as P type and the p channel type as n type.

After that, by covering the whole with the glabella insulating film 10 and providing a connection 1ull in the window opened therein, the source terminal S and the drain terminal are connected from the source/drain layer, and the input terminal 511 is connected from the two gates 5. and Si2 are derived, respectively.

The n-channel field effect transistor of FIG. 2(a) configured as described above becomes conductive between its source and drain only when an input signal of h is applied to the re-input terminals Sll and S12, so it can be used as a Nandt gate. Available, same figure (b)
The P-channel type of can be used as a NOR gate because it becomes conductive only when input signals of ~ are applied to both re-input terminals.

These n-channel and P-channel field effect transistors each having two gates are equivalent to two transistors connected in series on the circuit, and the above-mentioned intermediate source/drain layers 61 to 81 are located on the left side of the figure. It functions as a drain layer for the transistor on the right side, and as a source layer for the transistor on the right side, and serves to interconnect the channels on both sides.The number of gates in each field effect transistor is 2. In principle, it is possible to have more than one child.

[Problem to be solved by the invention]

In this way, conventional multiple-input field effect transistors connect the lower channels of multiple gates in series via intermediate source/drain layers, so it is more efficient than connecting multiple regular field effect transistors in series. In principle, it should be possible to save chip area, but the actual saving effect is not very high.

This is because the gate area occupies a fairly large proportion of the chip area required to fabricate a field effect transistor.

Of course, even in the conventional structure, the transistors on both sides are interconnected by the intermediate source/drain layer, so the chip area can be saved by eliminating the need for a connecting film, but this savings is small compared to the gate area, so the overall required chip The rate of decrease in area is very small, and the effectiveness is not very high.

SUMMARY OF THE INVENTION An object of the present invention is to enable a multi-input field effect transistor to be fabricated within a smaller chip area than before.

[Means to solve the problem]

According to the invention, this purpose is achieved by providing a single gate of polycrystalline silicon for a multi-input field effect transistor;
A plurality of gate portions doped with one conductivity type are provided in the gate with separating portions that are undoped or doped with the other conductivity type, and input terminals are individually connected from each gate portion of the gate. This is achieved by applying one t# potential to the isolated portion of the gate and the other power supply potential to the substrate region.

[Effect]

The present invention focuses on the fact that reducing the gate area is most effective in saving the required chip area of a multi-input field effect transistor. By applying this, the interior is divided into a plurality of gate parts by the separation part, and these can be used as independent gates on the circuit. For this reason, in the present invention, as described in the above structure, a plurality of portions within a polycrystalline silicon gate are doped with one conductivity type to serve as gate portions, and the remaining area remains undoped, or the other conductivity type is doped. The doping is done in the form of an isolating portion that separates the gate portions from each other.

However, this alone does not have the function of connecting channels in series, which the conventional intermediate source/drain layer had, so as in the above configuration, one power supply potential is applied to the separated part, and the other power supply potential is applied to the substrate region. by giving each
This function is provided in the substrate region below each separation part.

That is, in the conventional method, a 1iB voltage is applied to the separated portion of the gate in the substrate 6i region, a channel is formed on the surface of the substrate 6i region by electrostatic induction, and the channels on both sides are interconnected to this induced channel. It can serve as an intermediate source/drain layer.

Note that from the functional point of view of channel connection on the surface of the substrate region 9M under the separation portion, it is advantageous for the gate portion to have the same conductivity as the substrate region for the following reasons.

A diode is formed between the gate portion of one conductivity type and the undoped or isolated portion of the other conductivity type. By the way, when multiple input field effect transistors are used as logic gates, it is common practice to turn on all the channels under the multiple gate parts to prepare the gate opening conditions, so that a human input signal to a certain gate part can be used to open the logic gate. When placed in a logic state, the diode conducts in the forward direction from this gate portion to the adjacent isolation portion if its conductivity is the same as that of the substrate region.

This further strengthens the channel connection function of the surface of the substrate region under the isolation part, and even if the input signal to another gate part adjacent to this isolation part is in a logic state that closes the logic gate, The diode is reverse biased to prevent potentials corresponding to the logic state that closes the logic gate from adversely affecting this isolation.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to FIG. Figures (a) and 2) respectively show n-channel type and P-channel type multi-power field effect transistors according to the present invention in a form corresponding to Figure 2, and parts corresponding to Figure 2 are denoted by the same reference numerals. is attached. (C) and (
A) is an example of a circuit to which these field effect transistors are applied.

As shown in the figure, the only difference from the conventional method is the structure of the gate 5, and the rest is the same. The same figure is considered to be the substrate a region (
The p-type well 2 shown in a) and the n-type semiconductor region M region 1 shown in FIG.

A polycrystalline silicon film for the gate 5 is formed on the gate oxide film 4, which is formed on the semiconductor region 1 or the well 2 to a thickness of 0.05 to 0.10, by a normal thermal CVD method or the like.
The gate layer is grown to a thickness of about 0.5 mm, and impurities are locally introduced therein by, for example, ion implantation, followed by high-temperature heat treatment, and then formed into a predetermined gate pattern. As a result, in the gate 5, there is a gate portion 5p doped to the same p-type as the well 2, which is the substrate region, in the channel type shown in FIG. In this embodiment, two n-type gate portions 5n, which are the same as those of the semiconductor region 1 which is the substrate 6i region, are formed, and the non-doped portions are used as isolation portions 51.

Note that, as described above, this isolation portion 51 may be doped to be n-type for an n-channel type and p-type for a p-channel type. In any case, in the case of FIG. 1(a), from the gate portion 5p In the case of the isolation portion 51 (in the figure), diodes that conduct in the direction from the isolation portion 5I to the gate portion 5n are built in the gate 5.

Also, as in the prior art, an n-type source layer 8s and a drain layer 8d are used for the n-channel field effect transistor shown in FIG. 1(a).
and a p-type substrate connection layer 7.

For the p-channel field effect transistor in the same figure (b), p
A type source layer 6s, a drain layer 6d, and an n type substrate connection layer 8 are each formed with a high impurity concentration of 10!0 atoms/cj or more. The glabella insulating film IO and the connecting film 11 are also the same as in the conventional case.

In the n-channel type two-power field effect transistor of FIG. In this example, one power supply potential V, which is a positive potential, is applied. The well 2 as a substrate region is placed at the other power supply potential, which is the ground potential in this example, via the source 118g and the source terminal S led out from the substrate connection layer 7. drain layer 8
A drain terminal is derived from d. FIG. 1C shows an example of a circuit in which this two-power field effect transistor is used as a Nandt gate.

The two-power field effect transistor shown in FIG. 1(C) has its drain terminal connected to the power supply potential ■ via a resistor R,
As can be easily seen, the two input terminals 511 and S12
The output signal S derived from its drain terminal is turned on only when the input signals to both are in the logic state h.
It serves as a Nant gate that puts o into the logical state of t.

In the P-channel type two-power field effect transistor shown in FIG. E is the substrate 8! A power supply potential (■) is applied to each of the semiconductor regions 1, which are regions. In the corresponding applied circuit example shown in FIG. 1(d), the two-power field effect transistor has a resistor R at its drain terminal.
is connected to the ground potential E through two input terminals 511.
It turns on only when the input signals to and 512 are both in the logic state t, and serves as a NOR gate that brings the output signal So derived from its drain terminal to the logic state h.

In place of the above-mentioned resistor R, in the circuit of FIG. 1(C), a p-channel type two-power field effect transistor as shown in FIG. 1(b) is used, and in the circuit of FIG. Normal commercial by connecting two human-powered field effect transistors
It can be an O3 circuit.

In addition, only one of the input signals to the two input terminals Sll and 512 is in a logic state in which the logic gate is opened, that is, in FIG.
In Figure 11), when in state b, the diode built into the gate 5 is directed from the p-type gate portion 5p to the isolation portion 5i in Figure (a).

In the same figure (b), from the separation part 51 to the n-type gate part 5n
The substrate 8! of the separated portion 51 is electrically connected to the substrate 8! The channel induction effect on the surface of the region is further strengthened, and the diodes between other gate portions adjacent to the isolation portion 51 are placed in a reverse bias state, thereby preventing the potential of such gate portions from affecting the isolation portion. As mentioned above.

In the above embodiments, a two-manpower field effect transistor has been described, but it goes without saying that the present invention can also be applied to a case of three or more manpower.

〔Effect of the invention〕

As described above, in the present invention, a single gate made of polycrystalline silicon is provided on the substrate 8i region between a pair of source and drain layers of a field effect transistor, and one gate is provided within the gate along the direction between the source and drain. A plurality of gate portions doped with conductivity type are provided with, for example, an undoped separation portion sandwiched between them, input terminals are led out individually from each gate portion, and one power supply potential is connected to the separation portion. By applying the other t source potential to the straight regions, the following effects can be achieved.

(a)? Since only one gate is required for the Jl number input field effect transistor, the required chip area can be reduced by at least 30% compared to the case where field effect transistors are provided for the number of inputs.

(b) The number of gates that need to be formed in the wafer process when incorporated into an integrated circuit device is reduced by at least half, making it possible to apply finer rules than before for the photo process, further reducing the required chip area. can do.

(C) Since multiple channels are connected in series within the semiconductor region below a single gate, the source-drain withstand voltage and electrostatic overvoltage withstand capacity are improved compared to conventional ones, increasing operational reliability. can.

The multi-input field effect transistor according to the present invention inherently has a logic gate function and can be incorporated into a chip area that is smaller than the conventional one. Therefore, it is particularly effective in improving the degree of integration of integrated circuit devices, and its operation as described above is particularly high. A side effect that can improve reliability can be produced.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an n-channel type and a p-channel type multi-input field effect transistor according to the present invention, and a circuit diagram of an example of their application. FIG. 2 is a cross-sectional view showing a conventional multi-input field effect transistor for an n-channel type and a p-channel type.
2: Substrate region or well, 3: Field oxide, 4: Gate oxide, 5: Gate, 51: Isolation part of gate, 5n: Gate part doped in n-type, 5
P: P-type doped gate portion, 6: Source/drain layer, 6d Ni-drain layer, 6+: Intermediate source/drain layer, 6s: Source layer, 7: Substrate connection layer, 8: Source/drain layer, 8d Nidorain layer, 8s:
Source layer, 9: Substrate connection layer, 10: Glabella insulating film, 11: Connection film, D drain terminal, E: Other power supply potential or ground potential, R: Resistor, S: Source terminal, Si
l, Si2: input terminal, So: output signal, V and one power supply potential;

Claims (1)

[Claims] A single gate made of polycrystalline silicon is provided on a substrate region between a pair of source and drain layers, and a plurality of gate portions doped with one conductivity type are formed in the gate along the direction between the source and drain. A separate part that is undoped or doped with the other conductivity type is sandwiched between them, and a gate part is provided at both ends, and an input terminal is individually led out from each gate part of the gate. A multi-input field effect transistor in which one power supply potential is applied to the separation portion and the other power supply potential is applied to the substrate region.