JPH03178139A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03178139A JPH03178139A JP1316398A JP31639889A JPH03178139A JP H03178139 A JPH03178139 A JP H03178139A JP 1316398 A JP1316398 A JP 1316398A JP 31639889 A JP31639889 A JP 31639889A JP H03178139 A JPH03178139 A JP H03178139A
- Authority
- JP
- Japan
- Prior art keywords
- film carrier
- lead
- semiconductor chip
- pin
- molding die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000011347 resin Substances 0.000 claims abstract description 6
- 239000011159 matrix material Substances 0.000 claims abstract description 5
- 238000005304 joining Methods 0.000 claims abstract description 3
- 238000001721 transfer moulding Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 abstract description 7
- 239000003822 epoxy resin Substances 0.000 abstract description 3
- 229920000647 polyepoxide Polymers 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
プラスチックパッケージ型の半導体装置の製造方法に関
し、
品質、生産性の向上を目的とし、
半導体チップの電極に接続されるインナーリードと、該
インナーリードに接続され且つマトリクス状に配置され
たパッドとが形成されたフィルムキャリアに該半導体チ
ップを搭載する工程と、該パッドに対応する位置にピン
植設用の孔を設けた第１のモールド金型の線孔にリード
ピンを挿入する工程と、前記パッドにリードピンを接合
する工程と、該フィルムキャリアを該第１のモールド金
型と、これと対向する第２のモールド金型とにより所定
の空間を開けて挟んで両側をトランスファーモールドし
て樹脂封止する工程とを有するように構成する。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a plastic package type semiconductor device, for the purpose of improving quality and productivity, an inner lead connected to an electrode of a semiconductor chip, and an inner lead connected to the inner lead are provided. and a step of mounting the semiconductor chip on a film carrier having pads arranged in a matrix, and a wire hole of a first mold having holes for pin installation at positions corresponding to the pads. a step of inserting a lead pin into the pad, a step of joining the lead pin to the pad, and a step of sandwiching the film carrier between the first mold die and a second mold die facing the same with a predetermined space therebetween. Then, both sides are transfer-molded and resin-sealed.
本発明は、プラスチックパッケージ型の半導体装置の製
造方法に関する。The present invention relates to a method of manufacturing a plastic package type semiconductor device.
近年、半導体装置では、高密度実装に伴い集積度も向上
し、そのパッケージは多ピン化が要求されている。この
為多ビン化が可能なビングリッドアレイパッケージは各
社から供給されるパッケージを用いることで多ピン化に
対応しているが、製造工程及びコストが増えるので、こ
れの改善が要望されている。2. Description of the Related Art In recent years, the degree of integration of semiconductor devices has improved due to high-density packaging, and their packages are required to have a large number of pins. For this reason, bin grid array packages capable of increasing the number of bins are compatible with the increase in the number of pins by using packages supplied by various companies, but since the manufacturing process and cost increase, there is a demand for improvement in this.
従来の半導体装置においては、ガラスエポキシ基板をも
とにしたプラスチックビングリッドアレイが主流となっ
ている。In conventional semiconductor devices, plastic bin grid arrays based on glass epoxy substrates have become mainstream.
第２図はこのプラスチックビングリッドアレイを示す図
である。これは多数のリードビン１がマトリクス状に配
置され植設されたガラスエポキシ基板２に半導体チップ
３を搭載し、その電極とリードピンに接続されたインナ
ーリード４との間をワイヤ５で配線したのち、ポツティ
ング樹脂６で覆い、さらに要すればキャップ７とエポキ
シ樹脂８で封止したものである。FIG. 2 is a diagram showing this plastic bin grid array. In this process, a semiconductor chip 3 is mounted on a glass epoxy substrate 2 on which a large number of lead bins 1 are arranged and implanted in a matrix, and wires 5 are used to connect the electrodes to the inner leads 4 connected to the lead pins. It is covered with a potting resin 6 and further sealed with a cap 7 and an epoxy resin 8 if necessary.
〔発明が解決しようとする課題〕
上記従来の半導体装置では、環境試験における温度サイ
クルにおいて、ガラスエポキシ基板が劣化し易いという
品質上の問題があり、またその製造は■個、１個の組立
であるので生産性が悪いという問題があった。[Problems to be Solved by the Invention] The above-mentioned conventional semiconductor device has a quality problem in that the glass epoxy substrate easily deteriorates during temperature cycles in environmental tests. Because of this, there was a problem of poor productivity.
本発明は上記従来の問題点に鑑み、品質及び生産性の良
い半導体装置の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device with good quality and productivity.
上記目的を達成するために、本発明の半導体装置の製造
方法では、半導体チップ１５の電極に接続されるインナ
ーリード１２と、該インナーリード１２に接続され且つ
？＋１クス状に配置されたパッド１３とが形成されたフ
ィルムキャリア１０に該半導体チップ１５を搭載する工
程と、該パッドに対応する位置にビン植設用の孔１６を
設けた第１のモールド金型１７の鎖孔１６に、リードピ
ン１８を挿入する工程と、前記パッドにリードピン１８
を接合する工程と、該フィルムキャリア１０を該第１の
モールド金型と、これと対向する第２のモールド金型と
により所定の空間を開けて挟んで両側をトランスファー
モールドして樹脂封止する工程とを有することを特徴と
する。In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes an inner lead 12 connected to an electrode of a semiconductor chip 15, and a ? A process of mounting the semiconductor chip 15 on a film carrier 10 having pads 13 arranged in a box shape, and a first molding die having a hole 16 for installing a bottle at a position corresponding to the pad. A step of inserting the lead pin 18 into the chain hole 16 of the mold 17, and inserting the lead pin 18 into the pad.
and sandwiching the film carrier 10 between the first mold die and a second mold die facing it with a predetermined space therebetween, transfer molding both sides, and sealing with resin. It is characterized by having a process.
本発明では、予めリードビン接続用のパッド１３を形成
したフィルムキャリア１０を用意し、これに半導体チッ
プ１５の搭載とリードピン１８の接合を行なった後、樹
脂にてモールドするため、−度に数個のビングリッドア
レイパッケージを製造することができる。またフィルム
キャリア１０の両側を樹脂にてモールドするため耐熱性
が良く品質向上が可能となる。In the present invention, the film carrier 10 on which the pads 13 for connecting lead bins are formed in advance is prepared, and after the semiconductor chip 15 is mounted and the lead pins 18 are bonded to the film carrier 10, the semiconductor chip 15 is mounted and the lead pins 18 are bonded. Bin grid array packages can be manufactured. Furthermore, since both sides of the film carrier 10 are molded with resin, it has good heat resistance and can improve quality.
第１図は本発明の詳細な説明するための図であり、（ａ
）〜（ｇ）図はその工程を示す図である。FIG. 1 is a diagram for explaining the present invention in detail, (a
) to (g) are diagrams showing the steps.
本実施例の半導体装置の製造方法は、先ず第１図（ａ）
に示すようなフィルムキャリア１０を用意する。このフ
ィルムキャリア１０には半導体チップを搭載する窓部１
１と、半導体チップの電極に接続するインナーリード１
２と、リードピンを接合するパッド１３と、該パッド１
３とインナーリード１２間を接続した配線パターン１４
とが形成されている。The method for manufacturing the semiconductor device of this embodiment is first shown in FIG. 1(a).
A film carrier 10 as shown in FIG. 1 is prepared. This film carrier 10 has a window portion 1 on which a semiconductor chip is mounted.
1 and inner lead 1 connected to the electrode of the semiconductor chip.
2, a pad 13 for connecting the lead pin, and the pad 1
Wiring pattern 14 connecting between 3 and inner lead 12
is formed.
次に（ｂ）図に示すように上記フィルムキャリア１０に
ＴＡＢ法〈オートメイテッドボンディング〉等により半
導体チップ１５をチップ付けし、その電極とインナーリ
ード１２を接合する。Next, as shown in the figure (b), a semiconductor chip 15 is attached to the film carrier 10 by the TAB method (automated bonding) or the like, and its electrodes and inner leads 12 are bonded.
次いで（Ｃ）図の如くマトリクス状に孔１６をあけたピ
ン植設用のモールド金型１７を用意し、このモールド金
型１７に（ｄ）図の如くリードピン１８を挿入する。Next, a mold 17 for pin implantation having holes 16 formed in a matrix as shown in (C) is prepared, and a lead pin 18 is inserted into this mold 17 as shown in (d).
次に（ｅ）図に示すようにリードピンをセットしたモー
ルド金型１７の上にフィルムキャリア１０をのせ、（ｆ
〉図の如く該フィルムキャリア１０のパラド１３とリー
ドピン１８とをレーザを用いて半田１９で接続するか、
又はスクリーン印刷した導電性接着剤で接着し硬化させ
る。Next, as shown in FIG.
〉As shown in the figure, connect the parallel plate 13 of the film carrier 10 and the lead pin 18 with solder 19 using a laser, or
Or glue and cure with screen printed conductive adhesive.
次いで（ｇ）図に示すようにリードピン１８とフィルム
キャリア１０がモールド金型１７から浮き上がらない様
にリードピン１８を真空引きしながら該フィルムキャリ
ア１０をモールド金型の下型１７と上型１７’ との間
に挟みエポキシ樹脂等でトランスファーモールドする。Next, as shown in the figure (g), the film carrier 10 is placed between the lower die 17 and the upper die 17' of the mold die while vacuuming the lead pin 18 so that the lead pin 18 and the film carrier 10 do not come up from the mold die 17. Place it in between and transfer mold with epoxy resin.
以上の本実施例によればフィルムキャリアを用い、モー
ルド金型で一度に複数個のピングリッドアレイパッケー
ジを製造することができるため生産効率が向上する。ま
た製造されたピングリッド７Ｌ／イパツケージはガラス
エポキシ基板を使用せず、フィルムキャリアの両面を樹
脂にてモールドするため耐熱性が向上する。According to this embodiment, a plurality of pin grid array packages can be manufactured at once using a mold using a film carrier, thereby improving production efficiency. In addition, the manufactured pin grid 7L/ipakage does not use a glass epoxy substrate, but has improved heat resistance because both sides of the film carrier are molded with resin.
以上説明した様に本発明によれば、フィルムキャリアで
多ビン化が可能となり、トランスファーモールドで一度
に複数個のビングリッドアレイパッケージ型の半導体装
置が製造でき、生産性の向上及び品質の向上に寄与する
ところ大である。As explained above, according to the present invention, it is possible to manufacture multiple bins using a film carrier, and a plurality of bin grid array package type semiconductor devices can be manufactured at the same time using transfer molding, which improves productivity and quality. This is a great contribution.
第１図は本発明の詳細な説明するための図、第２図は従
来の半導体装置を示す図である。
図において、
１０はフィルムキャリア、
１１は窓、
１２はインナーリード、
１３はパッド、
１４は配線パターン、
１５は半導体チップ、
１６は孔、
１７．１７’はモールド金型、
１８はリードピン、
１９は半田
を示す。FIG. 1 is a diagram for explaining the present invention in detail, and FIG. 2 is a diagram showing a conventional semiconductor device. In the figure, 10 is a film carrier, 11 is a window, 12 is an inner lead, 13 is a pad, 14 is a wiring pattern, 15 is a semiconductor chip, 16 is a hole, 17.17' is a mold, 18 is a lead pin, 19 is a Showing solder.
Claims (1)
リード（１２）と、該インナーリードに接続され且つマ
トリクス状に配置されたパッド（１３）とが形成された
フィルムキャリア（１０）に該半導体チップ（１５）を
搭載する工程と、該パッドに対応する位置にピン植設用
の孔（１６）を設けた第１のモールド金型（１７）の該
孔（１６）に、リードピン（１８）を挿入する工程と、
前記パッド（１３）にリードピン（１８）を接合する工
程と、該フィルムキャリア（１０）を該第１のモールド
金型と、これと対向する第２のモールド金型とにより所
定の空間を開けて挟んで両側をトランスファーモールド
して樹脂封止する工程とを有することを特徴とする半導
体装置の製造方法。1. The semiconductor chip (15) is placed on a film carrier (10) on which inner leads (12) are connected to electrodes of the semiconductor chip (15) and pads (13) are connected to the inner leads and arranged in a matrix. In the step of mounting the chip (15), a lead pin (18) is inserted into the hole (16) of the first mold (17), which has a hole (16) for pin implantation at a position corresponding to the pad. a step of inserting the
A step of joining the lead pin (18) to the pad (13), and opening a predetermined space between the film carrier (10) and the first mold die and a second mold die facing thereto. 1. A method of manufacturing a semiconductor device, comprising the steps of sandwiching the semiconductor device, transfer molding both sides, and sealing with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316398A JPH03178139A (en) | 1989-12-07 | 1989-12-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316398A JPH03178139A (en) | 1989-12-07 | 1989-12-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03178139A true JPH03178139A (en) | 1991-08-02 |
Family
ID=18076632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1316398A Pending JPH03178139A (en) | 1989-12-07 | 1989-12-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03178139A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309021A (en) * | 1991-10-16 | 1994-05-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having particular power distribution interconnection arrangement |
-
1989
- 1989-12-07 JP JP1316398A patent/JPH03178139A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309021A (en) * | 1991-10-16 | 1994-05-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having particular power distribution interconnection arrangement |
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