JPH03177085A - Multiple quantum hall element - Google Patents

Multiple quantum hall element

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Publication number
JPH03177085A
JPH03177085A JP1316095A JP31609589A JPH03177085A JP H03177085 A JPH03177085 A JP H03177085A JP 1316095 A JP1316095 A JP 1316095A JP 31609589 A JP31609589 A JP 31609589A JP H03177085 A JPH03177085 A JP H03177085A
Authority
JP
Japan
Prior art keywords
mesa
crystal substrate
semiconductor multiple
resistance
hall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1316095A
Other languages
Japanese (ja)
Other versions
JPH0710013B2 (en
Inventor
Toshimi Wada
和田 敏美
Toshio Nemoto
根本 俊雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
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Agency of Industrial Science and Technology
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Priority to JP1316095A priority Critical patent/JPH0710013B2/en
Publication of JPH03177085A publication Critical patent/JPH03177085A/en
Publication of JPH0710013B2 publication Critical patent/JPH0710013B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To make it possible to improve measurement accuracy for various kinds of measuring instruments by carrying out mesa etching to a semiconductor multiple heterojunction crystal substrate to form a strip-shaped mesa and forming an ohmic electrode on both ends of the longer axis of a mesa and both ends of the central part respectively. CONSTITUTION:An ultraviolet light UV is radiated to the surface of a semiconductor multiple heterojunction crystal substrate 30 coated with photoresist 40 by way of a photomask 50 which draws a mesa-shaped pattern for quantum holes, and then developed. After the development, mesa etching is carried out on the surface of the semiconductor multiple heterojunction crystal substrate 30. Again a photoresist 41 is coated on the surface of the semiconductor multiple hetero crystal substrate which has been mesa-etched where ultraviolet light is exposed and developed by way of a photomask 51 which draws a portion of electrode so that it becomes a hole. Then, a thin film 60 made of an ohmic electrode material is deposited gradually on the entire surface of the semiconductor multiple hetero crystal substrate 30 to remove a metal thin film in an area not associated with the electrode and to form ohmic electrodes 31 and 32 through heat treatment.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、電気抵抗の基準器、特に種々の電気・電子
機器に用いられる電気・電子回部中の抵抗等の直流電気
量(抵抗、電圧、電流)の超精密測定装置に用いる多重
型量子ホール素子に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to electrical resistance standards, particularly DC electrical quantities (resistance, The present invention relates to multiple quantum Hall devices used in ultra-precision measurement devices for voltage and current.

〔従来の技術1 量子ホール効果とは、極低温下に置かれた短冊型をした
2次元的に分布した電子の集団(2次元電子ガス)に電
流Iを流し、2次元電子ガス面に垂直に強い磁場Bを印
加すると、電流工および磁場B双方に垂直な方向に発生
するホール電圧V。
[Conventional technology 1] The quantum Hall effect is a phenomenon in which a current I is passed through a rectangular group of two-dimensionally distributed electrons (two-dimensional electron gas) placed at an extremely low temperature, and the current is perpendicular to the plane of the two-dimensional electron gas. When a strong magnetic field B is applied to , a Hall voltage V is generated in a direction perpendicular to both the electric current and the magnetic field B.

が、第5図に示すように、磁場Bの変化に対して階段状
に変化するようになる現象であり、この時、各ステップ
においては、ホール電圧■8と電流工の比、 V、/I     (ホール抵抗) が h/ie2 となる。ただしhはブランク定数、eは素電荷。
However, as shown in Fig. 5, this is a phenomenon in which it changes stepwise in response to changes in the magnetic field B, and at each step, the ratio of the Hall voltage 8 to the current, V, / I (Hall resistance) becomes h/ie2. However, h is a blank constant and e is an elementary charge.

iは自然数である。i is a natural number.

この量子化したホール抵抗が量子化ホール抵抗(R’H
)であり、普遍物理定数りおよびeと自然数だけで表さ
れるようになるため、抵抗の絶対的な基準となる。
This quantized Hall resistance is the quantized Hall resistance (R'H
), which is expressed only by the universal physical constants ri and e and natural numbers, and thus becomes the absolute standard for resistance.

従来、この種の素子としては、第6図(a)に示すよう
な構造のものが知られている。なお、第6図(b)は、
第6図(a)の点線で囲んだ部分の拡大図である。すな
わち、半絶縁性ガリウム砒素(GaAs)からなる半導
体基板1の上に無添加ガリウム砒素層2.無添加アルミ
ニウム・ガリウム砒素(AJ2GaAs)層3.シリコ
ン添加アルミニウム・ガリウム砒素(S 1−AI2G
aAs)層4およびシリコン添加ガリウム砒素(S 1
−GaAs)層5を順次成長して、いわゆる変調ドープ
型のヘテロ接合を形成し、このヘテロ接合結晶基板10
を台地型食刻(メサ・エツチング)によって短冊型にし
、第6図(a)で斜線を施した部分にオーム性電極11
,12,13゜14を形成して量子ホール素子HEとす
るものである。なお、このヘテロ接合構造では、無添加
GaA3層2と無添加AcGaA3層3との界面に2次
元電子ガス層6が生ずる。
Conventionally, as this type of element, one having a structure as shown in FIG. 6(a) is known. In addition, FIG. 6(b) shows
It is an enlarged view of the part surrounded by the dotted line in FIG. 6(a). That is, an additive-free gallium arsenide layer 2. is formed on a semiconductor substrate 1 made of semi-insulating gallium arsenide (GaAs). Additive-free aluminum gallium arsenide (AJ2GaAs) layer 3. Silicon doped aluminum gallium arsenide (S 1-AI2G
aAs) layer 4 and silicon-doped gallium arsenide (S 1
-GaAs) layers 5 are sequentially grown to form a so-called modulation doped heterojunction, and this heterojunction crystal substrate 10
is made into a rectangular shape by mesa etching, and an ohmic electrode 11 is placed in the shaded area in FIG. 6(a).
, 12, 13° 14 to form a quantum Hall element HE. In this heterojunction structure, a two-dimensional electron gas layer 6 is generated at the interface between the additive-free GaA 3 layer 2 and the additive-free AcGaA 3 layer 3.

量子化ホール抵抗R,の値は、−8には第7図のような
回路を構成して測定する。図中、Rsはある基準抵抗で
あり、基準電圧■3はその電圧端子に生ずる電圧である
。なお、■は定電流を示す。ここで、実際に測定される
量はホール電圧VHと基準電圧vsの値であり、これら
の値の比から、 Vs /Vo ”  (Vs /I)/ (VH/I)
= Rs / R。
The value of the quantized Hall resistance R is measured by configuring a circuit as shown in FIG. 7 at -8. In the figure, Rs is a certain reference resistance, and reference voltage 3 is the voltage generated at its voltage terminal. Note that ■ indicates constant current. Here, the quantities actually measured are the values of the Hall voltage VH and the reference voltage vs, and from the ratio of these values, Vs /Vo '' (Vs /I) / (VH /I)
=Rs/R.

となり、量子化ホール抵抗RHの値と電圧比v3/V、
、から基準抵抗R,の値を決定することができる。した
がって、ホール電圧V)Iや基準電圧V3の値が大きけ
れば大きいほど、言い替えれば定電流Iが大きければ大
きいほど、ますます測定の精度がよくなる。例えば、電
流測定限界を1pAとすれば、電流値10uAに対して
O,ippmの測定精度であるが、100uAに対して
はが最も安定であるため、従来型の量子ホール素子HE
の場合は、12.9にΩの標準抵抗発生装置用の素子と
して重要である。
Then, the value of the quantized Hall resistance RH and the voltage ratio v3/V,
, the value of the reference resistance R, can be determined from . Therefore, the larger the values of the Hall voltage V)I and the reference voltage V3, in other words, the larger the constant current I, the better the measurement accuracy becomes. For example, if the current measurement limit is 1 pA, the measurement accuracy is O,ippm for a current value of 10 uA, but since it is the most stable for 100 uA, the conventional quantum Hall element HE
In this case, it is important as an element for a standard resistance generator of 12.9Ω.

〔発明が解決しようとする課題] しかしながら、上記従来の量子ホール素子HEにおいて
は、1つの量子ホール素子HEに流し込める電流量には
限度がある。すなわち、電流量が多くなると量子ホール
素子HEへの電流の流入点において電流が集中するため
、電子の温度が上昇し量子ホール効果が起こらなくなる
といった重要な問題点があった。したがって、量子ホー
ル素子HEに流し込める電流量には限界があり(従来型
量子ホール素子HEの場合10〜20LLA程度が限界
であった)、抵抗値の測定精度にも限界があった。
[Problems to be Solved by the Invention] However, in the conventional quantum Hall element HE described above, there is a limit to the amount of current that can be flowed into one quantum Hall element HE. That is, when the amount of current increases, the current concentrates at the point where the current flows into the quantum Hall element HE, which causes an important problem in that the temperature of the electrons increases and the quantum Hall effect no longer occurs. Therefore, there is a limit to the amount of current that can be flowed into the quantum Hall element HE (the limit was about 10 to 20 LLA in the case of the conventional quantum Hall element HE), and there is also a limit to the accuracy of measuring the resistance value.

また、量子化ホール抵抗RHの値に関しても標準抵抗器
の観点からすれば、12.9にΩに最も近い1−OKΩ
標準抵抗器よりも、IKΩ標準抵抗器が最も安定で信頼
性が高いため、量子化ホール抵抗R,の値も1にΩ前後
で最も精度よく測定できることが必要である。
Also, from the perspective of a standard resistor, the value of the quantized Hall resistance RH is 1-OKΩ, which is closest to 12.9Ω.
Since the IKΩ standard resistor is the most stable and reliable than the standard resistor, it is necessary that the value of the quantized Hall resistance R, can be measured with the highest accuracy around 1Ω.

また、分圧器に関しては、従来型のようにコイルの巻数
比やコンデンサの容量比などを利用した装置では、コイ
ル自身の抵抗やインダクタンス等の影響を避けることが
できない。
Furthermore, with regard to voltage dividers, in conventional devices that utilize the turns ratio of the coil, the capacitance ratio of the capacitor, etc., it is impossible to avoid the effects of the resistance, inductance, etc. of the coil itself.

この発明は、上述した従来の量子ホール素子の問題点を
解決するためになされたもので、注入できる電流の量を
増加できる多重型量子ホール素子を提供することを目的
とする。
The present invention was made in order to solve the above-mentioned problems of the conventional quantum Hall device, and it is an object of the present invention to provide a multiple quantum Hall device that can increase the amount of current that can be injected.

[課題を解決するための手段] この発明にかかる多重型量子ホール素子は、高純度の半
絶縁性ガリウム砒素基板上に2次元電子ガス層を生成す
るヘテロ接合を多重に形成して半導体多重ヘテロ接合結
晶板とし、この半導体多重ヘテロ接合結晶板に台地型食
刻を施して短冊型の台地を形成し、この台地の長軸両端
および中央部の両端にオーム性電極を形成したものであ
る。
[Means for Solving the Problems] The multiplexed quantum Hall device according to the present invention is a semiconductor multiplexed heterojunction by forming multiple heterojunctions that generate a two-dimensional electron gas layer on a high-purity semi-insulating gallium arsenide substrate. This semiconductor multiple heterojunction crystal plate is used as a bonded crystal plate, and this semiconductor multiple heterojunction crystal plate is etched into a plateau shape to form a rectangular plateau, and ohmic electrodes are formed at both ends of the long axis of the plateau and at both ends of the central portion.

〔作用〕[Effect]

この発明によれば、2次元電子ガス層が多重になってい
るため、多重型量子ホール素子に流し込める電流量が多
重になっている分だけ増加し、量子化ホール抵抗の測定
精度が飛躍的に改善される。例えば、2次元電子ガスの
積層数を13とすれば、得られる量子化ホール抵抗の値
が、R,,412,9にΩ/13二O,992にΩとな
り、最も安定な既存の標準抵抗器であるIKΩ標準抵抗
と一対一で比較測定ができるようになるため、さらに高
い精度で抵抗の値付けができる。
According to this invention, since the two-dimensional electron gas layer is multiplexed, the amount of current that can be passed into the multiplex quantum Hall element increases by the amount of multiplex, and the measurement accuracy of quantized Hall resistance is dramatically improved. will be improved. For example, if the number of stacked layers of two-dimensional electron gas is 13, the value of the quantized Hall resistance obtained is R,412,9Ω/132O,992Ω, which is the most stable existing standard resistance. This allows for one-to-one comparative measurements with the IKΩ standard resistor, which is a standard resistor, making it possible to value the resistor with even higher accuracy.

また、この発明による組合わせ型抵抗標準装置を用いれ
ば多くの種類の抵抗の基準値を同時に発生できるため、
同時に多くの抵抗の値付けが高精度でできるようになる
。また、精密分圧器を用いれば、インダクタンスや容量
の影響を受けずに多くの種類の電圧比を高精度で測定で
きるようになる。
Furthermore, by using the combination type resistance standard device according to the present invention, reference values for many types of resistance can be generated simultaneously.
At the same time, it becomes possible to value many resistors with high precision. Furthermore, by using a precision voltage divider, many types of voltage ratios can be measured with high precision without being affected by inductance or capacitance.

[実施例] 第1図に実施例として1にΩ用多重型量子ホール素子の
作製法の例のうち、多重2次元電子ガス層を持つ半導体
多重ヘテロ接合結晶板30の構造例を示し、第2図(a
)〜(h)には、第1図に第1図において、高純度の半
絶縁性ガリウム砒素基板21に、超高真空中で無添加の
ガリウム砒る。ここで、シリコン原子の添加量はlXl
0”個/ cm”前後とする。そして、各層23,24
゜25を繰り返し、さらに12回成長させ多重層26を
形成し、最後に表面の酸化を防ぐために、シリコン添加
ガリウム砒素層27を約200オングストローム成長す
る。以上によって、半導体多重ヘテロ接合結晶板30が
形成される。この構造(第1図)を作製することによっ
て、無添加ガリウム砒素層23と無添加アルミニウム・
ガリウム砒素層24との各界面に2次元電子ガス層が生
成される。したがって、合計13層の2次元電子ガス層
が形成される。このように作製した13層の2次元電子
ガス層を持つ半導体多重ヘテロ接合結晶板30に、第2
図に示七たプロセスで加工を施し、第6図(a)に示し
た構造と同様の量子ホール素子を作製する。この手順を
第2図(a)〜(h)によって以下に記す。
[Example] As an example, FIG. 1 shows an example of the structure of a semiconductor multiple heterojunction crystal plate 30 having multiple two-dimensional electron gas layers, among examples of the method for manufacturing a multiple quantum Hall device for Ω. Figure 2 (a
) to (h), as shown in FIG. 1, additive-free gallium arsenide is applied to a high purity semi-insulating gallium arsenide substrate 21 in an ultra-high vacuum. Here, the amount of silicon atoms added is lXl
The number should be around 0"pieces/cm". And each layer 23, 24
25 is repeated and grown 12 more times to form a multilayer 26, and finally, a silicon-doped gallium arsenide layer 27 is grown to a thickness of about 200 angstroms to prevent surface oxidation. Through the above steps, the semiconductor multiple heterojunction crystal plate 30 is formed. By manufacturing this structure (Fig. 1), the additive-free gallium arsenide layer 23 and the additive-free aluminum layer 23 are formed.
A two-dimensional electron gas layer is generated at each interface with the gallium arsenide layer 24. Therefore, a total of 13 two-dimensional electron gas layers are formed. A second semiconductor multi-heterojunction crystal plate 30 having 13 two-dimensional electron gas layers prepared in this way is
Processing is performed according to the process shown in the figure to produce a quantum Hall device having a structure similar to that shown in FIG. 6(a). This procedure is described below with reference to FIGS. 2(a) to (h).

量子ホール効果が生じる多重2次元電子ガス層を含む短
冊型の台地を形成するために、第2図(a)に示すよう
に、量子ホール素子の短冊型図形を描画したフォトマス
ク50を通して、表面全域にフォトレジスト40を塗布
した半導体多重ヘテロ接合結晶板30の表面に紫外光U
Vを照射(露光)する。
In order to form a rectangular plateau containing multiple two-dimensional electron gas layers where the quantum Hall effect occurs, as shown in FIG. 2(a), the surface is Ultraviolet light U is applied to the surface of the semiconductor multiple heterojunction crystal plate 30 coated with photoresist 40 over the entire area.
Irradiate (expose) V.

次に、第2図(b)のように現像した後、第2図(c)
のように硫酸、過酸化水素水および水の混合液を用いて
、半導体多重ヘテロ接合結晶板30表面の台地型蝕刻(
メサ・エツチング)を行う。
Next, after developing as shown in Fig. 2(b), Fig. 2(c)
Using a mixture of sulfuric acid, hydrogen peroxide, and water, plateau-type etching (
Mesa etching).

次に、第2図(d)のように残存フォトレジスト40を
除去した後、第2図(e)のようにメサ・エツチングし
た半導体多重ヘテロ接合結晶板30の表面に再びフォト
レジスト41を塗布し、電極となる部分が穴になるよう
に描画したフォトマスク51を通して紫外線UV露光す
る。
Next, after removing the remaining photoresist 40 as shown in FIG. 2(d), photoresist 41 is again applied to the surface of the mesa-etched semiconductor multiple heterojunction crystal plate 30 as shown in FIG. 2(e). Then, it is exposed to ultraviolet light through a photomask 51 drawn so that the portions that will become electrodes are holes.

次に第2図(f)のように現像した後、第2図(g)の
ように真空蒸着法を用いて半導体多重ヘテロ接合結晶板
30の表面全域にオーム性電極材料である金とゲルマニ
ウムの合金(A u G e ) 。
Next, after development as shown in FIG. 2(f), gold and germanium, which are ohmic electrode materials, are deposited on the entire surface of the semiconductor multiple heterojunction crystal plate 30 using a vacuum evaporation method as shown in FIG. 2(g). alloy (A u G e ).

ニッケル(Ni)および金(Au)の薄膜60を順次蒸
着し、電極31〜34(電極33.34は図示されてい
ない)用とする。
Thin films 60 of nickel (Ni) and gold (Au) are sequentially deposited for electrodes 31 to 34 (electrodes 33 and 34 are not shown).

次いで、第2図(h)のようにリフト・オフ法によって
余分な電極に関係のない領域の金属薄膜を除去し、最後
に熱処理をして蒸着金属のうち主にゲルマニウムを2次
元電子ガス層の方へと拡散してオーム性の電極31.3
2を形成する。
Next, as shown in Figure 2 (h), the excess metal thin film in areas unrelated to the electrodes is removed by a lift-off method, and finally heat treatment is performed to remove mainly germanium from the deposited metal into a two-dimensional electron gas layer. The ohmic electrode 31.3 diffuses towards
form 2.

このようにして作製された第6図(a)のような形状の
多重型量子ホール素子を、液体ヘリウム温度(4,2K
) 、できればさらに低温(1,5に程度)の雰囲気中
において、多重型量子ホール素子の表面に垂直に2次元
電子ガス層の電子濃度に応じて適当な磁場(6〜8テス
ラ程度)を印加する。このような環境の下で、第6図(
a)中のオーム性電極11からオーム性電極12へと電
流を流せば、オーム性電極13とオーム性電極14との
間に量子化したホール電圧■。が発生する。
The multiple quantum Hall device thus fabricated as shown in FIG. 6(a) was heated at a liquid helium temperature (4.2
), apply an appropriate magnetic field (about 6 to 8 Tesla) perpendicular to the surface of the multiplexed quantum Hall device according to the electron concentration of the two-dimensional electron gas layer, preferably in an atmosphere at an even lower temperature (about 1.5 Tesla). do. Under such an environment, Figure 6 (
a) If a current flows from the ohmic electrode 11 to the ohmic electrode 12 in the middle, a quantized Hall voltage ■ will be generated between the ohmic electrode 13 and the ohmic electrode 14. occurs.

この起電力を流入電流で除することにより精密な量子化
ホール抵抗R0の値を得ることができる。
By dividing this electromotive force by the inflow current, a precise value of the quantized Hall resistance R0 can be obtained.

第3図にはこの発明の利用例として組合わせ型抵抗標準
装置の構成例を示した。ここでは、−例として2次元電
子ガス層の積層数nが1,2,13.129の4種類の
多重型の量子ホール素子HEI、HE2.HE13.H
E129を定電流■の電流源に直列に接続した装置を示
した。n=1.2,13,129は各々RH=12.9
にΩ、6.45にΩ、IKΩおよび100Ωに対応して
おり、未知の抵抗Rにの値を測定する場合には、この装
置に直列にRxを接続した際に、Rxの電圧端子に生ず
る電圧■8と4種類の量子化ホール電圧(V□、 V 
82. V Hps + V 14129)のうち最も
近い電圧との比を求めることによって未知の抵抗Rxの
正確な値を決定することができる。
FIG. 3 shows a configuration example of a combination type resistance standard device as an example of the use of the present invention. Here, as an example, four types of multiplexed quantum Hall elements HEI, HE2. HE13. H
A device is shown in which E129 is connected in series to a constant current source. n=1.2, 13, 129 are each RH=12.9
It corresponds to Ω, 6.45Ω, IKΩ and 100Ω, and when measuring the value of an unknown resistance R, when Rx is connected in series to this device, the voltage generated at the Rx terminal is measured. Voltage ■8 and 4 types of quantized Hall voltage (V□, V
82. The exact value of the unknown resistance Rx can be determined by finding the ratio of V Hps + V 14129) to the nearest voltage.

第4図にはこの発明の他の利用例として精密分圧器の一
構成例を示した。この装置では、ある電圧■。に直列に
2次元電子ガス層の積層数nが各々β、、I22,12
mの多重型量子ホ:ル素子HEfll、HEj22.H
Eε3が接続されており、各素子の量子化ホール電圧と
して発生する。したがって、2次元電子ガス層の積層数
nが同じあるいは異なった多くの多重型量子ホール素子
でこの装置を構成することにより、分圧の自由度が非常
に高い精密分圧器となる。
FIG. 4 shows an example of the configuration of a precision voltage divider as another example of the use of the present invention. In this device, a certain voltage ■. The number n of two-dimensional electron gas layers stacked in series is β, , I22, 12, respectively.
m multiple quantum hole elements HEfll, HEj22. H
Eε3 is connected and is generated as a quantized Hall voltage of each element. Therefore, by configuring this device with many multiple quantum Hall devices in which the number n of two-dimensional electron gas layers stacked is the same or different, a precision voltage divider with a very high degree of freedom in partial pressure can be obtained.

[発明の効果1 この発明は、以上詳細に説明したように、高純度の半絶
縁性ガリウム砒素基板上に2次元電子ガス層を生成する
ペテロ接合を多重に形成して半導体多重ヘテロ接合結晶
板とし、この半導体多重ペテロ接合結晶板に台地型食刻
を施して短冊型の台地を形成し、この台地の長軸両端お
よび中央部の両端にオーム性電極を形成したので、従来
型の量子ホール素子よりも数段多くの電流を素子に流し
込め、それに応じて量子化ホール抵抗の測定精度が改善
される。また、同時にほとんど1にΩの量子化ホール抵
抗が得られるため、既存の非常に安定な1にΩ標準抵抗
器への値付は作業が容易になり、さらに高精度化できる
ようになる。また、この発明を組合せ型抵抗標準装置に
用いることにより、多種類の抵抗に精度高く値付けがで
きるようになる。さらに、精密分圧器に用いれば、リー
ド線等のインダクタンスや容量成分の影響を受けずに電
圧を正確に分圧することができるようになる。したがっ
て、この発明による多重型量子ホール素子を用いて種々
の計測機器等の計測精度の向上を図ることができる。
[Effects of the Invention 1] As explained in detail above, the present invention provides a semiconductor multiple heterojunction crystal plate by forming multiple Peter junctions that generate a two-dimensional electron gas layer on a high-purity semi-insulating gallium arsenide substrate. This semiconductor multiple Peter junction crystal plate was etched into a plateau shape to form a rectangular plateau, and ohmic electrodes were formed at both ends of the long axis and at both ends of the plateau. A current several steps higher than the element can be passed through the element, and the measurement accuracy of the quantized Hall resistance is improved accordingly. In addition, since a quantized Hall resistance of almost 1Ω is obtained at the same time, it becomes easier to assign a value to the existing extremely stable 1Ω standard resistor, and further accuracy can be achieved. Further, by applying the present invention to a combination type resistance standard device, it becomes possible to price many types of resistors with high accuracy. Furthermore, if used in a precision voltage divider, voltage can be divided accurately without being affected by inductance or capacitance components such as lead wires. Therefore, the measurement accuracy of various measuring instruments can be improved by using the multiple quantum Hall device according to the present invention.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明による多重型量子ホール素子の一実施
例における多重2次元電子ガス層の構成図、第2図(a
)〜(h)はこの発明による多重型量子ホール素子の作
製方法の工程図、第3図は組合せ型抵抗標準装置の一例
を示す図、第4図は精密分圧器の一例を示す図、第5図
は量子ホール効果を簡単に説明した図、第6図(a)は
従来型の量子ホール素子の構造を示す斜視図、第6図(
b)は、第6図(a)の部分拡大図、第7図は量子化ホ
ール抵抗の測定回路図である。 図中、21は半絶縁性ガリウム砒素基板、22はガリウ
ム砒素バッファ層、23は無添加ガリウ結晶板、31〜
34は電極、40.41はフォトレジスト、50.51
はフォトマスク、UVは紫外線である。 第 1 図 第 図 第 図 x 第 図 V。 第 図 第 図
FIG. 1 is a configuration diagram of multiple two-dimensional electron gas layers in an embodiment of the multiple quantum Hall device according to the present invention, and FIG.
) to (h) are process diagrams of the method for manufacturing a multiplexed quantum Hall device according to the present invention, FIG. 3 is a diagram showing an example of a combination type resistance standard device, FIG. 4 is a diagram showing an example of a precision voltage divider, and FIG. Figure 5 is a diagram briefly explaining the quantum Hall effect, Figure 6 (a) is a perspective view showing the structure of a conventional quantum Hall element, and Figure 6 (
b) is a partially enlarged view of FIG. 6(a), and FIG. 7 is a circuit diagram for measuring quantized Hall resistance. In the figure, 21 is a semi-insulating gallium arsenide substrate, 22 is a gallium arsenide buffer layer, 23 is an undoped gallium crystal plate, 31 -
34 is an electrode, 40.41 is a photoresist, 50.51
is a photomask, and UV is ultraviolet light. Figure 1 Figure x Figure V. Figure Figure

Claims (1)

【特許請求の範囲】[Claims]  高純度の半絶縁性ガリウム砒素基板上に2次元電子ガ
ス層を生成するヘテロ接合を多重に形成して半導体多重
ヘテロ接合結晶板とし、この半導体多重ヘテロ接合結晶
板に台地型食刻を施して短冊型の台地を形成し、この台
地の長軸両端および中央部の両端にオーム性電極を形成
したことを特徴とする多重型量子ホール素子。
A semiconductor multiple heterojunction crystal plate is obtained by forming multiple heterojunctions that generate a two-dimensional electron gas layer on a high-purity semi-insulating gallium arsenide substrate, and plateau-shaped etching is applied to this semiconductor multiple heterojunction crystal plate. 1. A multiplex quantum Hall device characterized by forming a rectangular plateau and forming ohmic electrodes at both ends of the longitudinal axis of the plateau and at both ends of the central part.
JP1316095A 1989-12-05 1989-12-05 Multiple quantum Hall device Expired - Lifetime JPH0710013B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1316095A JPH0710013B2 (en) 1989-12-05 1989-12-05 Multiple quantum Hall device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1316095A JPH0710013B2 (en) 1989-12-05 1989-12-05 Multiple quantum Hall device

Publications (2)

Publication Number Publication Date
JPH03177085A true JPH03177085A (en) 1991-08-01
JPH0710013B2 JPH0710013B2 (en) 1995-02-01

Family

ID=18073185

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH0710013B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0801379A1 (en) * 1996-04-12 1997-10-15 Silmag Process for producing a semiconductor magnetic field detector magnetic head and head obtained by this process
US7440227B2 (en) 2005-02-28 2008-10-21 Hitachi Global Storage Technologies Netherlands B.V. Magnetic head having a hall effect sensor and circuit for detecting recorded bits from magnetic recording media
CN103743930A (en) * 2013-12-26 2014-04-23 中国计量科学研究院 A set of decimal-system standard resistors and a voltage divider produced by using same
CN103743929A (en) * 2013-12-19 2014-04-23 中国计量科学研究院 1kohm and 100ohm standard resistors
CN109596871A (en) * 2018-11-12 2019-04-09 中国计量科学研究院 Quantum resistance standard device
CN117098445A (en) * 2023-10-17 2023-11-21 北京东方计量测试研究所 Low-magnetic-field gallium arsenide quantized Hall resistor sample and manufacturing method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0801379A1 (en) * 1996-04-12 1997-10-15 Silmag Process for producing a semiconductor magnetic field detector magnetic head and head obtained by this process
FR2747498A1 (en) * 1996-04-12 1997-10-17 Silmag Sa METHOD FOR MAKING A SEMICONDUCTOR FIELD DETECTOR MAGNETIC HEAD AND HEAD OBTAINED THEREBY
US7440227B2 (en) 2005-02-28 2008-10-21 Hitachi Global Storage Technologies Netherlands B.V. Magnetic head having a hall effect sensor and circuit for detecting recorded bits from magnetic recording media
CN103743929A (en) * 2013-12-19 2014-04-23 中国计量科学研究院 1kohm and 100ohm standard resistors
CN103743929B (en) * 2013-12-19 2016-10-05 中国计量科学研究院 A kind of 1k Ω and 100 Ω measuring resistances
CN103743930A (en) * 2013-12-26 2014-04-23 中国计量科学研究院 A set of decimal-system standard resistors and a voltage divider produced by using same
CN103743930B (en) * 2013-12-26 2016-09-07 中国计量科学研究院 One group of decimal system measuring resistance and the divider using it to make
CN109596871A (en) * 2018-11-12 2019-04-09 中国计量科学研究院 Quantum resistance standard device
CN117098445A (en) * 2023-10-17 2023-11-21 北京东方计量测试研究所 Low-magnetic-field gallium arsenide quantized Hall resistor sample and manufacturing method thereof
CN117098445B (en) * 2023-10-17 2023-12-22 北京东方计量测试研究所 Low-magnetic-field gallium arsenide quantized Hall resistor sample and manufacturing method thereof

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