JPH03176858A - Data processing circuit for disk device - Google Patents

Abstract

PURPOSE:To eliminate limitation on the way of use and to handle a fast signal and a micro signal by mounting the circuit on an optical head by out-fitting a component to change the available range of each function on a highly integrated circuit with few mounting area which converts the micro signal from the optical head to data in a broad band area. CONSTITUTION:To convert an electrical signal from the optical head 3 which detects light obtained by casting the light on the optical disk 1 and performs photoelectric conversion to read data, control track data, or sector mark data, the components such as resistors R1-R36, R40-R44, capacitors C1-C13, etc., to change the available range of each function are out-fitted on the highly integrated circuit with few packaging area in which several kinds of functions such as a subtraction circuit 41, an inverse amplifier circuit 42, a video signal processing circuit 43, a comparator 44, and a peak detection circuit 50, etc., are integrated and which converts the micro signal from the optical head 3 to the data in the broad band area. Thereby, it is possible to eliminate the limitation on the way of use and to handle the fast signal and the micro signal by packaging the circuit on the optical head 3.

Description

Detailed Description of the Invention [Objective of the Invention 1] (Industrial Application Field) This invention is directed to an electrical signal from an optical helad that detects light obtained by irradiating a disk with light and converts it into electricity. The present invention relates to a data processing circuit for a disk device that converts data into data.

(Prior Art) As is well known, for example, image data is recorded on an optical disk using a laser beam output from a semiconductor laser in an optical head, and image data, control track data, and sector mark data recorded on an optical disk are recorded. Various optical disk devices have been developed that perform reading by converting such data into electrical signals using a detector in an optical head and then converting the data into corresponding data using a data processing circuit.

The data processing circuit described above is a so-called discrete circuit created using an off-the-shelf operational amplifier, or a highly integrated circuit (LSI).

On the other hand, in the case of a circuit constructed using discrete circuits, although there is a degree of freedom, it takes up half the mounting area, increases the number of components, and is expensive, and is particularly difficult to construct because it is constructed by connecting several operational amplifiers. When handling high-speed signals or small signals, it was difficult to implement, and the wiring could introduce noise, making it impossible to bring out the best performance. In addition, highly integrated circuits (LSI)
), the above points can be avoided, but there are many limitations on the model, optical disk, power supply, input/output signal, etc.
The drawback was that it was difficult to use.

Therefore, there is a need for a device that is not limited in usage and can handle high-speed signals and minute signals by being mounted on an optical head.

(Problems to be Solved by the Invention) This invention is not limited in its usage, and there is a demand for a device that can handle high-speed signals and minute signals by being mounted on an optical head. The object of E's object is to provide a data processing circuit for a disk device that can handle high-speed signals and minute signals by being mounted on an optical head.

[Structure of the Invention] (Means for Solving the Problems) A data processing circuit of a disk device according to the present invention detects light obtained by irradiating a disk with light and converts it into an electric signal from an optical head. For converting data into data, various functions are integrated and a highly integrated circuit with a small mounting area converts the minute signal from the optical head into data over a wide band. It consists of parts that change the scope of use.

(Function) The present invention converts an electrical signal from an optical head into data, which detects light obtained by irradiating light onto a disk and performs photoelectric conversion, and in which various functions are integrated. This is a highly integrated circuit with a small mounting area that converts minute signals into data over a wide band, and external components that change the range of use of each function.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 shows a disk device. This disk device records and reproduces (or erases) information on an optical disk (disk) 1 using focused light.

A spiral groove (recording track) is formed on the surface of the optical disc 1, and the disc 1 is rotated by a motor 2 at a constant speed, for example. This motor 2 is controlled by a motor control circuit]8.

The optical disc 1 is, for example, 5.25 inches (approximately 13 inches).
．． 3 cm) or 12 inches, the surface of a circular substrate made of glass or plastic is coated with a donut-shaped metal film layer, that is, a recording film made of tellurium or bismuth. A notch, that is, a reference position mark, is provided near the center.

Furthermore, on the optical disk 1, there is a data recording area where a guide groove (recording track) is formed, and an area where there is no guide groove or servo bite provided on the inner circumferential side of this data recording area, where control track data is recorded. (Special application 1986
225527) and a characteristic data recording area recorded in advance at the time of manufacture.

The data recording area is divided into a plurality of sectors based on the reference mark. On the optical disk 1, variable length information is recorded over a plurality of blocks, and on the optical disk 1 there are 360,001 pieces of information.
- 300,000 blocks are now formed on the rack. A block header in which an address and the like are recorded is provided in advance at the beginning of the block. Further, some optical discs 1 have sector marks added to each sector.

Recording and reproduction of information on the optical disc 1 is performed by an optical head 3. This optical head 3 is fixed to a drive coil 13 that constitutes a movable part of a linear motor 31, and this drive coil 13 is connected to a linear motor control circuit 17.

A linear motor position detector 26 is connected to this linear motor control circuit 17, and this linear motor position detector 26 is connected to an optical scale 25 provided on the optical head 3.
By detecting this, a position signal is output.

Further, a permanent magnet (not shown) is provided at the fixed portion of the linear motor 31, and when the drive coil 13 is excited by the linear motor control circuit 17, the optical head 3 is moved in the radial direction of the optical disk 1. It has become so.

An objective lens 6 is held on the optical head 3 by a wire or a leaf spring (not shown), and the objective lens 6 is moved in the focusing direction (
The driving coil 4 allows movement in the tracking direction (direction perpendicular to the optical axis of the lens).

Further, the laser beam generated by the semiconductor laser 9 driven by the laser control circuit 14 is transmitted to the collimator lens 1.
1a1 half prism 11b1 is irradiated onto the optical disk 1 through the objective lens 6, and the reflected light from the disk 1 is then transmitted to the photodetector 8 via the objective lens 6, the half prism 11b1, the condensing lens 10a1, and the cylindrical lens 10b. be guided.

The objective lens drive device using the wire 4.5 is described in Japanese Patent Application No. 61-284591, so its explanation will be omitted here.

The photodetector 8 includes four photodiodes 8a and 8 that receive reflected light from the optical disc and convert it into an electrical signal.
b, Bc, and 8d.

Photodiode 3a of the optical head 3.

The cathode sides of 8b, 8c, and 8d are commonly connected to a video signal preamplifier circuit 19b, and the anode sides are respectively connected to a focus/tracking processing circuit 40. Here, photodiodes 8a, 8b s 8c
, 8d have junction capacitance, so a reverse bias of about 5 volts is applied from the anode to the cathode to reduce this junction capacitance. For this reason, the video signal preamplifier circuit 1.
The operating center of the signal input to 9b is 7.5 volts, and the operating center of the signal input to the focus/tracking processing circuit 40 is 2.5 volts.

As a result, current flows from the cathode to the anode in the photodiodes 8a, 8b, 8c, and 8d in response to the reflected light from the optical disc 1, and video signal processing is performed using the sum of the currents extracted from the cathode side. Focusing (maintaining a constant distance between the optical disc 1 and objective lens 6)/tracking (following a guide groove recorded in advance on the optical disc 1) is performed using each current taken out from the anode side. .

The focus/tracking processing circuit 40 includes amplifiers 12 a , 12 b , 1.2 c , 12
d, focusing control circuit 15, tracking control circuit 16, linear motor control circuit 17, adder 30a13
0c1 and operational amplifiers OPI and OF2.

That is, the output signal of the photodiode 8a of the photodetector 8 is sent to the adders 30a, 3 via the amplifier 1.2a.
The output signal of the photodiode 8b is supplied to one end of the photodiode 8b, 30c, and 30d, and the output signal is sent to the adder 3 via the amplifier 12b.
Supplied to one end of 0b, 30d, photodiode 8C
The output signal is sent to adders 30b and 3 via amplifier 12c.
The output signal of the photodiode 8d is supplied to the other end of the adders 30a and 30d via an amplifier 12d.

The output signal of the adder 30a is supplied to the inverting input terminal of the differential amplifier OPI, and the output signal of the adder 30b is supplied to the non-inverting input terminal of the differential amplifier OP1. As a result, the differential amplifier OPI operates as the adder 30a, 30.
A track difference signal is supplied to the tracking control circuit 16 according to the difference in b. This tracking control circuit 16 creates a track drive signal in response to a track difference signal supplied from the differential amplifier OPI.

A track drive signal output from the tracking control circuit 16 is supplied to the drive coil 4 in the tracking direction. Further, the track difference signal used in the tracking control circuit 16 is supplied to the linear motor control circuit 17 (j).

Further, the output signal of the adder 30c is transmitted to the differential amplifier OP2.
The output signal of the two-part adder 30d is supplied to the non-inverting input terminal of the differential amplifier OP2. As a result, the differential amplifier op2 is connected to the adder 30.
A signal regarding the focus point is supplied to the focusing control circuit 15 in accordance with the difference between c and 30d. The output signal of this focusing 'Jiq control circuit] 5 is supplied to a focusing drive coil 5, and is controlled so that the laser beam is always in just focus on the optical disk 1.

When focusing and tracking are performed as described above, the sum current from the cathode side of each photodiode 3a to 8d of the photodetector 8 reflects the unevenness of the bits (recorded information) formed on the track. ing. This sum current is converted into a voltage value by a video signal preamplifier circuit 19b and supplied to a video processing circuit (data processing circuit) 19al.
(track number, sector number, etc.), control track data (characteristic data), and sector mark data are reproduced.

The video signal processed by the video processing circuit 19a is sent to an interface circuit 7 which performs demodulation processing, error correction processing, etc.
0 as an external device, the optical disc control device 71
It is now output to .

Further, the light level detection signal, recording abnormality detection signal, and data presence/absence detection signal obtained by the video processing circuit 19a are as follows:
It is designed to be output to CPO23.

The tracking control circuit 16 also controls the CPU 2.
The objective lens 6 is moved in response to a track jump signal supplied from B via the D/A converter 22, and the beam light is moved by one track.

2 The above laser ffi! I control circuit 14, focusing control circuit] 5, tracking control circuit 16, linear motor control circuit 17, motor control circuit 18, video processing circuit 19a
etc. are controlled by the CPU 23 via the lotus line 20, and this CPO 23 is controlled by the memory 24.
A predetermined operation is performed by the program written in t0.

The video processing circuit 19a is composed of a highly integrated LSI section 90 and externally attached resistors, capacitors, analog switches, etc. to the LSI section 90. In this way, a part of the video processing circuits 1 and 9a are converted into analog LS
By using an I (highly integrated circuit), there are no intermediate signal lines, etc., and the influence of this can be removed, making it possible to achieve a wider band than before. In addition, by converting a part of the circuit into an LSI, there is no need for wiring with multilayer boards as in the past, and there are fewer external parts, so it is possible to lay out a layerer on a flexible board as shown in Figure 3, for example. It also becomes possible to insert it into the gap in the mechanical system as a 3-flexible board.

Furthermore, it is also possible to attach the flexible substrate to the housing, frame, base, etc. of the mechanism, etc., and by doing so, space can be saved and the device can be made smaller. The LSI section 90 is a 44-pin type, and the pin arrangement of the signal lines is such that the power supply system for analog signals and the power supply system for digital signals are separated, as shown in FIG. If necessary, add an analog GND line next to the circuit for very small signals, thereby making it possible to create a circuit that is resistant to crosstalk and noise.

Also, since current is supplied from the power supply to each circuit, the circuits that use minute signals should be placed farthest from the power supply GND.
This prevents noise to the power supply GND from causing crosstalk to the analog circuit.

Additionally, the open pins are connected to GND inside the LSI to prevent noise and static electricity from entering and improve reliability.

Furthermore, since the output signals coming out from the photodiodes 48a, . . . of the optical head 3 are minute on the order of μ and are high-speed signals of 10 to 20 MHz, it is possible to implement the video processing circuit 19a by LSI. The area becomes smaller, and the video processing circuit 19a and preamplifier circuit 19
b comes to rest on the optical head 3. In addition, even in the case of a small optical head 3, the preamplifier circuit 19b is only 19b (the LSI section 90 of the video processing circuit 19a is about 40 pins, whereas the preamplifier circuit 1.9b is about 8 pins).
Therefore, regardless of the model, the wiring length can be shortened for the parts that handle the minimum necessary minute signals. Even if the optical head 3 has a different shape, the same LSI can be used for this division.

As shown in FIGS. 1 and 5, the video processing circuit 19a includes a subtraction circuit 41, an inverting amplifier circuit 42, a video signal processing circuit 43, a comparison circuit 44, a selection circuit 45, a recording abnormality detection circuit 46, and a data presence/absence detection circuit 46. Detection circuit 47, reference voltage generation circuit 48, non-inverting amplifier circuit 49, peak detection circuit 50
, comparison circuit] 5 51, comparison circuit 52, and light amount detection circuit 53
It is made up of.

The subtraction circuit 41 receives the voltage value (read signal, recording signal) as data from the preamplifier circuit 19b and the reference voltage REF (7.5 volts) as shown in FIGS. 6(a) and 6(b).
This is a circuit that compares and converts the signal into a signal with a center of 6 volts, and includes an external input resistor R], R1, an amplifier 41a for differential amplification provided inside the LS1 section 90, and a feedback resistor R2.
, R2. In this case, the input resistance R
1. R1 is set as τj outside the LS1 section 90, and can be changed depending on the model.In relation to the next stage, the feedback resistor R is set so that the feedback resistors R2 and R2 that enter the LS1 section 90 are in a ratio.
2. R2 is a fixed value.

Therefore, when a signal as shown in FIG. 7(a) is supplied from the preamplifier circuit 19b, a signal as shown in FIG. 7(b) is output.

Here, the reason why the difference between the data from the preamplifier circuit 19b and the 6JA quasi-voltage REF is calculated is that a reverse bias is applied to the photodiodes 3a, . . . of the optical head 3, so the operation of the preamplifier circuit 19b is When the center has a supply voltage of 12y, it is not 12/2-6V but 7
．． “5V is set. So this LSI section 90
Since this voltage may vary depending on the model, by using human power to calculate the difference between the operating center of the preamplifier circuit 19b, the input stage and subsequent stages can be processed using the operating center of the LS1 section 90. Therefore, the operation center of the preceding circuit can be connected as long as it is within the operating range of the supply voltage of the LS1 section 90, and furthermore, there is an advantage that the subsequent signal processing performance does not change at all regardless of the value. .

Furthermore, a resistor Rm, which is smaller than the input resistor R1, is placed inside the LS1 section 90, and input data is inputted through the resistor Rm. This protects the 7 LS1 section 90 from unstable operation due to the low impedance of the addition point (-) input of the amplifier 41a and a load connected to the outside, or even if it is shorted during adjustment/assembly. disappears.

Further, the output of the subtraction circuit 41 is applied to the outside of the LSI section 9 as a signal check signal, and is supplied to the test pin TP via the resistor RT. In this case too,
By outputting the signal through a resistor Rm provided in the LSI section 90 whose resistance value is negligible for operation, the LS1 section 90 is protected from destruction due to short circuits or the like.

Further, the test pin TPI is brought out from a high impedance location such as the output of the amplifier 41a. This prevents the operation from becoming unstable due to a load being connected to the check terminal, that is, the test pin TPI. Therefore, the test pin TPI should be brought out from a high impedance location.

The output of the subtraction circuit 41 becomes the original signal when creating the recording abnormality detection signal. In this case, since the output of the subtraction circuit 41 is determined by the value of the feedback resistor R2 in the LSI section 90,
Although the variation becomes large] 8 There is no problem even if the recording abnormality detection signal varies slightly, so the accuracy can be improved by determining the output by the ratio of the feedback resistor R2 and the input resistor R1. There is.

The inverting amplifier circuit 42 is a circuit that inverts and amplifies the output from the subtraction circuit 41, and has external (=j feedback resistors R4, R5,
It is composed of capacitors C1 and C2, an amplifier 42a1 provided inside the LSI section 90, an analog switch 42b, and a human resistor R3. As a result, by switching the external feedback resistors R4 and R5 using the analog switch 42b in response to a select signal from the CPU 23, and by changing the cane, it is possible to adapt to various types of optical discs with different characteristics. . For example, a signal as shown in FIG. 8 is output. Further, the output of the inverting amplifier circuit 42 is supplied to the test pin TP2 via a resistor RT.

Here, the gain is determined by using external feedback resistors R4 and R5, and one external capacitor C1 and C2. This allows for versatility with multiple models.
Furthermore, these are switched externally by an analog switch 42b. By doing this, the gain of inverting amplification and the frequency of the signal 1. This makes it possible to simultaneously apply the same limit, and it becomes possible to support an optical disk device that can handle many types of optical disks 1 having different reflectances. If you want to set the time constant of the circuit to the CR Cain ratio a (however, all is set and the feedback resistor R4 is set to have the largest gain ratio), the constant can be determined as follows.

When switch is OFF...gain R4/R3, time constant C2
・From R4, C2=C, R4=R When the switch is ON...Gain R4・R5/(R4+
R5) From R3=a-R4/R3, R5= ta/ (1
--a)l ・R4 time constant +R4・R5/ (R4+
R5)! (C1+C2)=C2・R4, C1= ((1-a)/al・C2 Also, this output signal is gain-switched to make it a fixed output regardless of the model etc., making subsequent processing easier. Therefore, precision or crystallinity is required for this signal. However, the accuracy of the absolute value of the resistance within 0 in part 9 of the LSI section is poor at ±30%, but the ratio of the resistance is within 526. Therefore, the key of this signal is (R2/R1)X (R4/R3) ==R2・R4/R1・R3, but here, the resistance R
2 and resistor R3 are the internal resistances of the LSI section 90, so they appear as a ratio, and since resistors R1 and R4 are attached externally, this also has good accuracy, and this output can increase the viscosity.

In this way, accuracy can be improved by allowing the internal resistance to be expressed as a ratio for the calculation process performed within the LS1 section 90. Also, since this is consistent with the need to switch the external resistors of the circuit, the gain is determined by increasing accuracy and using two half of the resistors instead of using all the resistors.

Further, a minute resistor Rm is provided in the LS131 section 90 between the negative side of the amplifier 42a and the output pin, and between the output side and the output pin.

The video signal processing circuit 43 inverts and amplifies the data signal portion of the output from the inverting amplifier circuit 42, clips the negative (-) side of the output, performs level feedback on the positive (+) side of the output, and outputs the output from the inverting amplifier circuit 42. This is a circuit that removes fluctuations in the (-) level of the output from 42, and is also a circuit that creates an original signal for detecting the presence or absence of data. This video signal processing circuit 43 includes external resistors R12, R14, R15, capacitors C3, C6, a high-speed amplifier 43a provided inside the LS1 section 90, a low-speed amplifier 43b1, resistors R6, R
7, R8, R9, RIOlR], 1, R13, diode D1, and DID.

In other words, the signal from the inverting amplifier circuit 42 is inverted and amplified,
The output signal is centered around 6 V (-1), which is determined by the bias of the input signal, by the limiter for the input signal (10) side, and the low-frequency feedback.Here, this feedback signal is connected to an external capacitor C6
A time constant is determined by 2 and resistors R14 and R15. This is decided externally because it is necessary to take this band with high precision.

Particularly regarding time constants, where precision is required, terminals are provided so that they can be externally connected.

In other words, the low frequency component (feedback component) is as follows when diode D1 is off (vO≧3, vi≦0.9) vo=1/(1,+R7/R1,3+R7/R13・
R14/R15) f(R7/R6+R7/R8+R7/
R13+ 1-) va-(R7/R8)
v b + (R14/R], 5・R7/R13) vc−
(R7/R13) vil Here, resistors R6, R13, R7, and R8 are LS1 part 90
The internal resistors R14 and R15 are external, and are determined by the resistance ratio.

In addition, as shown in FIG. 9(b), since the high frequency component is not a feedback component, a signal appears on the (-) side with respect to the above vO, and the cane is R when the diode is OFF.
7/R6 ON (R7・R1,0/ (R10+R7)
] It can be expressed by /R6 and the fire of resistance in the inner 3 part.

Furthermore, the output of the low-speed amplifier 43b is “v w =((
R:1.4 + R15) / R151v O-(R
1,4/R15) VREF (VREP = 6
bolt).

Note that the signal from the inverting amplifier circuit 42 is as shown in FIG.
), the output of the high-speed amplifier 43a is as shown in (b) of the same figure, and the output of the low-speed amplifier 43b is as shown in (c) of the same figure.

Also in this case, a small resistor Rm is provided within the LSI section 9 of each output terminal.

The comparison circuit 44 obtains image data or address data by binarizing the data from the video signal processing circuit 43, and uses external capacitors C5, !
:, amplifier 4481 as a comparator provided inside the LSI section 90, human resistance R16, diode D2,
It is composed of D3.

Video 4 shown by the solid line in FIG. 10(a) is created by the signal from the amplifier 43a of the signal processing circuit 43, the forward voltage caused by the diode D7 due to the signal, and the primary filter made of the resistor R15 and capacitor C5. The amplifier 44a converts the signal shown by the broken line in FIG.
Binarized bolt data is created and output as image data or address data as read data.

Also, the L between the (-) terminal and the output terminal of the amplifier 44a
A resistor Rm, which is smaller than the input resistor R16, is provided in the S1 section 90.

The selection circuit 45 selectively selects the image data and address data from the comparison circuit 44, the control track data from the comparison circuit 51, or the sector mark data from the comparison circuit 52 in accordance with the selection signal from the CPU 23. Two-part interface circuit 7 by main signal line
0, and is constituted by a data selector 45a such as a multiplexer. A digital voltage VD is applied to the output of the data selector 5 lid 45a via an external resistor RP.

Therefore, by selecting a digital signal that is only used as a serial signal using the data selector 45a and converting it into a single signal, cross-strokes with analog signals are less likely to occur, and the number of pins of the LSI section 90 can be reduced. .

As a result, for digital signals that do not need to be output simultaneously (digital signals created from analog signals), the data selector 45a is provided internally with a multiplexer, and only the necessary lines are routed outside the LSI section 9, thereby reducing the number of digital lines.
Cross strokes with analog signals can be suppressed.

The recording abnormality detection circuit 46 uses the output from the subtracting circuit 41 as shown in FIG. 11(a) to perform recording on a portion where data has already been recorded at the time of recording, that is, recording as shown in FIG. 11(b). It outputs an abnormality detection signal (signal for abnormality detection).

That is, a signal obtained by comparing the output from the subtraction circuit 41 at a slice level determined by a signal determined in the LS1 section 90 is output as a recording abnormality detection signal. This output requires an external resistor R.
A digital voltage VD is applied via P.

The data presence/absence detection circuit 47 is configured such that the output from the inverting amplifier circuit 42 as shown in FIG. This signal is converted into a signal, and by comparing this signal at a predetermined slice level shown by the broken line in Fig. 2 (b), a signal as shown in Fig. 3 (C) corresponding to the presence or absence of data is output. be. A signal obtained by comparing the output from the amplifier 43b with a predetermined value is output as a pig presence/absence detection signal. The output of the amplifier 47a is output to the CPU 23 as a data presence/absence detection signal, and a digital voltage VD is applied to this output via an external resistor RP.

The reference voltage generation circuit 48 generates a 1/2 analog voltage VA/2 (6 volts) from the analog voltage VA (12 volts) supplied from an external power supply, and is constructed by resistors R26, R27, and an amplifier 48a. It is configured. The output of this amplifier 48a is the reference voltage R
The signal is supplied as EF to each section within the LS1 section 90, and is also output to an external focus/tracking processing circuit 40, etc.

The Pope voltage REF is made to be VA/2 with respect to the voltage VA supplied to the LS1 section 90.

As a result, even if the supply voltage is different, the voltage is reduced to 1/2, so that even if the supply voltage varies depending on the model, it can be handled. Therefore, the reference voltage REF changes in proportion to the supply voltage, allowing operation over a wide range of supply voltages and providing versatility. Further, by outputting this output to 0 on the LSI section 9, connection with other circuits becomes easy.

Further, a minute resistor Rm is provided in the LS1 section 90 between the output of the amplifier 48a and the output terminal.

The non-inverting amplifier circuit 49 is as shown in FIG. 13(a).
As shown in FIG. 8(b), the output from the inverting amplifier circuit 42 is non-inverting amplified and biased, and the resistors R17, R18, R19
, R20, and an amplifier 49a. The output from this non-inverting amplifier circuit 49 is output from the LS1 section 90, and this signal is sent to the focus/track processing circuit 40. This signal is sent to the optical when the group is turned off.
When the SOTO 3 is accessed, brightness and darkness appear depending on the group, so this is converted into a binary value and used as a signal to detect whether the optical head 3 is currently accessing a group or a land. Here, since this signal and the language voltage REF, which is the center of operation of this signal, are output, the receiving focus/track circuit 40 can also easily connect by calculating the difference.

Therefore, the reference voltage REF is also output from the LS1 section 90,
- It is designed to be output together. This makes it easy to connect to the connected circuit.

Further, a small resistor Rm is provided in the LSI section 9 between the output of the amplifier 49a and the output terminal.

9 The peak detection circuit 50 is as shown in FIG. 14(a).
The dark level of the output from the non-inverting amplifier circuit 49 is shown in FIG.
), it detects the peak and buffers it, and consists of an external resistor R28, a capacitor C8, and an amplifier 50a1 diode D4 provided inside the LS1 section 90.
, and a resistor R21.

Further, a reference voltage REF is supplied to the (+) terminal of the amplifier 50a via a resistor Rm' having a large resistance value so that the LS1 section 90 reaches a predetermined operating point even if there is no external input. ing.

The comparison circuit 5] converts the output from the peak detection circuit 50 into the comparison circuit 4 using its own signal as shown in FIG. 14(b).
The signal shown in the same figure (C), which is obtained by comparing the signals generated in the same manner as in 4, is output as control track data. Amplifier 51a1 resistor R22, diode D as a comparator provided
6, D5.

0 Zunawaji, ¥S14 The signal from the amplifier 50a of the Pixel detection circuit 50, shown by the solid line in Figure (b), and the forward voltage generated by the signal from the diodes D5 and D6. The same figure (b
) and the DC voltage shown by the broken line using the amplifier 51a, binary data of 0 to 5 volts as shown in the figure (C) is created and output as control track data. There is.

As shown in FIGS. 15(a) and 15(b), the comparison circuit 52
A signal obtained by comparing the outputs from the four non-inverting amplifier circuits with a signal generated in the same manner as the comparator circuit 44 using its own signal is output as sector data. This comparison circuit 52 is composed of an external capacitor C7, an amplifier 49a1 as a comparator provided inside the LS1 section 90, a resistor R23, and diodes D8 and D9.

A minute resistance Rm is provided within the LSI section 90 between the diode D7 and the output terminal.

1. As shown in FIGS. 16(a) and 16(b), the light level detection circuit 53 performs peak detection on the brighter output from the non-inverting amplifier circuit 49, divides the voltage, buffers it, and then outputs the light level detection signal. This is the output, and the external resistors R24 and R
25, a capacitor C5, a resistor R24 provided inside the LS1 section 90, a diode D7, and an amplifier 53a. During recording, a large signal enters and saturates, but oscillation, latching, etc. do not occur.

That is, the output of the amplifier 53a is "VO=R25/
(R24+R25) (Vi-0,7)J.

-F The light level detection signal from the light level detection circuit 53, that is, the amplifier 53a is input to an A/D converter (not shown) and is used as a signal for checking the level of light reflected from the optical disc 1. This checks whether the force is applied or not.

Here, when an A/D converter is connected next as in this signal, the A/D converter used differs depending on the device, so the final stage is connected by an external resistor.
Since the bias can be determined, there is no restriction on the next A/D converter, and the signal can be changed according to the operating range of the A/D converter, providing versatility. Also, by determining the time constant using an external resistor and capacitor, accuracy can be improved.

In addition, a reference voltage REF is supplied to the (+) terminal of the amplifier 53a via a resistor Rm' having a large resistance value so that a predetermined operating point can be achieved without any input from the outside of the LS1 section 90. ing. This eliminates the possibility that even if nothing is connected to the terminal, the operating point will not be determined and the entire LSI section 90 will become unstable or destroyed. Further, a small resistor Rm is provided in the LSI section 90 between each terminal of the amplifier 53a and the output terminal.

Further, the LSI section 90 is supplied with an analog voltage from an analog power supply (not shown) and three digital voltages from a digital power supply (not shown). This LS1 part 90
In this case, since both analog processing and digital processing after comparison exist, the structure is such that the analog power supply and the digital power supply are separated even if the voltage values are the same. This prevents digital noise from mixing with analog, making the circuit resistant to noise.

In addition, the ground system is also separated into analog and digital systems, so that the noise that enters the digital GND is separated from the analog side, making it difficult for noise to enter the circuit.

Next, in such a configuration, focusing, I.
The operation of reading the control track while racking is being performed will be explained.

For example, now, an instruction to access a control track is supplied to the CPU 23 from the optical disk control device 71.

Then, the CPU 23 controls the linear motor control circuit 17 to move the optical head 3 from the innermost circumference of the optical disc 1 toward the outside.

4. Then, the CPU 2B stops the optical head 3, that is, the linear motor 3, when the laser light from the optical head 3 corresponds to the vicinity of the center of the control track.

Then, the CPU 2B causes the semiconductor laser 9 to generate laser light. As a result, the laser beam generated from the semiconductor laser 9 is transmitted through the collimator lens colla and the half prism 1.
1-b, through the objective lens 6, the light reflected from the optical disk is z-1
object lens 6, half prism 1]b1 condenser lens 10a
1 and a cylindrical lens 10b to a photodetector 8.

Therefore, each photodiode 8a of the photodetector 8,
The sum current from the cathode side of ~8d, that is, the current reflecting the unevenness of the pits formed on the track, is converted into a voltage value by the preamplifier circuit 19b and supplied to the subtraction circuit 41 in the video processing circuit 19a. Ru. This subtraction circuit 4
The voltage value from the preamplifier circuit 19b and the reference voltage 5 are compared, converted into a signal centered on 6 volts, and outputted to the inverting amplifier circuit 42. The output from the subtracting circuit 41 is inverted and amplified by the inverting amplifier circuit 42 , non-invertingly amplified by the non-inverting amplifier circuit 49 and multiplied by a bias, and then supplied to the peak detection circuit 50 . The peak detection circuit 50 peak-detects the dark level of the output from the non-inverting amplifier circuit 49, buffers it, and outputs it to the comparison circuit 51. This comparison circuit 51 compares the output from the peak detection circuit 50 with the slice level determined by the output signal. The IJ signal is output to the selection circuit 45 as control track data. As a result, the selection circuit 45 selects the comparison circuit 5.
The control track data supplied from 1 is the above C
The signal is output to the optical disk control device 71 via the interface circuit 70 in response to a select signal from the PU 23.

Thereby, the optical disk control device 71 reads the colon track data, that is, the characteristic data, by checking the time interval between the supplied control track data, that is, the recorded portion and the unrecorded portion.
demodulation). Control corresponding to this read characteristic data is performed. That is, control corresponding to optical discs 1 of various specifications (companies) is performed.

For example, the film characteristics (reflectance) of the optical disc 1, the recording power of the semiconductor laser, the power during playback, the format type (1
(number of sectors per cycle), etc. are controlled according to the corresponding specifications.

Next, the operation of reading image data and address data will be explained. For example, now, an instruction to access a predetermined track is supplied to the CPU 23 from the optical disk control device 71. Then, the CPU 23 near motor control circuit 17
By controlling the optical head 3, the optical head 3 is moved to a predetermined track.

Next, the CPU 23 causes the semiconductor laser 9 to generate laser light. As a result, the laser light generated from the semiconductor laser 9 is transmitted through the collimator lens]]a1 half prism 1
1b, onto the optical disc 1 through the objective lens 6, and the reflected light from this optical disc is reflected by the objective lens 6,
The beam 11b1 is guided to the photodetector 8 via the condenser lens 10a1 and the cylindrical lens 10b.

Therefore, each photodiode 8a of the photodetector 8,
The sum current from the cathode side of ~8d, that is, the current reflecting the unevenness of the pits formed on the track, is converted into a voltage value by the preamplifier circuit 19b and supplied to the subtraction circuit 41 in the video processing circuit 19a. Ru. This subtraction circuit 4
1, the voltage value from the preamplifier circuit 19b and the language voltage are compared, converted into a signal centered on 6 volts, and outputted to the inverting amplifier circuit 42. This inverting amplifier circuit 42 inverts and amplifies the output from the subtracting circuit 4 and supplies it to a video signal processing circuit 43. This video signal processing circuit 43
As a result, the data signal portion of the output from the inverting amplifier circuit 42 is inverted and amplified, the negative (=) side of the output is clipped, and the level feedback of the positive (+) side of the output is performed. The (-) level fluctuation of the signal is removed and the signal is supplied to the comparator circuit 44. By this comparison circuit 84, the signal from the video signal processing circuit 43 is
The data is converted into a value, level-shifted, and outputted to the selection circuit 45 as image data or address data. As a result, the selection circuit 45 outputs the image data or address data supplied from the comparison circuit 44 to the optical disk control device 71 via the interface circuit 70 in response to the selection signal from the second CPO 23. As a result, the optical disk control device 71 processes the supplied image data or address data as read data.

Next, we will explain the process for reading sector marks from an optical disc with sector marks marked on it. ] The sector mark written in sector units can be read, and data corresponding to the block header can be read using this sector mark.

In other words, the output from the subtraction triple circuit 41 is inverted and amplified by the inverting amplifier circuit 42, and the non-inverting amplifier circuit 49
It is non-inverting amplified and biased by
The signal is supplied to the comparison circuit 52. With this comparison circuit 52,
A signal obtained by comparing the outputs from the four non-inverting amplifier circuits at slice levels determined by their own signals is output to the selection circuit 45 as sector data. Thereby, the selection circuit 45 outputs the sector mark data supplied from the comparison circuit 52 to the optical disk control device 71 via the interface circuit 70 in response to the selection signal from the CPO 23. This results in
The optical disk control device 71 uses the supplied sector mark data to determine the position of the block header that could not be read, and processes the data read following this position as reproduced data.

Further, the recording abnormality detection circuit 46 detects when recording data.
Based on the output from the subtraction circuit 41, a recording abnormality detection signal is output to the CPU 2'3 as an abnormality detection signal.

0 Furthermore, the data presence/absence detection circuit 47 outputs a data presence/absence detection signal corresponding to the presence or absence of data to the CPO 23 by comparing the signal from the amplifier 43b of the video signal processing circuit 43 at a predetermined slice level. .

Further, the light amount level detection circuit 53 peak-detects the brighter output from the non-inverting amplifier circuit 49, divides the voltage, buffers it, and outputs a light m level detection signal to the CPU 23.

As mentioned above, subtraction, Various functions such as inversion amplification, video signal processing, comparison, and peak detection are integrated into a highly integrated circuit with a small mounting area that converts the minute signal from the optical head into data over a wide band. This allows parts such as resistors and capacitors to be changed externally.

4] With this, by replacing resistors, capacitors, etc., it is possible to handle various types of optical discs and optical disc devices.In other words, there are no restrictions on how it can be used, and by mounting it on the optical head, it is possible to handle intermediate signal lines, etc. This eliminates the need for high-speed signals and allows handling of small signals.

[Effects of the Invention] As described in detail above, according to the present invention, there are no limitations on how it can be used, and by mounting it on an optical head, a data processing circuit for a disk device that can handle high-speed signals and minute signals can be realized. Can be provided.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIGS. 1 and 5 are diagrams showing a schematic configuration of a video processing circuit, FIG. 2 is a diagram showing a schematic configuration of a disk device, and FIG. 3 is a diagram showing a schematic configuration of a video processing circuit. Figure 4 is a diagram for explaining the pin arrangement of the LSI part of the circuit, Figure 4 is a diagram for explaining an example of the installation of a video processing circuit, Figure 6 is a signal waveform diagram showing read signals and recording signals in the preamplifier circuit, Figure 7 shows the signal waveforms of each part of the subtraction circuit, Figure 10 shows the signal waveforms of each part of the comparison circuit, and Figure 11 shows the signal waveforms of each part of the recording abnormality detection circuit.
Figure 12 is a diagram showing the signal waveforms of each part of the data presence detection circuit, Figure 13 is a diagram showing the signal waveforms of each part of the non-inverting amplifier circuit, and Figure 14 is a diagram showing the signal waveforms of each part of the peak detection circuit. , FIG. 15 is a diagram showing signal waveforms of each part of the comparison circuit, and FIG. 16 is a diagram showing signal waveforms of each part of the light amount level detection circuit. DESCRIPTION OF SYMBOLS 1... Optical disk, 3. Optical head, 8... Photodetector, 8a1-... Photodiode, Il, 9 g.
...Preamplifier circuit,]9b...Video processing circuit (data processing circuit), 23.CPU, 24..Memory, 40
... Focus/tracking processing circuit, 41... Subtraction circuit, 42... Inverting amplifier circuit, 43... Video signal processing circuit, 44... Comparison circuit, 45... Selection circuit, 4
6... Recording abnormality detection circuit, 47... Data presence/absence detection circuit, 48... Base L: $ voltage 3 generation circuit, 49... Non-inverting amplifier circuit, 50... Peak detection circuit, 51...・Comparison circuit, 52... Comparison circuit,
53...Light level detection circuit, 71...Optical disk control device, 90...LSI section, R1-R36, R40-R
44, Rm, Rm'-resistor, C1--C13... capacitor, D1-D15... diode.

Claims (1)

[Claims] In a data processing circuit of a disk device that converts an electrical signal from an optical head that detects light obtained by irradiating the disk with light and converts it photoelectrically into data, various functions are integrated, A highly integrated circuit with a small mounting area that converts the minute signal from the optical head into data over a wide band, and a component that is externally attached to this highly integrated circuit and changes the usage range of each function. Characteristic data processing circuit of disk device.