JPH03175672A - Bipolar memory - Google Patents

Abstract

PURPOSE:To contrive speeding up of operation without causing instable storage of memory cell by forming the base region in a lateral type 2nd transistor with an inverse conductivity type layer having an impurity concentration higher than that of an inverse conductivity type epitaxial layer in the collector region of a 1st transistor. CONSTITUTION:This device is composed of a 1st transistor Tr. 1 and a lateral type 2nd transistor Tr. 2 which are equipped with two emitters 7A and 7B that are formed in an inverse conductivity type epitaxial layer 5 on a one conductivity type semiconductor substrate 1. Further, this device is constructed as a bipolar storage device in which the base of the 1st transistor Tr. 1 and the collector of the 2nd transistor Tr. 2 are formed with a one conductivity type impurity layer 6, and the collector of the 1st transistor Tr. 1 and the base of the 2nd transistor Tr. 2 are formed with inverse conductivity type impurity layers 5 and 9. Then, the base region 9 of the 2nd transistor Tr. 2 is formed with the inverse conductivity type layer 9 having an impurity concentration higher than that of the inverse conductivity type epitaxial layer 5, i.e., the collector region of the 1st transistor Tr. 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a bipolar storage device that is high speed, low power consumption, highly integrated, and has excellent operational stability.

BACKGROUND ART Conventionally, lateral PNP load type memory cells have been used as memory cells of high-speed, low power consumption, and highly integrated bipolar storage devices.

An example of a conventional lateral PNP transistor load type memory cell structure will be described with reference to the cross-sectional structure diagram of FIG.

An N-type epitaxial layer 5 is formed on the N-type buried collector layer 2 formed in the surface region of the P-type silicon substrate 1. 2 with the first P type diffusion layer 6 as a base and the two N type diffusion layers 7A and 7B formed separately on the surface area of the first P type diffusion layer 6 as emitters.
Construct an NPN transistor with two emitters,
As the electrode of this NPN transistor, the first P-type expanded I
11 The base electrode 12 is on the layer 6, the emitter electrode En13 of the hold transistor is on the N-type diffusion layer 7A, and the emitter Wj of the write/read transistor is on the N-type diffusion layer 7B.
, pole ER7w14, an N-type collector formed in the N-type epitaxial layer 5 and connected to the N-type buried collector layer 2.
A collector electrode 15 is formed on the wall 4. Further, a second layer formed in the surface region of the N-type epitaxial layer 5
The P-type diffusion layer 8 of is an emitter, NR:! A lateral PN1) transistor is constructed with the epitaxial layer 5 as a base and the first P-type diffusion layer 6 as a collector, and this lateral P
An emitter electrode 11 is formed on the second P-type diffusion layer 8 as an electrode of the NP transistor. The N-type epitaxial WI5 is shared as the collector of the NPN transistor and the base of the lateral PNP transistor, and the first
The P-type diffusion WI6 is shared as the base of the NPN transistor and the collector of the lateral PNP transistor. 3 is the separation area.

16 is an insulating layer.

The composite element configured in this manner corresponds to the components 40a and 40b of the memory cell 50 in the equivalent circuit shown in FIG. The components 40a and 40b connect the emitter electrode 11 of the lateral PNP transistor Tr, 2 and the emitter ff1ffiEs+13 of the NPN transistor Tr, 1, respectively, to form a word V◆ terminal 51, a word ty- terminal 52, and a terminal of the NPN transistor Tr, 1. base fl
i t4112 and the collector electrode 15 are cross-connected and the emitter voltage t4 of the NPN transistor Tr,1 is
The memory cell 50 is formed by taking out each E*zw14 individually and using it as a bit O terminal 53 and a bit 1 terminal 54. In the operating state of memory cell 50, either component 40a or 40b is in a conductive state, and a small holding current is biased to word V terminal 58 to maintain that state. A case will be explained in which the memory cell 50 is in a non-selected state and the component 40a is conductive. NPN
Both the transistor Tr,1 and the lateral PNP transistor Tr,2 operate in saturation, and the base-collector junction of the NPN transistor Tr,1 is also forward biased. Bit O terminal 53 and Bit 1 terminal 5
When another memory cell connected to the same bit line pair as Tr.4 is selected for reading or writing, the potential of the emitter electrode ERzw14 is 0.2 V or more higher than the potential of the collector electrode 15 of Tr.1. Become. That is, N
In the PN transistor Tr,l, when the base-collector junction is forward biased, the emitter is at a high potential with respect to the collector, so current flows in the reverse direction from the emitter to the collector in the NPN transistor Tr,1. In other words, a current is sucked from the bit O terminal 53.Furthermore, this parasitic sucking current value has a characteristic that it increases as the hpt (current amplification factor) of the lateral PNP transistor rr,2 becomes larger.

Problems to be Solved by the Invention In the conventional configuration described above, in order to increase the operating speed of the memory cell, the N-type epitaxial layer M5 is lowered in order to reduce the collector-base junction capacitance of the NPN transistor Tr. In terms of concentration, since the base region of the lateral PNP transistor Tr,2 is also composed of the same N-type epitaxial layer 5, this also has a low concentration, and there is no need to explain it in detail.
2 hFE increases. As already mentioned, this increase in hPH of the lateral PNP transistor Tr,2 results in an increase in the value of the sink current from the bit terminals 53,54.
Ωc11. Lateral PNP transistor Tr.

When the base width of the transistor 2 is 3 μm, the hFE of the lateral PNP transistor Tr2 is about 70, and the sink current of the memory cells is 5 μm. By the way, in a normal memory, memory cells 5 connected to the same bit line pair
Because 0 consists of dozens or more.

The total parasitic sink current flowing through the bit line is several hundred μ.
Also becomes A. This current is supplied by a circuit that detects the potential within the memory cell 50, that is, a sense amplifier, through the bit line pair. This places an excessive burden on the sense amplifier, making the operation of the sense amplifier and the memory retention operation of unselected memory cells unstable. Therefore, as long as the above conventional configuration is used, it is difficult to increase the speed of the memory.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a bipolar memory device that can operate at high speed without destabilizing memory retention in memory cells.

Means for Solving the Problems In order to solve the above problems, the bipolar memory device of the present invention has a base region of a lateral type second transistor that is doped with impurities higher than the opposite conductivity type epitaxial layer of the collector region of the first transistor. It is formed from a conductive layer type with opposite concentrations.

Effect According to the above configuration, h of the lateral type second transistor
Fl! is determined by the concentration of the opposite conductivity type layer, so even if the concentration of the opposite conductivity type epitaxial layer is lowered to improve the operating speed, the hFE of the second transistor will not increase and the saturation of the first transistor will become deeper. This prevents the sinking current from increasing, so that the operation speed can be improved without making the memory retention operation of the memory cell unstable.

Example An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a structural diagram of a lateral PNP transistor load type memory cell showing an embodiment of the present invention. Components that are the same as those of the conventional example shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

In the memory cell of the present invention, the base region of the lateral PNP transistor is formed of a second N-type diffusion layer 9 having a higher impurity concentration than the N-type epitaxial layer 5 which is the collector region of the NPN transistor.

A method for forming a memory cell according to the present invention will be explained.

First, an N-type buried collector layer 2 is selectively formed in the surface region of a P-type silicon substrate 1, and then an N-type epitaxial layer 5 is grown. An isolation region 3 such as a P-type diffusion layer or a thick oxide film by LOCO8 method is formed, and an N-type collector wall 4 is selectively formed.The 0th-order N-type epitaxial layer 5 becomes the base of a lateral PNP transistor. A second N-type diffusion layer 9 is selectively formed in the desired surface region. After this, NP is applied to the surface region of the N-type epitaxial layer 5.
A first P-type diffusion layer 6, which will become the N transistor base region and the collector of the lateral PNP h transistor, and a second P-type diffusion layer 8, which will become the emitter of the lateral PNP transistor, are formed. moreover.

Two NPNs separated in the surface region of the first P-type diffusion layer 6
N-type diffusion layers 7A and 7B which will become emitters of transistors are formed.

According to the above formation method, the concentration of the second N-type diffusion layer 9 can be controlled independently from the concentration of the N-type epitaxial layer WJ5. For example, if the concentration ratio is increased to 10 times or more, the operation speed can be improved. Even if the concentration of the N-type epitaxial layer 5 is lowered in order to achieve this, the base concentration of the lateral PNP transistor will not become less than 90% of the original concentration.
The lateral PNP transistor hFE increases little, and therefore the parasitic sink current that makes the memory retention operation unstable increases little, the second N-type diffusion N9
By making the concentration 10 times or more higher than that of the N-type epitaxial layer 5, the hFE of the lateral PNP transistor is lower than that of a conventional structure in which all parts other than the second N-type diffusion layer 9 are the same. Therefore, the parasitic sink current decreases and the memory retention operation decreases.

Needless to say, it is stable.

- As an example, the specific resistance of the N-type epitaxial layer 5 is 1 Ωcm.
(Impurity concentration 5.5X101sas-'), and the concentration of the second N-type diffusion layer 9 is IX101701-',
By making the diffusion depth deeper than the first P-type diffusion layer 6 and the second P-type diffusion layer 8, the hFE of the lateral PNP h transistor with a base width of 3 μm becomes approximately 4. As a result, the parasitic sink current is about 1 μA, which is about 115 in the conventional example, and the memory retention operation can be stabilized.

As described in detail, according to the bipolar memory device of the present invention, the impurity concentration of the opposite conductivity type layer formed as the base region of the second transistor is made higher than the impurity concentration of the opposite conductivity type epitaxial layer. Even if the impurity concentration of the opposite conductivity type epitaxial layer is reduced in order to improve the operating speed, the hFE of the second transistor hardly increases, and an increase in parasitic sink current can be almost prevented. Therefore, stable memory retention characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a lateral PNP transistor-loaded memory cell showing an embodiment of the present invention. FIG. 2 is a cross-sectional structural diagram of a conventional lateral PNP transistor load type memory cell, and FIG. 3 is a circuit diagram of the memory cell. Process: P-type silicon substrate, 5: N-type epitaxial layer, 6: first P-type diffusion layer, 7: first N-type diffusion layer, 8: second P-type Diffusion layer, 9... Second N-type expanded I'II layer, 11... Emitter electrode, 12... Base electrode, 13... Emitter voltage tME+t of hold transistor, 14... Write/read transistor Emitter electrode ER/W, I5...Collector electrode, 50...Memory cell.

Claims (1)

[Claims] 1. Consisting of a first transistor having two emitters and a lateral type second transistor formed in an opposite conductivity type epitaxial layer on a semiconductor substrate of one conductivity type, the base of the first transistor and A bipolar memory device in which the collector of the second transistor is connected to an impurity layer of one conductivity type, and the collector of the first transistor and the base of the second transistor are connected to an impurity layer of an opposite conductivity type. . A bipolar memory device, wherein the base region of the second transistor is formed of an opposite conductivity type layer having a higher impurity concentration than the opposite conductivity type epitaxial layer which is the collector region of the first transistor.