JPH0317431B2 - - Google Patents

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention writes an output signal of a data restoration circuit that restores a block including a plurality of pixels into a block line memory, and reads out a read output signal from the block line memory. The present invention relates to a memory control method for controlling writing and reading so that a block line memory can be effectively used in an image processing circuit that transfers images to a recording section for image recording.

[Conventional technology]

The image processing circuit in the facsimile receiver is
For example, as shown in FIG.
, a block line memory circuit 2 , and a recording section 3 . The data restoration circuit 1 is for restoring the received compressed data, and when the data compression method targets a block including a plurality of pixels, the received compressed data is restored and output in units of blocks. This restored data in units of blocks is added to the block line memory circuit 2.

The block line memory circuit 2 has a buffer function for temporarily storing data so that the data is transferred at a constant speed to the recording unit 3 in response to irregular restored data input from the data restoration circuit 1;
It has a function to convert the input/output order from a block unit to a data order according to a normal line, and when the data restoration circuit 1 generates an error, it converts the block line affected by the error to the previous block line. It also has an error recovery function that replaces the error.

The recording section 3 has a configuration that follows a recording method such as an electrostatic recording method or a thermal recording method, and records images in accordance with data transferred from the block line memory circuit 2 at a constant speed. .

Figure 6 is an explanatory diagram of blocks and block lines, where LO1, LO2, LO3,... are odd lines,
LE1, LE2, LE3,... are even lines, BL1,
BL2, BL3,... are block lines, BK1,
BK2, BK3, . . . are block numbers, indicating a case where a block line is composed of two lines, an odd number line and an even number line, and a case where 2×4 pixels constitute one block.

For example, when data compression processing is performed on dithered image data using a 4 x 4 dither matrix using a pattern predictive coding method, the data compression processing is performed using 2 x 4 pixels as one block. , when restoring the received compressed data, as described above, the restored data is obtained with one block of 2×4 pixels.

For example, as shown in FIG. 7, the data restoration circuit 1 outputs restored data in units of block numbers BK1, BK2, BK3, etc. of the block line memory BLi, and inputs it to the block line memory circuit 2. Ru. The block line memory circuit 2 stores the data input in block units, and stores it in the block number BK of the odd line LOi.
Outputs in the order of 1, BK2, BK3, etc. up to the last block number of the odd line LOi, then shifts to the even line LEi and outputs the block number from the beginning.
BK1, BK2, BK3, . . . are output in this order and transferred to the recording unit 3 for image recording.

FIG. 8 is a block diagram of a conventional block line memory circuit, in which 4, 5, and 13 are registers (REG), 6 and 7 are demultiplexers (DMPX),
8 to 11 are line memories (LM), and 12 is a multiplexer (MPX). The restored data from the data restoration circuit 1 in the previous stage of this block line memory circuit is divided into odd line data LOD and even line data LED, and is stored in registers 4 and 4, respectively.
It is latched at 5.

Odd line data LOD is distributed to odd line memories 8 and 9 by demultiplexer 6, and even line data LED is distributed to even line memories 10 and 11 by demultiplexer 7. When one of the odd line memories 8, 9 performs a write operation, the other performs a read operation, and when one of the even line memories 10, 11 performs a write operation, the other performs a read operation. The data read by the read operation is sent to the multiplexer 12.
The data is latched in the register 13 via the ROM and transferred to the recording unit 3 as reproduced image data PD.

FIG. 9 is an explanatory diagram of the operation timing of the conventional block line memory circuit described above, and a to d are odd line memories 8, 9, even line memories 10,
A write operation W and a read operation R with respect to No. 11 are shown. First, as shown in a and c, a write operation W is performed between the odd line memory 8 and the even line memory 10 at time t1.
is started, and the odd line data LOD and even line data LED from the data restoration circuit 1 are written simultaneously. When the writing ends at time t2, the odd line memory 9 and the even line memory 11 start the write operation W, as shown in b and d.
Further, as shown in a, the odd line memory 8 enters the read operation R, and when the read operation R ends at time t3, the even line memory 10 enters the read operation R, as shown in c. Similarly, from time t3 to time t
8, data is written in blocks by the selection of line memories 8 to 11, and then read out in line order and transferred to the recording unit 3 as image data at a constant speed. Records will be made in accordance with.

Also, between times t2 and t4, data is read out at a constant speed from the odd line memory 8 and the even line memory 10, and until the reading is finished, as shown between times t2 and t3', the odd number It is necessary that the write operation W of the line memory 9 and the even line memory 11 has been completed. Therefore, the block line memory circuit 2 only has a buffering capacity for one block line.

FIG. 10 is a timing diagram for explaining the error recovery operation in which, when an error occurs in the data restoration circuit 1, the block line affected by the error is replaced with the previous block line, and the timing diagram shows the error recovery operation at time t11.
~t19 indicates a break in line data output.

At time t12', the odd and even line memories 9,
If a data error is detected during the write operation W of 11, the data in those line memories 9 and 11 are not normal, so the data of the previous block line remaining in the odd and even line memories 8 and 10 is By repeatedly reading out from time t13 to time t17, the error block line is replaced. Also, data restoration circuit 1
Then, error recovery processing is performed, and when normal data is output from time t13' to t15' and written to the odd and even line memories 9 and 11, the data is read from time t17, so it is normal. The situation will be restored. Therefore, when an error occurs, two block lines are replaced by the data of the block line immediately before the error block line.

[Problem that the invention seeks to solve]

Since the block line memory circuit 2 has a buffering capacity for one block line, it cannot immediately return to normal operation upon recovery from an error. That is, in FIG. 10, the first odd number after error recovery at time t15',
Even if the normal data write operation W to the even line memories 9 and 11 is completed, the even line memory 1
Unless the read operation R of 0 is completed at time t17, the odd line 9 is read out R.
It was not possible to read data normally.

Furthermore, the lower the resolution, the lower the usage efficiency of the block line memory circuit, and the buffer capacity is only one block line regardless of the resolution. For example, in Figure 11, the original size is B4, and the resolution is 4, 8, 12, 16.
(lines/mm) (100, 200, 300, 400 [dots/inch]), line memory 8, when line memory capacity is configured as 1024 x 4 bits in accordance with resolution 16 [lines/mm]. 10, 9, and 11, and a is a resolution of 4 [lines/mm] (1024 [dots/mm]).
line]), line memories 8, 10,
The used areas 9 and 11 are fixed areas from 0 to 0FFF, and writing and reading of data corresponding to the block line is executed only within the area from 0 to 0FFF. Therefore, the total 0~
This meant that only 1/4 of the area of 3FFF was used, resulting in a decrease in usage efficiency.

Also, b indicates the case where the resolution is 8 [lines/mm] (2048 [dots/line]), and line memories 8, 10, 9,
Since the used area of No. 11 is a fixed area of 0 to 1 FFF, only 1/2 of the entire area is used. Also, c indicates the case where the resolution is 12 [lines/mm] (3072 [dots/line]), and line memory 8,
The used areas of 10, 9, and 11 are fixed areas of 0 to 2 FFF, so 3/4 of the area of 0 to 3 FFF is used.

Also, d indicates the case where the resolution is 16 [lines/mm] (4096 [dots/line]), and it is about the case where the capacity corresponds to this resolution, so it is 100%.
The efficiency of use is as follows.

As mentioned above, regardless of the resolution, the buffering capacity is only for one block line, and writing and reading are performed in a fixed address range corresponding to the resolution, so the lower the resolution, the more efficient line memory usage becomes. It was a decline.

The present invention aims to improve the above-mentioned conventional drawbacks.

[Means for solving problems]

The memory control method of the present invention is a memory control method that controls a block line memory for adding image data restored by a data restoration circuit of a facsimile to a recording unit, and performs a write operation and a read operation in units of words. A plurality of line memories that can be executed alternately and a control circuit that controls the write operation and read operation of the line memories are provided, and the data restoration circuit is configured to perform the data restoration circuit for the plurality of line memories corresponding to the lines constituting the block line. The restored block data is written in word units, and the data is sequentially read out from the selected line memory in word units and transferred to the recording section. Instead of this data, the data of the immediately preceding block line is read out and transferred to the recording section.

[Effect]

The block data restored by the data restoration circuit is simultaneously written to the line memory corresponding to the block line, and sequentially read from the selected line memory and transferred to the recording section to form image data at a constant speed. If the addresses overlap, writing and reading are performed alternately in word units, and control is performed so that writing and reading are performed for all addresses in the line memory. Also, by detecting an error in the data restoration circuit, instead of the data in the error block line, the data in the immediately preceding block line is read out, replaced with the data in the error block, and transferred to the recording unit. It is.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
21, 22, 26 are registers REG, 23, 24
are line memories LM1 and LM2, 25 is multiplexer MPX, and 27 is write address control circuit.
WAD, 28 is a read address control circuit, and 29 is a control circuit. Odd line data LOD from the data recovery circuit is latched into register 21, and even line data LED is latched into register 22.

The line memories 23 and 24 are fast-in-fast-out (FIFO) type memories in which writing and reading can be performed alternately in word units.
The data read out is latched into the register 26 via the multiplexer 25 and transferred to the recording section as image data PD.

The control circuit 29 also includes a write address control circuit 27 to which a block data restoration end signal DD and an error detection signal ER from the data restoration circuit are applied, and outputs a write address signal for the line memories 23 and 24, and a line memory. A read address control circuit 28 that outputs read address signals 23 and 24, a read control signal, and a switching control signal of the multiplexer 25.
It has the following.

The write address control circuit 27 starts incrementing the write address in response to the restoration end signal DD from the data restoration circuit, and performs increments of one word.
Outputs an address signal to write the odd line data LOD and even line data LED latched in the registers 21 and 22 to the line memories 23 and 24 in word units, and writes the data to all addresses in the line memories 23 and 24. This controls the writing. When the error detection signal ER from the data recovery circuit is applied, the output of the write address signal is stopped, the write operation of the line memories 23 and 24 is stopped, and the data recovery circuit becomes normal. When the restoration end signal DD is applied, the write address signal starts advancing from the start address of the area corresponding to the error block line, and the odd line data LOD and even line data LED are stored in the line memories 23 and 24. This allows writing to be performed.

Further, the read address control circuit 28 includes means for outputting a read address signal that continuously advances and can perform read control for all addresses in the line memories 23 and 24, and a means for outputting a read address signal that can perform read control for all addresses in the line memories 23 and 24, and a means for outputting a read address signal that can perform read control for all addresses in the line memories 23 and 24, and a means for outputting a read address signal that can perform read control for all addresses in the line memories 23 and 24, and a means for outputting a read address signal that can perform read control for all addresses in the line memories 23 and 24, and a means for outputting a read address signal that can perform read control for all addresses in the line memories 23 and 24, A control signal and a multiplexer 25 that cause one of the line memories 23 and 24 to perform a read operation
and means for controlling the read address signal so as to read out the data of the immediately preceding block line again based on the error detection signal ER from the data restoration circuit. The signal output means can be composed of, for example, a counter that continuously counts clocks and a decoder that decodes the count contents of the counter and generates a read address signal. The signal can be formed using the output signals of some output stages of the counter.

The block data restored by the data restoration circuit is latched in the registers 21 and 22 as odd line data LOD and even line data LED, respectively, and is sent to the write address control circuit 27 by the block data restoration end signal DD from the data restoration circuit. The write address signal from is incremented, and according to the write address signal, registers 21 and 22
The data latched into the line memories 23 and 24
written to. Further, by a control signal from the read address control circuit 28, for example, when the line memory 23 enters a read operation, the multiplexer 25 is switched and controlled to selectively output the data read from the line memory 23. When one line of data is read from the line memory 23, the control signal controls the line memory 24 to perform a read operation, and the multiplexer 25 selectively outputs the data read from the line memory 24. Switching is controlled.

For example, when block data is input from the data restoration circuit while the line memory 23 is in read operation, one word of data is written by the write address signal, and one word is written by the read address signal. The reading of data will be performed alternately. Therefore,
Data that has already been written can be read from the line memory during the writing operation, and image data can be read at a constant speed.
PD can be transferred to the recording section.

FIG. 2 is an explanatory diagram of the operation timing of the embodiment of the present invention, in the case where the resolution is 8 [lines/mm] (2048 [dots/line]) and the line memories 23 and 24 have a capacity for 4 block lines. belongs to. In the figure, a and b indicate the write operation and read operation of the line memory 23, and c and d indicate the line memory 23.
4, the writing of the data of the block line BL1 restored by the data restoration circuit is started from time t1 to the line memories 23 and 24.

When the writing of the data on the block line BL1 is completed at time t2, reading of the data on the odd line LO1 constituting the block line BL1 from the line memory 23 is started. Further, from time t2 to time t3', the next block line BL2 is written. Therefore, in the line memory 23, writing and reading are performed alternately in word units.

When the reading of one line is completed at time t3,
Reading of the data of the even line LE1 constituting the block line BL1 from the line memory 24 is started. At this time, the line memory 24 stores the time t.
Since the data on block line BL2 up to 3' is written, and then the data on block line BL3 is written, writing and reading are performed alternately on a word-by-word basis.

As mentioned above, the line memories 23 and 24 have four
Since it has a capacity for block lines, even after writing of data for block line BL1 is completed, there remains an area for three block lines. Therefore, at time t3', the block line Even if reading of data on even line LE1 of line BL1 is not completed, the block line
Immediately after writing the data of BL2, it becomes possible to write the data of the next block line BL3.
Therefore, depending on the ratio of writing speed and reading speed,
It is also possible to write continuously as at times t4' to t7' and t9, increasing the data buffering capacity.

Moreover, FIG. 3 is an explanatory diagram of operation timing when an error occurs in the data restoration circuit, and a to d are as follows.
Corresponding to a to d in Fig. 2, block line BL8
Suppose that the error detection signal ER from the data restoration circuit is applied to the control circuit 29 at time t12' while data is being written to the even line LE6 and data from the even line LE6 is being read. After that, the already written block line BL7
The reading of data on the odd line LO7 starts at time t.
13 to t14, then the even number line
Reading of data of LE7 is from time t14 to t15.
It will be held at.

Also, an error in the data restoration circuit occurs at time t13.
After recovery, the restored block line BL
Writing of data No. 10 begins immediately at time t13'. Then, for example, data is continuously written to block lines BL11 and BL12 until time t18. Also error block line
Block line just before BL8 Odd number line of BL7
The data of LO7, even line LE7 is at time t15.
Since the data is repeatedly read from t19 to t19, the data for two block lines BL8 and BL9 is replaced by the data for block line BL7.

FIG. 4 is an explanatory diagram of the usage state of the line memories 23 and 24, with the document size set to B4 and the resolution set to 4.
8, 12, 16 [lines/mm] (100, 200, 300, 400 [dots/inch]), and the line memory 23 has a 2 x 1024 x 4 bit configuration to match the resolution of 16 [lines/mm]. 24.

a indicates the case where the resolution is 4 ([lines/mm] (1024 [dots/line])), and if data of an odd number line that constitutes one block line is written in the area from 0 to 0FFF, the data of the next odd number line is 0FFF
It is written in the area of ~1FFF, and the same goes for the following,
It is controlled to write up to 7FFF,
This results in a buffer capacity of 7 block lines.

Therefore, the write address control circuit 27 and read address control circuit 28 of the control circuit 29
It has a configuration that can output a 7FFF address signal. For example, from 0 to line memory 23
After reading the 0FFF area, read the 0 to 0FFF area of the line memory 24, and then read the area of the line memory 24.
After reading the area from 0FFF to 1FFF in 3.
Reading of the area 0FFF to 1FFF of the line memory 24 is performed. In this way, the read address signal
The data written in the area from 0 to 7FFF is read out at a constant speed. In this case, the read address signals for the line memories 23 and 24 can be formed separately from the upper 0 to 7 since the lower 0 to FFF are common.

Also, b indicates the case where the resolution is 8 [lines/mm] (2048 [dots/line]), and the data corresponding to block lines are 0 to 1 FFF, 1 FFF to 3 FFF, 3 FFF to
Since it is written to each area of 5FFF and 5FFF to 7FFF, it has a buffer capacity of 3 block lines. Then, the line data corresponding to one block line is read by the read address signal from 0 to 1 FFF, and then the line data corresponding to the next block line is read by the read address signal from 1 FFF to 3 FFF.

Also, c is a resolution of 12 [lines/mm] (3072 [dots/mm]).
Line]), 1 in the area 0 to 2FFF
Since the data for the block line is written,
It has a buffer capacity of 5/3 block line. Also, c is the resolution 16 [lines/mm] (4096
[dot/line]), and has a buffer capacity for one block line. In addition, in all resolutions, the remaining one block line is
It is necessary to secure it for error recovery.

In the above embodiment, the capacity of the line memories 23 and 24 is selected to suit a resolution of 16 lines/mm, but the capacity of the line memories 23 and 24 is not limited to this. It's not something you can do. Further, the control circuit 29 which outputs the write address signal and the read address signal of the line memories 23 and 24 may be constructed from a microprocessor or the like, and the writing and reading may be controlled by a program.

〔Effect of the invention〕

As described above, the present invention provides line memories 23 and 24 that can alternately perform write operations and read operations in units of words, and a control circuit 29, and block data from the data restoration circuit 1. is written to the line memories 23 and 24 in word units,
By sequentially selecting the line memories 23 and 24 and reading out the data in word units, it is transferred to the recording unit 3 as image data at a constant speed, and error detection in the data restoration circuit 1 allows the error block line to be corrected. Instead of the data, the data of the immediately preceding block line is read from the line memories 23 and 24 and transferred to the recording section 3, and the line memories 23 and 24 can be used effectively, so when the resolution is low. has the advantage of having a large buffer capacity. Further, the data restoration circuit 1 has the advantage of returning to normal operation more quickly after error recovery than the conventional example due to the large buffering capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of operation timing of the embodiment of the present invention, and FIG.
The figure is a diagram explaining the operation timing when an error occurs in the embodiment of the present invention, FIG. Explanatory diagram of block line,
Fig. 7 is an explanatory diagram of the rearrangement of the order of input and output in a block line memory circuit, Fig. 8 is a block diagram of a conventional block line memory circuit, and Fig. 9
FIG. 10 is a diagram illustrating the operation timing of the conventional example, FIG. 10 is a diagram illustrating the operation timing when an error occurs in the conventional example, and FIG. 11 is a diagram illustrating the state of use of the line memory in the conventional example. 21, 22, 26 are registers (REG), 23,
24 is line memory LM1, LM2, 25 is multiplexer (MPX), 27 is write address control circuit (WAD), 28 is read address control circuit, 2
9 is the control circuit, LOD is odd line data, LED
is even line data, DD is a restoration end signal, ER is an error detection signal, and PD is image data.

Claims (1)

[Claims] 1. In a memory control method for controlling a block line memory for adding image data restored by a data restoration circuit of a facsimile to a recording section, a write operation and a read operation are alternately performed in units of words. First-in-first
multiple line memories consisting of out memories;
A control circuit for controlling a write operation and a read operation of the line memory is provided, and the block data of the plurality of lines restored by the data restoration circuit is word-coded into the plurality of line memories corresponding to the lines constituting the block line. The data for one line is read out in units of words from the sequentially selected line memories among the plurality of line memories and transferred to the recording unit, and the error is detected by the error detection in the data restoration circuit. - A memory control method characterized in that, instead of the data of a block line, data for one line of the immediately preceding block line is repeatedly read out and transferred to the recording section.