JPH03169110A - Differential amplifier having a gain switching circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for increasing a power voltage by avoiding a change in a DC bias current of a load resistor through the gain changeover. CONSTITUTION:A collector current of a 2nd differential amplifier A2 flows to 1st and 2nd load resistors RL1, RL2 via 7th and 8th transistors(TRs) Q7, Q8 in the case of a 1st gain and flows to the 1st and 2nd load resistors RL1, RL2 via 9th and 10th TRs Q9, Q10 in the case of a 2nd gain. Thus, the DC bias current of the load resistors RL1, RL2 by the gain changeover is unchanged. Since no bias voltage is changed, it is not required to change the drive voltage while anticipating the fluctuation of the bias voltage of the next stage in the multi-stage connection circuit.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a differential amplifier having a gain switching circuit configured to switch the gain by selectively connecting at least two sets of differential amplifiers in parallel. It concerns amplifiers. [The problem that the prior art and the invention try to solve [!] ] In a differential amplifier, a power supply is connected to the collectors of a pair of transistors via a load resistor, and an input voltage e is connected to a pair of input terminals.
When l and e2 are given, the collector currents of the pair of transistors flow at a shunt ratio corresponding to the ratio of the input voltages e1 and e2, and a differential output is obtained. Figure 2 shows a conventional gain switching circuit configured to switch the gain by connecting this type of differential amplifier in parallel. This gain switching circuit has first and second input terminals 1 and 2, and first and second output terminals 3.
, 4, an emitter voltage source terminal 5 that provides a voltage ve to flow a constant current, a collector power source terminal 6 that provides a t source voltage VC, and a first bar. It includes a first bias power supply terminal 7 that provides bias voltage Vb1, a second bias power supply terminal 8 that provides second bias voltage Vb2, and a power supply terminal 9 that provides voltage Vp.

A first differential amplifier A1, shown surrounded by a broken line, is connected to first and second transistors Q1a and Q2a, and each base is connected to the first and second input terminals 1 and 2.
The emitters of the first and second transistors Qla and Q2a are connected to each other via resistors R1a and R2a, and the midpoint of this connection is connected to the voltage source terminal 5 via a resistor R5a for providing a constant current.

To configure the second differential amplifier A2, four third transistors Q3a, Q3b, Q3(Q3d) and four fourth transistors Q4a, Q4b, Q4c, Q
4d, and each emitter is connected to R3a, R3b,
R3c, R3d, R4a, R4b%R4c, R4
d, and each midpoint is connected to the emitter voltage source terminal 5 via resistors R5b, R5c, R5d, and R5e for providing a constant current. In FIG. 2, a constant current is supplied to each differential amplifier AI and A2 by the voltage source terminal 5 and resistors R5a to R5e, but the constant current source C
e may be provided.

The first and second transistors Q of the first differential amplifier A1
The collectors of 1a and Q2a are the fifth cascode-connected collectors.
and is connected to the power supply terminal 6 via the sixth transistors Q5 and Q6 and the first and second load resistors RLI and RL2. The first and second output terminals 3, 4 are led out from the collectors of the fifth and sixth transistors Q5, Q6. The third transistor Q that constitutes the second differential amplifier A2
The collectors of transistors 3a to Q3d are connected in common to the emitter of the seventh transistor Q7. The seventh transistor Q7 functions as a switch,
This collector is connected to the collector of the fifth transistor Q5. The collectors of the fourth transistors Q4a to Q4d constituting the second differential amplifier A2 are connected in common and connected to the emitter of the eighth transistor Q8. This eighth transistor Q8 is connected to the transistor Q8. It functions as a switch, and its collector is connected to the collector of the sixth transistor Q6. The emitter of the ninth transistor Q9 functioning as a switch is connected to the common collector line of the third transistors Q3a to Q3d, the collector is connected to the power supply terminal 9, and the base is connected to the second bias power supply terminal 8. ．． Similarly, the emitter of the tenth transistor QIO, which functions as a switch, is connected to the common collector line of the fourth transistors Q4a to Q4d, the collector is connected to the power supply terminal 9, and the base is connected to the second bias power supply terminal 8. ing. An input signal source e is connected between the first input terminal 1 and the ground via a resistor RS1, and a resistor RS2 is connected between the second input terminal 2 and the ground. Of course, an input signal source can also be connected to the second input terminal 2. Note that all of the first to tenth transistors Q1a to Q10 are of the same type (n type). In addition, the first transistor Qla and the second transistor Q2a are arranged in a pair.
, third transistors Q3a to Q3d and fourth transistors Q4a to Q4d, fifth transistor Q5 and sixth transistor Q6, seventh transistor Q7 and eighth transistor Q8, ninth transistor Q9 and tenth transistor Transistor Q10 has the same performance. Also, the resistance R
la and R2a and resistors R3a to R3d and R4a to R4d,
Five resistors R5a to R5e and load resistors RLI and RL2 are set to the same value. In the circuit shown in FIG. 2, if the performances of the first to fourth transistors Q1a to Q4d consisting of 10 transistors are exactly the same, then the first and second differential amplifiers AI
, the ratio of collector currents of A2 is 1:4. By controlling the voltage Vb2 of the terminal 8, the ninth and first
When the seventh and eighth transistors Q9 and QIO are controlled to be turned on and the seventh and eighth transistors Q7 and Q8 are controlled to be turned off, the first differential amplifier A is connected to the load resistors RLI and RL2.
A collector current of only 1 flows, and the voltage drop based on this becomes the output voltage of output terminals 3 and 4. On the other hand, by changing the voltage Vb2 of the terminal 8, the seventh and eighth transistors Q7
, Q8 are turned on, and the ninth and tenth transistors Q9 and Q10 are turned on, the sum of the collector currents of the first and second differential amplifiers A1 and A2 becomes equal to the load resistance R.
Flows to L1 and RL2. The current value at this time is five times the current value when the seventh and eighth transistors Q7 and Q8 are off. Therefore, the seventh and eighth transistors Q7,
If the gain when Q8 is 1, then the gain when the seventh and eighth transistors Q7 and Q8 are on is 5. This circuit has the feature that there is little frequency band change due to gain switching. However, in this circuit, the load resistance R
Since the gain is switched by switching the currents flowing through L1 and RL2, the DC bias currents flowing through load resistors RL1 and RL2 change simultaneously. If the DC bias current changes, the output DC bias voltage will also change, and if a differential amplifier is configured in multiple stages, the input bias voltage of the subsequent stage will also change. Therefore, the drive voltage (bias voltage) must be changed in anticipation of changes in the bias voltage.

In order to suppress changes in DC bias current due to gain switching, the fifth and sixth transistors Q are connected as shown in FIG.
5, the collector of Q6 and the first and second load resistors RLI
, RL2, the eleventh and twelfth transistors Q
11 and Q12 are connected to each other, and further, a common connection line of the collectors of the ninth and tenth transistors Q9 and QIQ is connected to the first and second load resistors RL1 and RL2 via resistors RD1 and RD2, respectively. 13th and 14th
transistors Q13 and Q14 are connected, and the 11th to 1st transistors are connected.
Japanese Patent Laid-Open No. 1-29044 proposes connecting the bases of the four transistors Q11 to Q14 to the voltage source terminal 10, respectively. In the circuit shown in FIG. 3, the collector currents including the signal currents in the collectors of the ninth and tenth transistors Q9 and Q10 are combined into a DC component, and the bases of the thirteenth and fourteenth transistors Q13 and Q14 are By making the potentials the same, the DC component is divided into 172 parts and the first and second load resistors RLI, R. Flow to L2. As a result, even if the gain is changed, the DC bias current does not change. but,
The gain switching circuit shown in FIG. 3 has the disadvantage that the number of parts is large, and the eleventh and twelfth transistors Q11, Q
12, the disadvantage is that the voltage supplied to the power supply terminal 6 must be set high. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a differential amplifier having a gain switching circuit that can reduce changes in DC bias current due to gain switching with a relatively simple circuit and that does not require increasing the power supply voltage. There is a particular thing. [Means for Solving the Problem] The present invention for achieving the above object is as follows:
Referring to the reference numerals in the figure, the first and second input terminals 1 and 2, and the base or gate of the first input terminal 1
the first transistors Q1a to QIC connected to the second input terminal 2; the second transistors Q2a to Q2c whose bases or gates are connected to the second input terminal 2;
constant current sources R5a to R5C connected to the midpoint of connecting the emitters or sources of the transistors Q2a to Q2C; and a third constant current source R5a to R5C whose base or gate is connected to the first input terminal 1. Transistor Q3a
, Q3b, and the base or gate is connected to the second input terminal 2.
the emitters and sources of the third transistors Q3a and Q3b and the emitters or sources of the fourth transistors Q4a and Q4b are connected to constant current sources R5d and R5e, and a fifth transistor Q whose emitter or source is connected to the collector or drain of the first transistors Q1a to Q1C.
5, and the emitter or source of the second transistor Q
A sixth transistor Q6 connected to the collector or drain of 2a to Q2C, and the fifth transistor Q
A first load resistor RL1 connected between the collector or drain of the sixth transistor Q6 and the power supply terminal 6, and a second load resistor RL1 connected between the collector or drain of the sixth transistor Q6 and the power supply terminal 6. a second load resistor RL2 connected between the load resistor RL2 and the power supply terminal 6; and a second load resistor RL2 connected between the collector or drain of the fifth transistor Q5 and the first load resistor RL1. a first output terminal 3 whose emitter or source is connected between the collector or drain of the sixth transistor Q6 and the second load resistor RL2; a seventh transistor Q7 whose collector or drain is connected to the collector or drain of the third transistor Q3a, Q3b and whose emitter or source is connected to the collector or drain of the fifth transistor Q5; an eighth transistor Q8 whose collector or drain is connected to the collector or drain of Q4b and whose collector or drain is connected to the collector or drain of the sixth transistor Q6; and whose emitter or source is the collector of the third transistor Q3a, Q3b. or a ninth transistor Q9 whose collector or drain is connected to the collector or drain of the sixth transistor Q6, and whose emitter or source is connected to the fourth transistor Q4a, Q4.
a tenth transistor Q10 connected to the collector or drain of the fifth transistor Q5, and whose collector or drain is connected to the collector or drain of the fifth transistor Q5; and the fifth, sixth, seventh and eighth transistors Q5. ,
a first bias power supply terminal 7 connected to the bases or gates of Q6, Q7, and Q8;
a second bias power supply terminal 8 connected to the bases or gates of the transistors Q9, Q10; The ninth and tenth transistors Q9 and Q1G are turned off and the seventh and eighth transistors Q7 and Q8 are turned on, or the ninth and tenth transistors Q9 and QIO are turned on and the seventh and eighth transistors are turned on simultaneously. 8 transistor Q7,
The present invention relates to a differential amplifier that can perform gain switching by controlling the seventh to tenth transistors so as to control Q8 off. Note that the first to fourth tigers. When using multiple transistors, connect them in parallel to each other.

[Function] According to the present invention, when the collector current of the second differential amplifier A2 is the first gain, the seventh and eighth transistors Q
7, the first and second load resistors RL1 through Q8,
flows to RL2, and also flows to the 9th and 10th at the second gain.
the first and second transistors Q9 and Q10.
The current flows through the load resistances RL1 and RL2. Therefore, the DC bias current of the load resistors RL1 and RL2 does not change due to gain switching. As a result, the bias voltage also does not change. This eliminates the need to change the drive voltage in a multistage connection circuit in anticipation of changes in the bias voltage of the next stage. [Embodiment 2] Next, a gain switching circuit according to an embodiment of the present invention will be described.
This will be explained with reference to the figure. However, in FIG. 1, parts that are substantially the same as those in FIG. 2 are designated by the same reference numerals, and their explanation will be omitted. In FIG. 1, the first differential amplifier A1 includes three first transistors Q1a, Q1b, Q1c, three second transistors Q2a, Q2b, Q2c, and six emitter resistors R1a, R1b, R1C. , R2a, R
2b, Rb3, and three constant t flow source resistors R5a, R
5b and R5c. The emitters of the first and second transistors Q1a-Q1c, Q2a-Q2c are connected to each other via resistors R1a-R1c, R2a-R2c, and each midpoint is connected to a constant 'r4 current source resistor R5a-R.
5c to the terminal 5, each base is connected to the first and second input terminals 1, 2, and each collector is connected to the terminal 5 through the 4c.
f--fifth and sixth transistors Q5, Q6 in series;
is connected to the emitter of Therefore, the first differential amplifier A1 is constructed by connecting three unit differential amplifiers in parallel, and the signal component of one collector current of one unit differential amplifier is I, and the signal component of the collector current of the other unit differential amplifier is I. If the signal division is ■, the signal division of the entire collector current is 3I, and 3
It becomes I. The second differential amplifier A2 consists of two third transistors Q3
a, Q3b, and two fourth transistors Q4a,
Q4b and four emitter resistors R3a, , R3b, R4
a, R4b and two constant current source resistors R5d and R5e
It has the same structure as the second differential amplifier A2 in FIG. 2, except that the number of unit differential amplifiers is half of that in FIG. Note that the second differential amplifier A2 in FIG. 1 is a parallel circuit of two unit differential amplifiers, so the signal distribution of the collector current on one side is 2I, and the signal distribution of the collector current on the other side is 2I. is 2I. The connections of the fifth to eighth transistors Q5 to Q8 in FIG. 1 are the same as in FIG. 2, but the connections of the collectors of the ninth and tenth transistors Q9 and Q10 are completely different. The collector of the ninth transistor Q9 is connected to the collector of the sixth transistor Q6, that is, one end of the second load resistor RL2, and the collector of the tenth transistor QIO is connected to the collector of the fifth transistor Q5, that is, one end of the first load resistor R.
Connected to one end of LI. In the circuit of FIG. 1, the seventh and eighth transistors Q
7, turn off Q8 and turn off the ninth and tenth transistors Q
9, when Q10 is turned on, the first load resistance R
A total of 3■ of the signal distribution of the collector currents of the three first transistors Q1a to Q1c flows through LI, and a total of the collector currents of the two fourth transistors Q4a and Q4b flows through the LI.
Signal component 2■ of stream a is obtained. fourth transistor Q
Since the signal component 2I of the total collector current of transistors 4a and Q4b is in a negative phase relationship with the signal component 3I of the total collector current of the first transistors Q1a to Q1c, the current flowing through the first load resistor RLI After all, 31+21=31-
2I=I. Similarly, for the second load resistance RL2, 3
The signal component 3 of the total collector current of the second transistors Q2a to Q2C and the two third transistors Q3
The signal 2I of the collector current of a and Q3b flows, and in the end, 3I+2I=-3I+2I==■ flows. Regarding the DC component (bias current), since the same bias current Ib flows through the first to fourth transistors Q1a to Q4b, the first and second load resistors RL1,
A bias current of 5lb flows through each RL2. On the other hand, the seventh and eighth transistors Q7. , Q8 is turned on and the ninth and tenth transistors Q9 and QIO are turned off, the three first transistors Q1a to QaC and the two third transistors Q are connected to the first load resistor RL1.
A signal 5■ of the total collector current of 3a to Q3c flows, and three second transistors Q2a to Q2c and two fourth transistors Q4 flow to the second load resistor RL2.
Signal component 5I of total collector current of a, Q4b = -5
I flows.

At this time, the direct current (bias current) flowing through the first and second load resistors RLI and RL2 is 5Ib. Therefore, if the gain when the seventh and eighth transistors Q7 and Q8 are turned off is 1, the gain when they are turned on is 5. On the other hand, the DC bias current is a constant value (5Ib) regardless of the change in gain. [Modifications] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example. (1> In the IUJ!U, the number of transistors in the pair of the first and second differential amplifiers AI and A2 can be varied, and it is also possible to use one transistor for the first to fourth transistors. (2) Another constant current source can be connected in place of the resistors R5a to R5e. (3) The first to tenth transistors Qla to Q10 can be replaced with FETs (t-field effect transistors). (4) Change the voltage of both terminals 7 and 8 in Figure 1 to
, the eighth, ninth, and tenth transistors Q7 to Q10 may be turned on and off. [Effects of the Invention] As explained above, according to the present invention, it is possible to provide a differential amplifier in which the DC bias current does not change even when the gain is switched.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a differential amplifier having a gain switching circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing a differential amplifier having a conventional gain switching circuit. 1.2...Input terminal, 3.4...Output terminal, 5.
... Voltage source terminal, 6... Power supply terminal, 7.8... Bias power supply terminal, Q1a to Q1c... First transistor, Q2a to Q2C... Second transistor, Q3a
, Q3b...Third transistor, Q4a, Q4
b...Fourth transistor, Q5-QIO...Fifth
~10th transistor, RLI, RL2...Load resistance.

Claims (1)

[Scope of Claims] [1] First and second input terminals (1) (2), and a first transistor (Q1a to Q1a) whose base or gate is connected to the first input terminal (1). Q1c), a second transistor (Q2a-Q2c) whose base or gate is connected to the second input terminal (2), an emitter or source of the first transistor (Q1a-Q1c) and the second transistor (Q2a-Q2c), 2 transistors (Q2a to Q2c
) a constant current source (R5a to R5c) connected to the midpoint where the emitter and source of the
transistors (Q3a, Q3b); a fourth transistor (Q4a, Q4b) whose base or gate is connected to the second input terminal (2); and an emitter of the third transistor (Q3a, Q3b). or the source and the fourth transistor (Q4a, Q4b
) and a constant current source (R5d, R5e) connected to the middle point where the emitters or sources of the transistors (R5d, R5e) are connected to each other;
a fifth transistor (Q5) whose emitter or source is connected to the collector or drain of the second transistor (Q2a);
A sixth transistor (Q6) connected to the collector or drain of the fifth transistor (Q2c) and a first transistor connected between the collector or drain of the fifth transistor (Q5) and the power supply terminal (6) a load resistor (RL1); a second load resistor (RL2) connected between the collector or drain of the sixth transistor (Q6) and the power supply terminal (6); and the fifth transistor (Q6). Q5) and the first output terminal (3) connected between the collector or drain of the sixth transistor (Q6) and the first load resistor (RL1), and the collector or drain of the sixth transistor (Q6) and the second The second output resistor (4) connected between the load resistor (RL2) of
), and the emitter or source is the third transistor (
Q3a, Q3b) is connected to the collector or drain of
The collector or drain of the fifth transistor (Q5
) a seventh transistor (Q7) connected to the collector or drain of the fourth transistor (Q4a);
, Q4b), the collector or drain of which is connected to the collector or drain of the sixth transistor (Q6); and the emitter or source of the third transistor (Q6). (Q3a
, Q3b), the collector or drain of which is connected to the collector or drain of the sixth transistor (Q6); and the emitter or source of the fourth transistor (Q6). (Q4a
, Q4b) and whose collector or drain is connected to the collector or drain of the fifth transistor (Q5); and the first bias power supply terminal (7) connected to the base or gate of the eighth transistor (Q5, Q6, Q7, Q8), respectively.
); and a second bias power terminal (8) connected to the bases or gates of the ninth and tenth transistors (Q9, Q10); )(
8), the ninth and tenth transistors (Q9, Q10) are turned off and the seventh and eighth transistors (Q
7, Q8) or at the same time as turning on the ninth and tenth transistors (Q9, Q10).
and a differential amplifier that can perform gain switching by controlling the seventh to tenth transistors so as to turn off the eighth transistor (Q7, Q8).