JPH0316722U

JPH0316722U -

Info

Publication number: JPH0316722U
Application number: JP7863389U
Authority: JP
Priority date: 1989-07-03
Filing date: 1989-07-03
Publication date: 1991-02-19

Description

[Brief explanation of the drawing]

第１図及び第２図は本考案の一実施例を示し、
第１図は要部の回路図、第２図は受光信号の波形
図、第３図はＣ−ＭＯＳ形アンプを示す回路図、
第４図はＣ−ＭＯＳインバータの内部回路と共に
示す従来の同アンプの回路図、第５図は電源電圧
を高く設定した場合におけるＣ−ＭＯＳインバー
タの入出力特性図、第６図は電源電圧をその動作
可能最低電圧と略等しくした場合におけるＣ−Ｍ
ＯＳインバータの入出力特性図、第７図はＣ−Ｍ
ＯＳ形アンプの周波数特性図である。図面中、１１……受光素子、１２……第１の増
幅回路、１３，２２……Ｃ−ＭＯＳインバータ、
１４，２１……抵抗（帰還用インピーダンス素子
）、１６，２４……電流制限抵抗（電流制限手段
）、１７……第１のアナログスイツチ、１８……
積分回路（通信開始検出手段）、２０……第２の
増幅回路、２３……第２のアナログスイツチ（ス
イツチ手段）である。 1 and 2 show an embodiment of the present invention,
Figure 1 is a circuit diagram of the main part, Figure 2 is a waveform diagram of a received light signal, Figure 3 is a circuit diagram showing a C-MOS type amplifier,
Figure 4 is a circuit diagram of the conventional amplifier shown together with the internal circuit of the C-MOS inverter, Figure 5 is an input/output characteristic diagram of the C-MOS inverter when the power supply voltage is set high, and Figure 6 is a diagram showing the input/output characteristics of the C-MOS inverter when the power supply voltage is set high. C-M when set approximately equal to the lowest operable voltage
Input/output characteristic diagram of OS inverter, Figure 7 is C-M
It is a frequency characteristic diagram of an OS type amplifier. In the drawings, 11... light receiving element, 12... first amplifier circuit, 13, 22... C-MOS inverter,
14, 21... Resistor (feedback impedance element), 16, 24... Current limiting resistor (current limiting means), 17... First analog switch, 18...
Integrating circuit (communication start detection means), 20...second amplifier circuit, 23...second analog switch (switching means).

Claims

[Scope of utility model registration request]

a first amplification circuit configured by connecting a feedback impedance element between a light receiving element receiving an optical signal and an input/output of a C-MOS inverter and amplifying a signal from the light receiving element; current limiting means provided in the power supply circuit to limit the inflow current so that the voltage applied to the C-MOS inverter becomes approximately equal to the lowest operable voltage; a second amplifier circuit capable of operating at higher speed than the first amplifier circuit; a communication start detection means for detecting the start of communication based on the output of the first amplifier circuit; and a communication start detection means for detecting the start of communication based on the output of the first amplifier circuit. A receiving circuit for optical communication, comprising a switch means for starting power supply to the second amplifier circuit on the condition that the second amplifier circuit is detected.