JPH03164866A - Hash encoding circuit - Google Patents

Abstract

PURPOSE:To adopt a hash encoding circuit even to the address starting method of a collision treatment by providing a first table to output a hash address by an input key, a second table to output the hash address by the input key and the number of times of collision, and selecting mechanism for an output hash address. CONSTITUTION:When hash address data, which are outputted by the first table 3 according to the input key, executes collision in the search of a hash table, the second table 6 outputs the new hash address data by inputting the key and the number of times for collision. Further, the selecting mechanism of the first and second tables 3 and 6 issues an instruction to select the second table 6. Accordingly, the new hash address can be obtained. As long as the collision is generated, the number of times of collision is counted and inputted by a series of these operations. Thus, the second table 6 can output the new hash address data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hash encoding circuit used in a database management system or the like in an information processing system.

[Conventional technology]

In the conventional hash circuit, as described in Japanese Patent Laid-open No. 63-136223, hash addresses with good randomness are calculated in advance for all input keys, and a table holding the numbers is provided. It was done. Read the contents of the table using the key as an address.

It was configured to use this data as the hash address.

[Problem to be solved by the invention]

In the above conventional technology, for predetermined data such as when only reserved words in a computer program or limited words in an information processing system are expected to be input, randomization is performed when condensing to a key for data indexing. It is possible to generate a valid hash address because it is possible to take into consideration the numerical value, but consideration must be given to data that is not predetermined and that is arbitrarily selected by the user, such as variable names, function names, and lists. There is a problem in that the generated hash addresses may collide on the hash table, and that only the chain method can be applied as a method for dealing with such collisions.

The purpose of the present invention is to generate a new hash address as long as a collision occurs on the hash table.

By creating a selection mechanism between the hash address corresponding to the input key and the newly generated hash address.

An object of the present invention is to provide a hash encoding circuit that can also be applied to the open address method, which is a collision processing method.

[Means to solve the problem]

To achieve the above object, a hash encoding circuit according to the present invention includes a first table that outputs a hash address using an input key as an input value, and a first table that outputs a hash address using an input key as an input value, and a new table that outputs a hash address using the number of collisions between the key and the hash address as an input value. and a second table that outputs hash addresses.

A selection mechanism is provided between the output value of the first table and the output value of the second table, and when the first key is entered manually, the output value of the first table is selected and output as a hash address, and by searching the hash table, When a collision occurs, the number of collisions is given to this hashish encoding circuit, and the output value of the second table can be selected to output the hashish address.As long as a collision occurs on the hashish table, a new This makes it possible to generate a hash address.

[Effect]

The hashish encoding circuit generates a second table by inputting the key and the number of collisions when a collision occurs in the hashish address outputted from the first table by the inputted key. A new hash address is output, and a new hash address is output by instructing the selection mechanism between the output value of the first table and the output value of the second table to select the output value of the second table. As long as a collision occurs, the second table continues to output new hash addresses by counting and inputting the number of collisions.
In addition, separate algorithms are used for the hash function of the first table and the hash function of the second table, or by using a heuristic method, the generation of type 1 and type 2 clusters is determined based on the characteristics of two independent tables. It can be harnessed and suppressed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

FIG. 1 is a block diagram showing an embodiment of a hash encoding circuit according to the present invention. In FIG. 1, 1 is a key register, 2 is a bit shirtful circuit, 3 is a first table, 4 is a bit shirtful circuit, 5 is a selector circuit,
6 is the second table, 7 is the hash address register, 10
is key data, 11 is intermediate key data, 12 is hash address data, 13 is collision number data, 14 is intermediate key data, 15 is hash address data, 16 is selection (No. 1,
17 is hash address data.

This hashed m-bit key is input to the key register 1 and temporarily stored, and the key data 10 output from the key register 1 is stored in the bit shirtful circuits 2 and 4.
connected so that it can be output to. The bit shirtful circuit 2 cuts the inputted m-bit key data 10 to a certain width, for example, from the LSB to the Q pit width in FIG. This circuit reduces the data to Ω bits by calculating according to the following, and is connected so that the data reduced to Ω bits can be outputted to the first table 3 as intermediate key data 11.

The first tenible 3 is stored in advance by calculating a hash address of X bits with good randomness for all values of the input intermediate key data 11, and the intermediate key data 11 is now input. The contents corresponding to the intermediate key are read out, and the hash address of the X bits corresponding to the key data 10 of the key register 1 is changed. This X-bit data is connected so that it can be output to the selector circuit 5 as hash address data 12.

In addition, the Pi1-shirtful circuit 4 inputs the m-bit key data 1o and the X-bit collision count data 13 generated by searching the hash table, and mixes them to reduce the data to Ω-bit data. This reduction method is the same as the bit shirtful circuit 2 described above, and the Ω bit data is connected so as to be outputted to the second table 6 as intermediate key data 14.

The second table 6 has good randomness for all values of the input intermediate key data 14, and X-bit hash addresses having a series different from the hash address series of the first table 3 are calculated in advance. If the intermediate key data 14 is now input, the contents corresponding to the intermediate key are read out and a new hash address is changed in the event of a hash address collision. This X-bit data is connected so that the hash address data can be output to the selector circuit 5 as hash address data 15.

The selector circuit 5 is a selection output circuit for hash address data 12 and hash address data 15, and a selection operation is performed by a selection signal 16 of the hash address data. The X-bit data selected by the selector circuit 16 is connected to be outputted to the X-bit hash address register 17 as hash address data 17, and by temporarily storing the hash address data in this hash address register 17, , can be output as a hash address.

In addition, the number of collisions data 13 is obtained by controlling the key register 1 and the hash address register 7 and by searching the hash table.
The input setting of the selection signal 16 is based on an instruction from a higher-level control circuit (not shown), and the present invention does not specify the configuration of the higher-level control circuit.

Next, the operation shown in FIG. 1 will be explained with reference to FIGS. 2 to 6, with specific numerical values and calculation methods set as follows.

1. The key shall be two characters expressed in JIS code (m
=16).

2. The size of the hash table = 2'' is '7'.

That is, the bit width of the hash address data 12, 15°17 output by the tables 3, 6 and the selector circuit 5:
is 3 bits and takes the value jOl~'6' (x=3)
.

3. The bit shirtful circuit 2 divides the input 16-bit key into 5-bit widths starting from the LSB, performs an exclusive OR on each section, and compresses it into a 5-bit intermediate code (intermediate key data) 11. (m=
5).

4. The bit shirtful circuit 4 outputs the 19-bit data from the LSI 3, with the input 16-bit key as the upper-order and the 3-bit collision count data 13 as the lower-order.
-, and performs an exclusive OR on each section to create a 5-bit intermediate code (intermediate key data) 14
This can be reduced to .

5. Hash function of Table 3: It is assumed that b+(K) hash address data calculated and held using a linear equation by applying the division method.

ho(K) = K mod 7 (K is intermediate key data 11) 6. Hash function in Table 4: h□(K) applies the multiplication method and hash address data is calculated and retained using a linear formula. shall be.

hz (K) = [7X (KX 2)] (K is intermediate key data 14, 2 is the reciprocal of the golden section ratio: 2 = (fish -
-1)/2゜'[]' is a Gauss symbol, '()' is a symbol for extracting the decimal part) In the above configuration, assume a case where a request is made to store the following three sets of keys in the order of occurrence of the keys. .

1, “DO+” 2, “ED” 3, “IF” First, the key: “Do” is temporarily stored in the key register 1, and is sent to the bit shirtful circuit 2, where intermediate key data 11 is output. Fig. 2 is an explanatory diagram showing the calculation process of intermediate key data in the bit/shirtful circuit 2. In Fig. 2, the key sent to the bit/shirtful circuit 2 shown in Fig. 2a is 'Do'. is the second
It is represented by the bit configuration of the JIS code as shown in the figure. In the bit shirtful circuit 2, as shown in Figure 2C, this is divided into 5-bit units, and as shown in Figure 2D, exclusive OR is performed between each section of these 5 bits to obtain a decimal value. '3o' is obtained and output as intermediate key data 11.

The intermediate key data 11: '30' obtained here is sent to table 3. FIG. 3 is an explanatory diagram showing the storage state and index state of hash address data in table 3. The table 3 is configured as shown in FIG.
As shown in Table 3, by indexing using intermediate key data 11: '30', the numerical value '2'' is obtained and output as hash address data 12. Hash address data 12 obtained from this table 3: '2' is sent to the upper control circuit via the selector circuit 5 and the hash address register 7, and the hash table is searched in the upper control circuit as shown in FIG. 2". FIG. 6 is an explanatory diagram showing the storage state of the hash table.

Next, when the key 'ED' is input, the intermediate key data 11 is generated by the bit shirtful circuit 2 in the same way.
: '31' is obtained, and as a result, the number '3' is obtained from the table as shown in Figure 3.
2, and as shown in Figure 6, the upper control circuit sets the key: 'E' to hash address '3' in the hash table.
D' is stored.

Next, when the key: 'IF' is input, the intermediate key data 11: '30' is obtained by the bit shirt full circuit 2, and the numerical value '2' is output from the table 3 as the hash address data 12. However, as shown in FIG. 6, when the hash table is searched by the upper control circuit, it is detected that the key: 'Do' is already filled in the hash address '2' (a collision has occurred). As a result, the upper control circuit inputs the numerical value '1' to the bit shirtful circuit 4 as the number of collisions data 13, and also instructs the hash address data selection signal 16 so that the selector circuit 5 selects the hash address data 15 of the table 6. It is controlled to selectively output as hash address data 17.

At this time, intermediate key data 14 is output from the bit shirtful circuit 4 as follows. FIG. 4 is an explanatory diagram showing the calculation process of intermediate key data of the bit shirtful circuit 4. In FIG. 4, collision count data 13 sent to the bit shirtful circuit 4 shown in FIG. 4a: '1'
The key previously input: 'IF' is represented by a bit configuration as shown in Figure 4. In the bit shirtful circuit 4, this is divided into 5-bit units as shown in FIG. 4C, and these 5 bits are divided as shown in FIG. 4D.
Take the exclusive OR between each intercept of bits and get 2 in decimal value.
2' is obtained and output as intermediate key data 14.

The intermediate key data 14: '22' obtained here is sent to table 6. FIG. 5 is an explanatory diagram showing the storage state and index state of hash address data in table 6. The table 6 is configured as shown in FIG.
As shown in the figure, by indexing using the intermediate key data 14: '22', the numerical value '4' is obtained and output as the hash address data 15. The hash address data 15:'4' obtained from this table 6 is sent to the upper control circuit via the selector circuit 5 and the hash address register 7, and is further sent to the upper control circuit as shown in FIG. 6C. The table is searched and the key: 'IF' is stored at hash address '4'.

According to this embodiment, even if a collision occurs in the hash address data output by the first table 3 due to the input key, the second table 3 can be retrieved by inputting the key and the number of collisions. The table 6 outputs new hash address data, and the first table 3
A new hash address is obtained by instructing the selection mechanism of and second table 6 to select the second table 6, and as long as a collision occurs due to these series of operations, the number of collisions is counted. By inputting the data, the second table 6 can output new hash address data.

In the operation of the embodiment shown in Fig. 1, specific numerical values and calculation methods are set uniquely in Fig. 1 and explained using Figs. 2 to 6. It goes without saying that the hashish encoding circuit can be configured with numerical values and arithmetic methods that are optimal for the target to be used.

(Effects of the Invention) According to the present invention, there are two types of independent tables: a first table that outputs a hash address based on an input key, and a second table that outputs a hash address based on an input key and a collision count value. By providing a table and an output hash address selection mechanism, a new hash address can be output as long as a hash address conflict continues, which has the effect of being applicable to the open address method of the collision handling method. There is.

Furthermore, the hash address is generated by generating an intermediate key using an independent bit/shirtful circuit and by indexing an independent table.

Needless to say, a table can be constructed by using a heuristic method or the like, as well as using different algorithms for hash functions, and these methods have the effect of suppressing the occurrence of type 1 and type 2 clusters.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the hash encoding circuit according to the present invention, FIG. 2 is an explanatory diagram showing the calculation process of intermediate key data of the bit shirtful circuit 2 of FIG.
4 is an explanatory diagram showing the storage state and index state of hash address data in table 3 in FIG. 1, FIG. FIG. 5 is an explanatory diagram showing the storage state and index state of hash address data in table 6 of FIG. 1. FIG. 6 is an explanatory diagram showing the storage state of the hash table of FIG. 1. 1...Key register, 2...Bit shirtful circuit, 3...First table. 4... Bit shirtful circuit, 5... Selector circuit, 6... Second table. 7... Hatshu address register. 13...Collision number data, 16...Selection signal. Compilation Map Compilation Map d 栴仝口I ■Eco (22--10 Not Existed) No.

Claims (1)

[Claims] 1. A first table that holds hash addresses corresponding to input keys, and a hash address that corresponds to the input key and the collision count value that is input when a collision occurs due to the hash table search. A hash encoding circuit comprising: a second table; and means for selecting and outputting the read contents of the first table and the read contents of the second table.