JPH03164842A - Memory controller - Google Patents

Abstract

PURPOSE:To efficiently use a memory space in accordance with contents to be processed by generating the address of an extended memory in accordance with the number of the bank constituted on the extended memory, the capacity of the bank address space, and an address signal outputted from a CPU. CONSTITUTION:When the address of the address signal outputted from the CPU is in the bank address space and bank switching is selected, a memory switching control means 16 switches the memory from a main memory 2 to an extended memory 3. An upper address generating means 17 generates the upper address of the extended memory in accordance with the number of the bank constituted on the extended memory, the capacity of the bank address space, and the upper address signal of the address signal outputted from the CPU. Thus, the memory space is efficiently used in accordance with processing contents.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a memory control device for controlling memory bank switching in a microcomputer.

<telConventional Technology In a microcomputer, the memory space that can be directly accessed by the CPU is determined by the number of bits of the address signal output from the CPU.For example, an 8-bit microprocessor generally uses a 16-bit address signal. Yes, and a maximum address space of 64 KB is used as memory space.

Also, when accessing memory in a space wider than the address space provided by the address signal output from the CPU,
So-called bank switching control is performed in which an extended memory provided separately from the main memory is used in place of the main memory, or the extended memory is accessed via a specific address range of the main memory.

FIG. 8 shows an example of a circuit for performing conventional bank switching control.

In this example, the bank address space to open the extended memory bank in the main memory address space is $E000 to $E.
In this example, it is set to FFF. In the same figure, AND
Gates 5-7, N.

The R gate 8 and the AND gate 9 are logic circuits that detect a state in which the four bits A15 to A12 of the address signal output by the CPU are 1110, that is, the designated address is $Exxx. In addition, 13 is the WR output by CPU1
*This is a flip-flop that stores 1-bit data at the timing of a signal (active low write signal), and is cleared when banks are switched, and reset when banks are not switched. Therefore flip-flop 1
3 is in the set state and when EOOO to $EFFF are addressed, the output of the NAND gate 10 goes to the "L" level and the extended memory 3 is selected. On the other hand, at this time, the output of the OR gate 12 becomes 'H' level, and the main memory 2 is not selected.Here, C8* is an active low chip select signal.Flip-flop 13
is in the reset state, or $E000~$EF
When a space other than FFF is addressed, the output of the NOR gate 10 becomes "H" level and the extended memory 3 is not selected. Furthermore, if the address decoder 4 detects that the memory space of the main memory 2 is addressed in this state, the output of the OR gate 12 becomes "L3" and the output of the OR gate 12 becomes "L3", and the main Memory 2 will be selected.

(e) Problem to be Solved by the Invention However, in such a conventional memory control device that performs bank switching, the bank address and bank size (capacity) for opening the extended memory bank in the address space of the main memory are determined in advance. It was fixed by the designed circuit and could not be changed by the program. Therefore, there is a problem that the degree of freedom in memory mapping is low, and the burden on the program increases depending on the type and amount of data to be handled.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control device that solves the above-mentioned problem by allowing a bank address space for opening a bank of an extended memory to be freely set in the address space of a main memory.

(d) Means for Solving the Problems The memory control device of the present invention provides an expansion of the address space of the main memory in a microcomputer equipped with a CPU, a main memory and an expansion memory connected to a bus of the CPU. bank address space storage means for storing a bank address space for opening a memory bank; bank switching selection storage means for storing whether or not bank switching is selected; A memory switching control means that switches the memory selection from the main memory to the extended memory when is selected, and the address of the extended memory is determined from the number of the bank configured on the extended memory, the capacity of the bank address space, and the address signal output from the CPU. and address generation means for generating the address.

(81 Action) The configuration of the memory control device of the present invention is shown in Figure 1. Examples of bank address spaces are shown in Figures 2 (A) and (B).

As shown in FIG. 1, bank address space storage means 14
stores the specified bank address space. For example, as shown in Figure 2 (A), $7,000 to $7 FFF
A 4KB space is stored as a bank address space.

Bank switching selection storage means 15 stores the selection state of whether or not to perform bank switching. The memory switching control means 16 is a CP
When the address signal output by U is in the bank address space and bank switching is selected, the memory selection is switched from the main memory to the extended memory. The upper address generation means 17 generates the upper address of the extended memory from the number of the bank configured on the extended memory, the capacity of the bank address space, and the upper address signal of the address signal output from the CPU.

Since the bank address space can be set arbitrarily in this way, for example, the bank address space shown in Figure 2 (A) can be moved to 4KB from $EOOO to $EFFF, or the bank address space shown in Figure 2 (B) can be moved to 4 KB from $EOOO to $EFFF. from $7000 to $8FF
It is also possible to change the bank size, such as making 8KB of F the bank address space.

(f) Embodiment A block diagram of a memory control device according to an embodiment of the present invention is shown in FIG.
are connected. Also, the address bus A15 of CPU1
AO is given as an address signal for the main memory 2, and the upper 4 bits (A15 to A12) are given to the memory control device 18.
The lower 12 bits A11-AO are applied to the lower addresses MAII-MAO of the extended memory 3. When the memory control device 18 should select the main memory 2, it selects C31*.
C32* is activated when expansion memory 3 is to be selected. Further, the upper address signals MA22 to MA12 are applied to the extended memory 3.

Next, the configuration of the memory control device 18 is shown in FIGS. 4 and 5.
As shown in the figure.

FIG. 4 shows a logic circuit of the memory control device 18 shown in FIG. 3, which includes circuits corresponding to bank address space storage means, bank switching selection storage means, and memory switching control means according to the present invention. In this example, the location of the bank address space is set in 4KB units, that is, the upper 4 bits A15 to A12 of the address signal output by the CPU, and the capacity (bank size) of the bank address space is set to 4KB, 8KB, 16KB, 32KB, or 64KB. It can be set to either. 21~ in Figure 4
24 is a 4-bit flip-flop for storing the position of the bank address space, and 29 to 32 are 4-bit flip-flops for storing the bank size, which correspond to the bank address space storage means according to the present invention. do.

The flip-flops 21 to 24 are OR gates 38, which will be described later.
When the output of the data signal becomes “L” level, the data signal D7~
Flip-flops 29 to 32 store the 4-bit data of D4, and the output output of an OR gate 39, which will be described later, is
- When the level reaches t, m, 4-bit data of D7 to D4 is stored. A flip-flop 41 corresponds to the bank switching selection storage means of the present invention, and stores the DO state of the data signal when the output of the OR gate 40 becomes "L" level. When selecting bank switching, this flip-flop 41 is used.

EX-NOR gates 25 to 28 correspond to the upper 4 bits A15 to A12 of the address signal and the flip-flop 21, respectively.
When the state stored in .about.24 matches, an "H" level is output. On the other hand, if the contents of flip-flops 29 to 32 are expressed as 4-bit data, the bank size is 4K.
B, 0000.8KB, 0001.1
0011 when it is 6KB.011 when it is 32KB
1 and 64 KB, 1111 is stored. Therefore, when the bank size is 4KB, the address signal A
Only when the states of the flip-flops 15 to A12 all match the states of the flip-flops 21 to 24, the outputs of the OR gates 33 to 36 all become "H", and the output of the AND gate 9 becomes "H". Also, the bank size is set to 8KB. EX when it is
-N.

Since the output of the OR gate 36 is "H" regardless of the output of the R gate 28, the upper three bits of the address A15 to A
13 and flip-flops 21 to 23 match, AND
The output of gate 23 becomes “Ho”.Similarly, if the bank size is set to 16KB, OR gates 35 and 3
Since the output of A15.6 is always "H", the upper two bits of the address signal A15. A14 and flip-flop 21.22
If only the two match, the output of the AND gate 9 becomes "H".

Furthermore, if the bank size is set to 64 KB, the output of the AND gate will always be "H" regardless of the address signal. For example, the 4-bit data of flip-flops 21-24 is 1100, and the data of flip-flops 29-32 is 1100.
The 4-bit data is 0001, that is, bank size 8.
When set to KB, the CPU address signal is $C.
When it is XXX or $DXXX, that is, $C000
When the address of ~$DFFF is selected, the output of the AND gate 9 becomes "H".

When bank switching is selected, the output of the flip-flop 41 is "H", so when the output of the AND gate 9 becomes "H", the output of the NAND gate 1O becomes "L", and the expansion memory 3 is selected. At this time, the output of the inverter 11 becomes "H" and the output of the OR gate 12 becomes "Hl", so the main memory 2 is not selected.

In FIG. 4, the address decoder 20 is the main memory 2.
This is a circuit that outputs a selection signal when the address signal assigned to the At some point, the output is set to "L" level. Therefore, main memory 2 is selected in the range of $1000 to $FFFF and when no extended memory is selected.

The address decoder 37 includes the flip-flops 21 to 2.
This circuit detects the write address when writing data to 4.29 to 32.41 and other flip-flops to be described later. For example, the address signal is 5otoo
When the address signal is $0101, the ADH is set to "L" level (active), and when the address signal is $0101, the SIZ* is set to "L"
level, and when the address signal is $0102, C33* is set to "L" level. Therefore, when an instruction to write data 1100xxxx to address $0100 is executed, the ADR* signal and WR* signal become "L" level. Therefore, the output of the OR gate 38 becomes "L" and 1100 is written to the flip-flops 21 to 24. Also, when the instruction to write 0O01xxxx to address $0101 is executed, the signals SIZ* and WR* go to "L" level. Therefore, the output of the OR gate 39 becomes L'' and 0001 is written into the flip-flops 29-32. Furthermore, when the instruction to write XXXXX 1 to address $0102 is executed, the signal C33* and the WR signal go to "L" level, and the output of OR gate 40 goes to "L" level, so flip-flop 41 is set. Ru.

FIG. 5 shows a signal sIz in FIG. 0, which is a logic circuit corresponding to the upper address generation means according to the present invention in the memory control device 18 shown in FIG.

~5IZ3 is the flip-flop 29~3 shown in FIG.
This is a bank size data signal output from 2. Further, signals NUM1* and NUM2* in FIG. 5 are signals output from the address decoder 37 shown in FIG. Further, in the figure, 66 to 76 are flip-flops, respectively, and when the output of the OR gate 77 becomes "L", the flip-flops 69 to 76 switch to the data signals D7 to D.
Store the contents of O. Also, the output of the OR gate 78 is “L”
'' level, flip-flops 66 to 68 are D
2-Memorize the contents of DO. For example NUM1* and N
If the address decoder 37 shown in FIG. 4 is configured so that UM2* is output when addresses $0103 and $0104 are accessed, then if data is written to address $0103, the data D7 to DO will be output. It is set in flip-flops 69-76. Furthermore, if data is written to address $0104, the contents of D2-DO are set in flip-flops 66-68.

In the figure, NAND gates 50-53 selectively output the upper 4 bits A15-A12 of the address signal as expansion memory address signals MA15-MAI2 in accordance with bank size data 5IZ3-5rzo. Also NA
ND gates 58 to 61 receive bank size data 5rZ3 to
5rzo, the contents of flip-flops 173-76 are output as addresses MA15-MA12 of the extended memory. For example, when 5IZ3-5IZO is 0000 (bank size 4 KB), the outputs of inverters 54-57 go to "H" level, and the inverted signals of flip-flops 73-76 are output from NAND gates 58-61. On the other hand, since the outputs of NAND gates 50-53 are all at H'' level, the contents of flip-flops 73-76 are output as they are to NAND gates 62-65.

Also, for example, when 5IZ3 to 5IZO are 0001 (when the bank size is 8 KB), the contents of the flip-flops 74 to 76 are output as they are to the NAND gates 63 to 65, but the output of the inverter 57 is at "L" level, so the NOR gate 61 The output is always at "H" level. On the other hand, since the NAND gate 53 outputs an inverted signal of A12, the NAND gate 65 outputs A12.

At this time, the flip-flop 76 is disabled, so the bank address of the 10-bit binary code set in the flip-flops 66 to 75 is the address MA22 of the extended memory.
~MA13. For example, signal 5IZ3
~5 When IZO is 0011 (bank size 16 KB), the outputs of flip-flops 75 and 76 are disabled and address signals A13 and A12 are enabled. That is, the extended memory address signal MA13. MA12 receives the CPU address signal A13. A12 is output and MA
A 9-bit binary code representing the bank position set in the flip-flops 66-74 is outputted to 22-MA14.

Next, we will show a simple example of a specific processing program using expanded memory.

Fig. 7 is a flowchart showing the processing procedure of the CPU;
The figure shows a memory map.

As shown in FIG. 6, a program is written from $2000 in the main memory, and 8 KB from $C000 to $DFFF is set as a bank address space. Banks are allocated to the extended memory in units of 8 KB.

As shown in FIG. 7, first, $0000 is set as the bank address (starting address of the bank address space) (nl). Specifically, as described above, 1too is set in the flip-flops 21 to 24 shown in FIG. 4 by writing 1100XXXX to address $0100.

Next, set 8KB as the bank size (n2). Specifically, as mentioned above, 0OOIXX is located at address $0101.
By writing XX, 0001 is set in the flip-flops 29 to 32 shown in FIG.

Next, the initial value 0 is input to BN as a bank fish, and the bank limit indicated by BN is set (n3→n4). Specifically, as described above, by writing bank-wide binary codes in addresses $0103 and $0104, flip-flops 66 to 66 of the flip-flops 66 to 76 shown in FIG.
Set the bank magnet to 75. Next, input the initial value 0 to C as a loop counter and wait for key input (n5-n6
).

If there is a key input and the key is not the end key, the key input data is stored in the extended memory (n7-n
8). Next, increment the counter C and repeat the above process until the value reaches 8192 (8KB) (n 9-=n 10-n 6...). After writing 8KB worth of data, write bank NaBN. Increment and reset the bank magnetism (nil→n4...).

In this way, input data can be sequentially written into the extended memory.

In the embodiment shown above, there was one bank address space for opening the extended memory bank in the main memory address space, but the number of extended memory channels is increased and each channel is stored on the main memory. Setting the bank address space can be done in a similar manner.

In addition, in the embodiment, the minimum capacity of the bank address space is set to 4.
Although the upper address of the memory is generated from the upper address of the CPU address and the bank address as the KB, the present invention is not limited to this. (g) Effect of the Invention According to this invention, the address space of the main memory can be Since the location and size of the bank address space for opening banks in the extended memory can be freely set by a program, the memory space can be used efficiently depending on the content to be processed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of the present invention. Figure 2 (A)
, (B) is an explanatory diagram of the operation of the memory control device of the present invention. FIG. 3 is a block diagram showing the configuration of a microcomputer using a memory control device according to an embodiment of the present invention. 4 and 5 are detailed logic circuit diagrams of the memory control device. FIGS. 6 and 7 are flowcharts showing an example of the memory map of the device and the processing procedure of the CPU. FIG. 8 is a logic circuit diagram of a conventional memory control device.

Claims (1)

[Claims] (1) In a microcomputer equipped with a CPU, a main memory, and an extended memory connected to the bus of this CPU, a bank address space memory that stores a bank address space for opening a bank of extended memory in the address space of the main memory. means for storing memory selection from the main memory to the expanded memory when the address signal output from the CPU is in the bank address space and the bank switching is selected; A memory control device comprising memory switching control means for switching, and address generation means for generating an address of the extended memory from the number of a bank configured on the extended memory, the capacity of the bank address space, and an address signal output from a CPU.