JPH03163859A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH03163859A JPH03163859A JP30400589A JP30400589A JPH03163859A JP H03163859 A JPH03163859 A JP H03163859A JP 30400589 A JP30400589 A JP 30400589A JP 30400589 A JP30400589 A JP 30400589A JP H03163859 A JPH03163859 A JP H03163859A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- connector
- islands
- island
- die bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000001816 cooling Methods 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000008602 contraction Effects 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 4
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置用リードフレームに関し、特に、
アイランドの構造に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a lead frame for a semiconductor device, and in particular,
Concerning the structure of the island.
従来の半導体用リードフレームは、アイランドの形状は
第４図、第５図に示す如く、１つの部分で楕或されてい
る。In a conventional semiconductor lead frame, the shape of the island is elliptical in one part, as shown in FIGS. 4 and 5.
上述した従来の半導体装置用リードフレームに於いては
、第４図，第５図に示すアイランド１はチップダイボン
ディング時、ダイボンディング後の加熱冷却作用により
膨張収縮を行う際にチップ３とアイランド１の伸縮が異
なる為チップにクラックが入り易いという欠点がある。In the conventional lead frame for a semiconductor device described above, the island 1 shown in FIGS. 4 and 5 is connected to the chip 3 and the island 1 when the island 1 expands and contracts due to the heating and cooling action after die bonding during chip die bonding. The disadvantage is that the chips are prone to cracks because they expand and contract differently.
本発明の目的は、チップダイボンディング時やダイボン
ディング後の加熱、冷却作用により生ずるチップとアイ
ランド間に生ずるストレスを低減することができ、チッ
プのクラック発生を少なくすることができる半導体装置
用リードフレームを提供することにある。An object of the present invention is to provide a lead frame for a semiconductor device that can reduce the stress generated between a chip and an island during chip die bonding and due to heating and cooling effects after die bonding, and can reduce the occurrence of cracks in the chip. Our goal is to provide the following.
本発明の半導体装置用リードフレームは、アイランドが
チップダイボンディング時やダイボンディング後の加熱
冷却作用によって、膨張を生じた際に、チップの膨張に
アイランドが追従し、両者の間にストレスを生じない構
造として、チップ接合部であるアイランドを二つに分割
し、そして分割したアイランドは伸縮自在な接続子によ
り接続されている。この接続子は、上記熱膨張によって
分割されたアイランド間が広がるのに追従する弾性変形
部を構成している。In the lead frame for a semiconductor device of the present invention, when the island expands during chip die bonding or due to heating and cooling action after die bonding, the island follows the expansion of the chip, and no stress is generated between the two. As a structure, the island, which is the chip joint, is divided into two, and the divided islands are connected by a flexible connector. This connector constitutes an elastic deformation portion that follows the expansion of the islands divided by the thermal expansion.
次に、本発明について図面を参照して説明する。第１図
，第３図はそれぞれ本発明の一実施例をの斜視図および
その要部の縦断面図である。Next, the present invention will be explained with reference to the drawings. FIGS. 1 and 3 are a perspective view and a vertical sectional view of an essential part of an embodiment of the present invention, respectively.
第３図において二つのアイランド１．２にその間をつな
ぐ接続子３が設けてある。このアイランドにチップ４を
金−シリコン共晶合金方法あるいは、エボキシ系樹脂等
による方法でダイボンディングが行われる。接続子３に
は、ダイボンディング時にチップ４を接合しないように
コイニングが施され第３図に示すように１段低くなって
いる。In FIG. 3, two islands 1.2 are provided with a connector 3 connecting them. Die bonding of the chip 4 to this island is performed using a gold-silicon eutectic alloy method or a method using an epoxy resin or the like. The connector 3 is coined so as not to bond the chip 4 during die bonding, and is lowered by one step as shown in FIG.
第３図において、ダイボンディング時やダイボン後の加
熱・冷却作用により、チップ４の伸縮にアイランド１．
２がその間の伸縮自在な接続子３にて追従可能となりチ
ップ４とアイランド１，２間に生じるストレスを低減す
る。In FIG. 3, island 1.
2 can be followed by the expandable connector 3 between them, reducing the stress generated between the chip 4 and the islands 1 and 2.
第２図は本発明の他の実施例の斜睨図であり、その要部
の縦断面図は第３図と同様てある。本第２の実益例にお
いてもタイホンテインク方法およびダイボンディング時
やダイポンディング後の加熱冷却作用に対する動作は第
１の実施例と同様でる。この実施例では、アイランド１
，２間をつなぐ接続子３を複数個有することにより、接
続子３の変形を防１ヒできる利点かある。FIG. 2 is a perspective view of another embodiment of the present invention, and a longitudinal sectional view of the main parts thereof is the same as FIG. 3. In the second practical example as well, the ink method and the operation for heating and cooling during die bonding and after die bonding are the same as in the first embodiment. In this example, island 1
, 2 has the advantage of preventing deformation of the connectors 3.
ｒ発明の効果〕
以上説明したように本発明は、半導体装置用リー１・ノ
レーｌ＼に於いて、ア，イランドか二一）の部分から柘
成され、その間をつなぐ接続子が伸縮自７１′な形状を
有している為、チップダイボンディング時やタイボン後
の加然・冷却作用によるチップの伸縮に追従可能となり
チップとアイランド間に生じるストレスを低減できる効
果がある。[Effects of the Invention] As explained above, the present invention is constructed from the A, Iland or 21) parts in the Lee 1 and Norley \ for semiconductor devices, and the connector connecting therebetween is a telescopic 71. '' shape, it is possible to follow the expansion and contraction of the chip during chip die bonding and due to the cooling effect after tie bonding, and has the effect of reducing the stress generated between the chip and the island.
第１図は本発明の−実施例の斜視口、第２図は本発明の
他の実施例の斜視図、第３図は第１図、第２図に示す実
施例の要部の縦断面図、第４図は従来の半導体装置用リ
ード゛フレームの一例の斜視図、第５図は第４図に示す
従来例の要部の縦断面図である。
１，２・・・アイランド、３・・・接続子、４・・・チ
ップ。Fig. 1 is a perspective view of an embodiment of the present invention, Fig. 2 is a perspective view of another embodiment of the invention, and Fig. 3 is a vertical cross-section of the main part of the embodiment shown in Figs. 1 and 2. 4 is a perspective view of an example of a conventional lead frame for a semiconductor device, and FIG. 5 is a longitudinal cross-sectional view of a main part of the conventional example shown in FIG. 4. 1, 2... Island, 3... Connector, 4... Chip.
Claims (1)
フレームに於いて、アイランドが二つの部分から構成さ
れ、前記二つの部分が伸縮自在な形状を有する接続子に
より接続されていることを特徴とするリードフレーム。A lead frame for a semiconductor device used in a resin-sealed semiconductor device is characterized in that the island is composed of two parts, and the two parts are connected by a connector having an expandable shape. Lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30400589A JPH03163859A (en) | 1989-11-21 | 1989-11-21 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30400589A JPH03163859A (en) | 1989-11-21 | 1989-11-21 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03163859A true JPH03163859A (en) | 1991-07-15 |
Family
ID=17927914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30400589A Pending JPH03163859A (en) | 1989-11-21 | 1989-11-21 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03163859A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281566B1 (en) * | 1996-09-30 | 2001-08-28 | Sgs-Thomson Microelectronics S.R.L. | Plastic package for electronic devices |
-
1989
- 1989-11-21 JP JP30400589A patent/JPH03163859A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281566B1 (en) * | 1996-09-30 | 2001-08-28 | Sgs-Thomson Microelectronics S.R.L. | Plastic package for electronic devices |
| EP0833382B1 (en) * | 1996-09-30 | 2005-11-30 | STMicroelectronics S.r.l. | Plastic package for electronic devices |
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