JPH03160544A - Direct memory access control system - Google Patents

Abstract

PURPOSE:To prevent the processing of a processor from being delayed by accessing a memory by the processor regardless of data transfer between an input/output device and the memory. CONSTITUTION:A processor 5 sets a reference address to an address designating means 8 and instructs data transmission to an input/output device 10. Otherwise, after instructing the reception of the data, the data transfer between a memory 7 and the input/output device 10 is executed through a data bus 11. Accordingly, the processor 5 can execute the data transfer with the memory 7 through a data bus 12. Thus, when the processor 5 executes plural jobs, the memory 7 can be accessed even in the case that the data transfer between the input/output device 10 and the memory 7 by one job, and accordingly, the processing of the other job is prevented from being delayed.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems Effects of the invention [Summary] Data between input/output devices and memory Regarding the direct memory access control method that allows the processor to access memory regardless of the transfer, the purpose is to prevent delays in processor processing, and to transfer data under the control of the processor and the processor. A memory that has multiple ports that correspond to human output devices and multiple data buses, and that transfers data individually to the processor and input/output devices, and a memory that handles bus usage in response to bus usage requests sent by human output devices. In a system equipped with a bus allocation circuit that sends a permission allocation signal, the address of write/read data is specified by incrementing or decrementing the address of the write/read data in response to the allocation signal, based on the address set by the processor. Addressing means are provided, and the processor is configured to:
An instruction means for instructing the setting of a reference address is provided, and after the processor sets the reference address in the memory addressing means according to the instruction of the instruction means, the addressing means sends out the reference address regardless of the processor's access to the memory. Depending on the address, the data sent out by the input/output device specified by the allocation signal is sequentially written into the memory, or the data sequentially read from the memory is written into the input/output device specified by the allocation signal.

[Industrial application field]

The present invention relates to a system that executes data transfer between a memory and an input/output device in a direct memory access (hereinafter abbreviated as DMA) mode, and in particular, the present invention relates to a system that executes data transfer between a memory and an input/output device in a direct memory access (hereinafter abbreviated as DMA) mode. The present invention relates to a direct memory access control method that enables direct memory access.

In a system operating in DMA mode, when data is transferred between memory and an input/output device, the processor activates the DMA control circuit, and thereafter the DMA control circuit is controlled without the need for processor intervention. The data transfer is now executed.

By the way, when the DMA control circuit transfers data between the memory and the human output device, the cycle in which the DMA control circuit accesses the memory stops the processor from accessing the memory, which reduces the processing speed of the processor. It is necessary to prevent such a decrease in processing speed.

[Conventional technology]

FIG. 4 is a block diagram illustrating an example of the prior art.

The processor 1 stores in the internal register of the DMA control circuit 3 the start address of the area where data to be read from the memory 2 is stored or the area where the data to be written to the memory 2 is stored;
After setting the address of the human output device 4 and the number of words to be transferred, etc.
Activate the DM AffilJ control circuit 3.

The activated DMA control circuit 3 refers to the start address of the memory 2 set in the internal register and the address of the input/output device 4, and determines the start address of the storage area of the data to be transferred existing in the memory 2 and the number of words to be transferred. or when the start address of the memory area storing the data to be written to the memory 2 and the number of transferred words are recognized, the data of the specified number of words is sequentially read from the specified address of the memory 2, and the input/output device 4 or input/output device W
The data of 4 is sequentially read out in the designated number of words, transferred to the memory 2, and stored in the designated address area of the memory 2.

Figure 5 is a time chart explaining the operation of Figure 4. Since the processor 1 and the DMA control device 3 both share one bus, they cannot access the memory 2 at the same time. Therefore, the processor 1 creates a cycle in which the DMA control circuit 3 accesses the memory 2, and for example, accesses the memory 2 alternately.

That is, in Figure 5, if time is plotted on the horizontal axis, Figure 5 (
As shown in a), when processor 1 only accesses memory 2, C P tJ■, CPU■, cpu
As shown in ■ and CPU■, the memory 2 is sequentially accessed to execute processing, but when the DMA control circuit 3 operates,
As shown in FIG. 5(b), the processor 1 is the CPU■~■
The DMA control circuit 3 accesses the memory 2 in cycles shown in DMA (1) to (4).

[Problem to be solved by the invention]

Since the processor 1 operates by reading a program from the memory 2 and also stores data to be processed in the memory 2, as described above, in data transfer using the conventional DMA control circuit 3, the DMA control circuit 3 While accessing the memory 2, the processing of the processor l is forced to wait.

Therefore, when the processor 1 is executing one job by a single task, the delay in the processing of the processor 1 is not noticeable even if the DMA control circuit 3 operates, but when executing multiple jobs, the delay in the processing of the processor 1 is not noticeable. When the DMA control circuit 3 is activated for one job, there is a problem that delays in processing other jobs become noticeable.

In view of these problems, the present invention enables the processor 1 to access the memory 2 regardless of data transfer between the input/output device 4 and the memory 2, and prevents delays in the processing of the processor 1. It is intended to be.

[Means to solve the problem] FIG. 1 is a block diagram illustrating the principle of the present invention.

Based on the instruction from the instruction means 6, the processor 5 writes the start address of the area where the data to be transferred to the input/output device IO is stored, or the data to be sent by the input/output device 10, to the addressing means 8 of the memory 7. Set the start address of the area to be inserted as the reference address. Further, the memory 7 is provided with a port for connecting the data bus 12 to the processor 5 and a port for connecting the data bus 11 to the input/output device IO, respectively. Data transfers can be performed independently and individually.

When transferring data stored in the memory 7 to the input/output device 10, the processor 5 sets a reference address in the addressing stage 8 and instructs the input/output device 10 to receive the data, as described above.

When the human output device 10 is instructed to receive data, the memory 7
For example, the output enable signal OE is kept off, and a bus use request is sent to the bus allocation circuit 9. When the data bus 11 between the input/output device 10 and the memory 7 is usable, the bus assignment circuit 9 sends an assignment signal to the input/output device i11fio and the addressing means 8 to notify permission to use the bus. The addressing stage 8 which received the assignment signal,
The reference address is sent to the memory 7, and since the output enable signal OE is off, the memory 7 outputs, for example, one word (
(word) is read out and sent to the input/output device 10. Since the input/output device 10 receives the allocation signal from the bus allocation circuit 9, it takes in this data and writes it, for example, to an internal buffer memory.

When one word of data is written to the human output device 1fIO,
The next bus use request is sent to the bus allocation circuit 9, and the bus allocation circuit 9 sends the data bus 1l between the human output device 10 and the memory 7.
If the bus is available for use, an assignment signal is sent to the input/output device 10 and the addressing means 8 to notify permission to use the bus.

When the addressing stage 8 receives this assignment signal, it increments or decrements the address and sends it to the memory 7, so that the next one word of data is read from the memory 7 and transferred to the input/output device 10. Ru. and,
Similarly to the above, it is written to the buffer memory of the input/output device 10.

In this way, each time the input/output device 10 sends a bus use request, the bus allocation circuit 9 sends an allocation signal to the addressing means 8, and the address is incremented or decremented from the addressing means 8 to the memory 7. Therefore, the data stored in the memory 7 is sequentially transferred word by word to the input/output device 10.

Then, when the Huffer memory from the input/output device 10 becomes full and no path use request is sent, data transfer from the memory 7 to the input/output device 10 ends.

When the processor 5 has data to be transferred to the memory 7 in the input/output device 10, the processor 5 uses the addressing stage 8 as described above.
A reference address is set to , and the input/output device 10 is instructed to transmit data.

When the input/output device 1O is instructed to send data, the memory 7
The output enable signal OE for the bus is turned on, and a bus use request is sent to the bus allocation circuit 9.

When the data bus l1 between the human output device 10 and the memory 7 is usable, the bus assignment circuit 9 sends an assignment signal to the input/output device 10 and the addressing stage 8 to notify permission to use the bus.

The input/output device 0, which has received the assignment signal, sends the data of word ① to the data bus II, and the address designation means 8, which has received the assignment signal, sends the reference address to the memory 7. At this time, since the output enable signal OE is on, the memory 7 writes one word of data sent from the human output device 10 into the area designated by the reference address.

When the data transfer of one word is completed, the human output device 10
The bus allocation circuit 9 sends the next bus use request to the bus allocation circuit 9, and the bus allocation circuit 9 connects the data bus 1 between the input/output device 10 and the memory 7.
1 is usable, an assignment signal is sent to the input/output device 10 and the addressing means 8 to notify permission to use the bus.

When the input/output device 10 receives the assignment signal, it sends the next l word of data to the data bus 11, and when the address designation means 8 of the memory 7 receives the assignment signal, it increments or decrements the address and writes it to the memory. Send on 7. Therefore, in the same manner as described above, the data of the {circle around (1)} word is written in the area designated by the address incremented or decremented by the address designating means 8 in the memory 7.

In this way, each time the input/output device 10 sends a bus use request, the bus allocation circuit 9 sends an allocation signal to the addressing stage 8, and the address is incremented or decremented from the addressing means 8 to the memory 7. Therefore, the data sent by the human output device 10 is stored in the memory 7.
are written sequentially.

Then, when there is no more data to be transferred from the human output device 10 and bus usage requests are no longer sent, the input/output device 1
Data transfer from 0 to memory 7 is completed.

After setting the address in the address designation stage 8 according to the instruction from the instruction means 6, the broker 5 transfers the data bus 12 regardless of access to the memory 7 of the input/output device 10.
Data is transferred to the memory 7 via the .

[Effect]

With the above configuration, the processor 5 sets a reference address in the addressing stage 8, and the input/output device 10
After instructing the processor 5 to send data or to receive data, the processor 5
can perform data transfer with the memory 7 via the data bus 12.

Therefore, when the processor 5 performs multiple jobs,
Even if data is transferred between the input/output device 10 and the memory 7 for one job, the memory 7 can be accessed, thereby eliminating delays in processing other jobs.

[Embodiment] FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

When transferring data from the memory 7 to the human output devices M1 0 and 13, the processor 5 sends the address of the counter 15 to the address analysis unit l4 of the memory 7 according to instructions from the instruction program l7, and selects the counter l5. Then, the counter 15 is set to the starting address of the area of the memory 7 in which data to be transmitted to the input/output device 10 is stored.

Subsequently, when the counter 16 is selected in the same manner, the starting address of the area of the memory 7 in which data to be transmitted to the input/output device l3 is stored is set to the counter l6.

The processor 5 then selects the input/output device 10 via the address bus, and selects the input/output device 1 via the data bus l2.
0 to receive data. Then, when the input/output device 13 is selected via the address bus, the data bus l
2, the human output device 13 is instructed to receive the data.

The human output device 10 that has been instructed to receive data sends a request to use the data bus I1 to the bus allocation circuit 9 while keeping the output enable signal OE off.

The bus allocation circuit 9 checks the usage status of the data bus 11, and if it detects that the human output device 13 is not using it, it sends an allocation signal to the input/output device IO and the counter 15.

When the first assignment signal is input, the counter 15 sends the address set from the processor 5 to the memory 7,
Since the output enable signal OE of the memory 7 is off,
Read one word of data from the specified address,
Send to data node 1l.

When the input/output device IO receives the assignment signal, it transfers the data bus 1
1 and writes it to the internal buffer memory.

The human output device 13 that has been instructed to receive data sends a request to use the data bus 11 to the bus allocation circuit 9 while keeping the output enable signal OE off.

The bus allocation circuit 9 checks the usage status of the data bus 11, and if it detects that the human output device 10 is not using it, it sends an allocation signal to the input/output device 13 and the counter 16.

When the first allocation signal is input, the counter l6 sends the address set from the processor 5 to the memory I77, and since the output enable signal OE is off, the memory 7 receives one word from the specified address. The data is read and sent to the data bus 1l.

When the input/output device 13 receives the assignment signal, the input/output device 13 connects the data bus 1
1 and writes it to the internal buffer memory.

The human output devices 10 and 13 receive the following data:
The bus use request is sent to the bus allocation circuit 9 again, and the bus allocation circuit 9 checks the use status of the data bus l1, and when it becomes usable, sends an allocation signal to the input/output device that sent the use request earlier. .

For example, if the human output device 10 has priority, an allocation signal is sent to the input/output device 10 and the counter 15, and the
Since the received assignment signal is not the first one, the address is incremented by one, for example, and sent to the memory 7.

Therefore, one word of the next data is read from the memory 7 and sent to the data space 11. Then, it is written into the buffer memory of the input/output device W10 that received the assignment signal.

In this way, data is sequentially written into the buffer memory of the input/output device IO one word at a time, and when it becomes full, the input/output device fflo does not send a bus use request to the bus allocation circuit 9, so the data for the input/output device IO is The transfer is finished and
Similarly, when the buffer memory of the input/output device l3 becomes full, data transfer to the human output device l3 ends.

When the processor 5 transfers data from the input/output devices 10 and 13 to the memory 7, the processor 5 sends the address of the counter 15 to the address analysis section 14 of the memory 7 according to instructions from the instruction program 17, and selects the counter 15. The starting address of the area of the memory 7 that stores data received from the input/output device 110 is set for the counter l5.

Subsequently, when the counter 16 is selected in the same manner, the starting address of the area of the memory 7 that stores the data received from the human output device 13 is set for this counter 16.

The processor 5 then selects the input/output device 10 via the address bus, and selects the input/output device W1 via the data bus 12.
0 to send data. When the input/output device 13 is selected via the address bus, the input/output device 13 is instructed to transmit data via the data bus 12.

The human output device 10 that has been instructed to transmit data turns on the output enable signal OE and sends a request to use the data bus 1l to the path allocation circuit 9. The bus allocation circuit 9 checks the usage status of the data bus l1, and when it detects that the input/output device l3 is not in use, it transfers the data bus l1 to the human output device 10 and the counter l5.
Sends an allocation signal to.

When the human output device 10 receives the assignment signal, it reads out one word of data from the bus memory and sends it to the data bus 11.
Send to.

When the first assignment signal is manually input, the counter 15 sends the address set from the processor 5 to the memory 7, and since the output enable signal OE is on, the memory 7 receives the l word manually input from the data bus l1. Take in the data and write it to the address specified by counter l5. The human output device 13, which has been instructed to transmit data, turns on the output enable signal OE and sends a request to use the data bus 11 to the bus allocation circuit 9. The bus allocation circuit 9 checks the usage status of the data bus 1l, and when it detects that the human output device 10 is not using it, the input/output device 13 and the counter 16
Sends an allocation signal to. When the human output device 13 receives the assignment signal, it outputs one word of data from the buffer memory and sends it to the data bus 1l.
Send to.

When the counter 16 receives the first allocation signal, it sends the address set from the processor 5 to the memory 7, and since the output enable signal OE is on, the memory 7 receives the l word manually input from the data bus 11. The data is taken in and written to the address specified by the counter l6.

The human output devices 10 and 13 transmit the following data:
The bus use request is sent again to the bus allocation circuit 9, and the bus allocation circuit 9 checks the use status of the data bus 11, and when it becomes usable, sends an allocation signal to the input/output device that sent the use request earlier. .

For example, if the input/output device 10 has priority, an allocation signal is sent to the input/output device 10 and counter l5, and counter 15
Since the allocation signal is not the first, the address is counted up by one and sent to the memory 7, for example.

The next one word of data is read from the buffer memory of the input/output device 10 that has received the assignment signal, and the data bus 1
1. Then, the memory 7 takes in l words of data manually inputted from the data bus 11, and stores the data in the counter l.
Write to the address specified by 5.

In this way, data is read one word at a time from the buffer memory of the input/output device 10, and when the buffer memory becomes empty, the human output device 110 does not send a bus use request to the bus allocation circuit 9, so the human output device The IO data transfer ends, and similarly, when the buffer memory of the input/output device 13 becomes empty, the data transfer of the human output device 13 also ends.

FIG. 3 is a time chart explaining the operation of FIG. 2.

As shown in the DMA information set in FIG.
When it becomes necessary to transfer data from the input/output devices 1O and 13 to the memory 7, the data is transferred from the counter 1 via the address analysis section 14 of the memory 7, as described above.
5 and 16, and instruct the human output devices 10 and 13 to send or receive data.

The human output devices 10 and 13 operate as described above and are shown in FIG.
), the human output device 10 transfers data with the memory 7 via the data bus 11 in the cycle indicated by DMA [phase], and the human output device 13 transfers data to the memory 7 in the cycle indicated by DMA ■.
The reason why DMA[phase] and DMA@ do not alternately occupy the data bus 1l is due to the order in which bus use requests are sent to the bus allocation circuit 9.

In addition, the processor 5 inputs and outputs the input/output device WlO or 13 and the memo I7 in the cycles shown by CPU■ to ■ in FIG. 3(a).
Data is transferred to and from the memory 7 via the data bus 12, regardless of the data transfer during that time.

〔Effect of the invention〕

As explained above, the present invention prevents a processor that performs multiple zips from causing a delay in the processing of other jobs even if data is transferred between an input/output device and memory for one job. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the principle of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 3 is a time chart explaining the operation of FIG. 2, and FIG.
The figure is a block diagram explaining an example of the prior art, and FIG. 5 is a time chart explaining the operation of FIG. 4. In the figure, 1.5 is a processor, 2.7 is a memory, 3 is a DMA control circuit, 4, 10. 13 is an input/output device, 6 is an instruction means, 8 is an address designation means, 9 is a bus allocation circuit, 11.12 is a data bus, 14 is an address analysis section,
15. 16 is a counter. Part 1 of the prior art and explanation i-3 Fig. 7 Fig. 4

Claims (1)

[Claims] A processor (5), an input/output device (10) that transfers data under the control of the processor (5), and a plurality of ports corresponding to a plurality of data buses (11) and (12). ,
Permission to use the bus is granted to the processor (5) and the input/output device (10), in response to bus usage requests sent by the memory (7) and the input/output device (10), respectively, which transfer data individually. A bus assignment circuit (9) that sends out assignment signals to be notified.
), the memory (7) stores write/read data based on the address set by the processor (5) and in response to the allocation signal sent by the bus allocation circuit (9). The processor (5) is provided with an addressing means (8) for sequentially incrementing or decrementing the addresses of ), and after the processor (5) sets a reference address in the addressing means (8) of the memory (7) according to the instruction of the instruction means (6), the memory ( 7
), the allocation signal sent out by the bus allocation circuit (9) is determined by the address sent out by the addressing means (8) based on the reference address set in the addressing means (8). The assignment signal sent by the bus assignment circuit (9) sequentially writes the data sent by the designated input/output device (10) to the memory (7), or sequentially reads the data from the memory (7). A direct memory access control method characterized by writing to a designated input/output device (10).