JPH0315977A - Vector operation processor - Google Patents

Abstract

PURPOSE:To improve the efficiency of vector operation by providing a bypass processing means which bypasses on adder part and writes a multiplication result in a vector register when a multiplier part detects an index overflow exception. CONSTITUTION:An element control circuit 11 is removed, the adder 8 is bypassed by a selector 12 at the time of generating an arithmetic operation exception, and the output of a register 7 is stored in the register 9. Then, in case where the index overflow exception is detected by the multiplier 5, '1' meaning the index overflow exception is set in the register 10. When '1' is set in the register 10, the selector 12 inputs the stored contents of the register 7 directly to the register 9 by bypassing the adder 8 without sending them to the adder 8. Thus, data can be secured without disturbing the flow of a pipeline.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a vector arithmetic processing technique for writing addition results to a multiplication result into a vector register, and in particular, efficient processing when an exponent overflow exception occurs in the multiplication section. This is a review of effective techniques that can be used to carry out specific tasks.

[Conventional technology]

An example of a conventional pipeline type vector processing device is shown in the block diagram of FIG.

In this vector arithmetic processing device, a vector register (VR) 1 is connected to registers 2, 3, and 4 in which operands are written, and a multiplier 5 is connected to registers 3 and 4 to multiply the outputs of both registers. There is. Further, a delay register 6 is connected to the register 2. A register 7 for storing the multiplication result is connected to the multiplier 5, and an adder 8 is provided to add the outputs of the register 7 and the delay register 6. A register 9 is connected to the adder 8, and its output is sent to the vector register 1.
is applied to. Further, a register 10 is connected to the multiplier 5, and "l1" is set when an exponent overflow is detected.This register IO contains an element control circuit l1.
is connected.

Next, the operation of the vector arithmetic processing device with the above structure will be explained.

Here, exponent overflow exception handling using one of the vector instructions, Multiply and add, will be described.

The multiply-and-add instruction is a compound instruction,
Two of the three operands are multiplied for each element, and one other operand is added to the result.

Three operands are read from vector register l in the order of element numbers and stored in registers 2-4. The two operands stored in registers 3 and 4 are manually input to multiplier 5, multiplication processing is performed on the two operands, and the result of the operation is stored in register 7.

On the other hand, the remaining operand stored in register 2 is stored in delay register 6. The operand of delay register 6 and the operation result stored in register 7 are added by adder 8, and the result is stored in register 9.

Here, if the multiplier 5 detects an exponent overflow exception, the value after addition is input to the register 9, and this value cannot be input to the vector register 1. At this time, "1" is set in the register 10, which means that an exponent overflow exception has been detected. The element control circuit 11 that receives this set value inputs the operand of the main element of the operation exception t again to registers 3 and 4, multiplies them by the multiplier 5, and sends the result to the vector via the register 7. Write to register 1.

Note that, for example, Japanese Patent Laid-Open No. 57-97169 relates to this type of device.

[Problem to be solved by the invention]

However, in the vector arithmetic processing device described above, which writes the multiplication result to the vector register without performing addition processing when an exponential overflow exception is detected, an overrun occurs due to this processing, and the operation of the element at the time of the exception is interrupted. The inventor discovered a problem in that the processing takes a lot of time.

An object of the present invention is to provide a vector arithmetic processing device that does not generate one run.

The above objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a vector that multiplies at least two of a plurality of operands read from a vector register in a multiplier, adds the multiplication result and at least one of the remaining operands in an adder, and writes the addition result to the vector register. The arithmetic processing device is provided with bypass processing means for bypassing the addition section and writing the multiplication result into the vector register when the multiplication section detects an exponent overflow exception.

Alternatively, addition processing means may be provided that forces data output from the addition section and writes it into the vector register when the multiplication section detects an exponent overflow exception.

[Effect]

According to the above means, when the multiplication section detects an exponent overflow exception, the multiplication result is written to the vector register without passing through the addition section.

Therefore, only the multiplication results that have not been subjected to addition processing are written to the vector register, so that the flow of the pipeline is not disturbed, processing is performed in accordance with the flow, and malfunctions do not occur.

[Example ■]

FIG. 1 is a block diagram showing an embodiment of a vector arithmetic processing device according to the present invention. In this embodiment, the same reference numerals are used for the same parts as in FIG. 3, and therefore, redundant explanation will be omitted below.

This embodiment differs from FIG. 3 in that the element control circuit 11 is removed and the adder 8 is bypassed by the selector l2 when an arithmetic exception (overflow exception) occurs.
The configuration is such that the output of register 7 is stored in register 9.

In the above structure, the processing when an exponent overflow exception is not detected is the same as described in FIG. 3 above, so a redundant explanation will be omitted here. If an exponential overflow exception is detected in multiplier 5, register 10
"l" is set to indicate an exponent overflow exception. When "1" is set in the register 10, the selector 12 directly inputs the contents stored in the register 7 to the register 9, bypassing the adder 8, without sending the contents stored in the register 7 to the adder 8.

In this manner, by bypassing the adder 8 when an exponent overflow exception occurs, data can be guaranteed without disturbing the flow of the pipeline.

[Example 2] FIG. 2 is a block diagram showing another embodiment of the invention.

In this embodiment as well, the same reference numerals are used for the same parts as used in FIG. 3, so the repeated explanation will be omitted below.

This embodiment differs from the previous embodiment in that a selector 13 is provided which forcibly sets the data output of the delay register 6 to "0" when "12" is set in the register 10. be.

In this embodiment, when an exponent overflow exception occurs and "1" is set in the register 10, the selector l3 detecting this setting forces the data output of the delay register 6 to "0". As a result, adder 8
Then, the data output "0" of the delay register 6 is added to the contents of the register 7, and the contents of the register 7 are stored in the register 9 as they are. Therefore, even when an exponential overflow exception occurs, data can be guaranteed without disturbing the flow of the pipeline.

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.

That is, a vector that multiplies at least two of a plurality of operands read from a vector register in a multiplier, adds the multiplication result and at least one of the remaining operands in an adder, and writes the addition result to the vector register. In the arithmetic processing device, bypass processing means is provided for bypassing the addition unit and writing the multiplication result to the vector register when the multiplication unit detects an exponent overflow exception, or the multiplication unit detects an exponent overflow exception. When the data output of the adder is executed, the data output of the adder is forcibly set to zero, and this zero value is added to the multiplication result, and an addition processing means is provided for writing the result to the vector register. Data recovery processing is not required when an operation exception occurs, and the efficiency of vector operations can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the vector arithmetic processing device according to the present invention, FIG. 2 is a block diagram showing another embodiment of the vector arithmetic processing device according to the present invention, and FIG. 3 is a block diagram showing a conventional pipeline type vector arithmetic processing device. FIG. 2 is a block diagram showing an example of a vector arithmetic processing device. I... Hector register, 2, 3, 4, 7.9.10
...Register, 5...Multiplier, 6...Delay register, 8...Adder, 12.13...Selector. 1st Figure 12: Selector

Claims (1)

[Claims] 1. A vector operation process in which at least two of a plurality of operands read from a vector register are multiplied by a multiplier, the multiplication result and at least one of the remaining operands are added by an adder, and the addition result is written to the vector register. In the apparatus, when the multiplier detects an exponent overflow exception, the adder is bypassed;
A vector arithmetic processing device, further comprising bypass processing means for writing the multiplication result into the vector register.