JPH03158944A - Cache control system - Google Patents

Abstract

PURPOSE:To improve the processing speed by constituting the system so that a control part recognizes an access area corresponding to a storage device designated by an access command, and executes an access to data held in a cache memory. CONSTITUTION:At the time of executing an access to data in a cache memory 2b, a processor 1 issues a command provided with information (information of a capacity ratio) related to how many folds of the capacity of one access block of the cache memory 2b the capacity of an access block of a storage device which becomes a store origin of its data is, to a control part 2a. The control part 2a analyzes the information of the command contents, etc., written in this command. On the other hand, a number recognizing means 2c informs a value of the capacity ratio as the number of times of an access executed to the cache memory by an access means 2d. Subsequently, the access means 2d brings the data of the cache memory 2b to access by the number of blocks corresponding to the capacity of one access block of the storage device being a store origin. In such a way, the processing speed can be improved.

Description

[Detailed description of the invention] 〔overview〕 The present invention focuses on main memory and storage device (magnetic disk).

Regarding the control method of a system that performs disk caching to fill the access gap between magnetic drums, magnetic tapes, optical disks, etc., it is common for storage devices with access block capacities that are different from the access block capacity managed by cache memory. The purpose is to provide a disk cache control method that enables high-speed data transfer and ultimately improves processing speed by enabling cache control. It is equipped with a plurality of storage devices each having a different amount, and a unit storage area with a capacity corresponding to a common divisor of the minimum unit data amount of each of the storage devices, and uses the unit storage area to store data for each unit data amount. a cache memory that holds some data in the storage device;
A control unit that accesses the cache memory in response to an access command to the storage device from a processing device,
a control unit having a number recognition means for recognizing the number of unit storage areas in which unit data is stored from the access command; and an access means for accessing an area of the cache memory corresponding to the number recognized by the number recognition means. The control unit is configured to recognize an access area according to the storage device specified by the access command and access data held in the cache memory.

[Industrial application field]

The present invention focuses on main memory and storage device (magnetic disk).

This invention relates to a control method for a cache system that fills the access gap between magnetic drums, optical disks, etc.

As the performance of computers has increased in recent years, systems having a disk function have appeared as one method for filling the access gap between main memory and storage devices.

In this system, conventionally, when a LEET command was issued to operate the disk cache, a certain amount of data was stored in an access block (e.g., equivalent to a sector on a disk) as an access unit (hereinafter referred to as the minimum access command unit). Data is read from the storage device that stores the data each time the data is stored in the main memory, and at the same time the data is transferred to the main memory and also imported into the cache memory. By doing so, after importing, when there is an access to the same block 11, the data is read from the cache memory, thereby speeding up the access.

The cache memory includes a data storage section that stores data and an address storage section that stores the address of the data. The data storage section of the cache memory and the data storage area of the storage device are each divided into blocks of equal storage capacity, and the data storage section and address storage section have a one-to-one correspondence. A copy of the data in the storage device is then placed in the data storage unit.

For this reason, cache control cannot be performed for a storage device in which the storage capacity of one block is different from the storage capacity of one block of the data storage section of the cache memory. Therefore, it is necessary to enable cache control for such storage devices as well.

[Conventional technology]

A conventional technique is shown in FIGS. 6(a) and 6(b). This will be explained below with reference to the drawings.

FIG. 6(a) is an explanatory diagram when a read command is issued from the processing device, the corresponding data is stored in the cache memory, and the data is transferred from the cache memory to the main memory.

When a read command is issued from the processing device, first, a search is made to see if the address in the storage device is stored in the address storage section. As a result of the search, if the data exists, the data at the corresponding address is transferred from the cache memory to the main memory. That is, the corresponding data in the cache memory is transferred to the main memory.

FIG. 6(b) is an explanatory diagram when a read command is issued from the processing device, the corresponding data is not stored in the cache memory, and the data is transferred from the storage device to the main memory.

When a read command is issued from the processing device, first, a search is made to see if the address in the storage device is stored in the address storage section. As a result of the search, if the data does not exist, the data at the corresponding address is transferred from the storage device to the main memory and also transferred to the cache memory. That is, the corresponding address is registered in the address storage section, and the corresponding data is written in the data storage section in correspondence with this address.

Typically, to enable cache control as described above,
1 block in the storage device, 1 block in the data storage unit
The data storage capacity of one block set on the block and main memory is set to be equal.

[Problem to be solved by the invention]

On the other hand, in recent years, various storage devices with different storage capacities per block have become popular, and there is a strong need for a system that can centrally control these devices with a single system.

However, in the conventional cache control method,
Since the capacity of one block of cache memory is fixed to the capacity of one block of storage device, cache control cannot be applied to storage devices where the capacity of one block is different from the capacity of one block of cache memory. . To give a specific example, even if you try to apply a storage device with a capacity of 1 block of 512 Bytes to a cache memory whose capacity of 1 block of data storage is 256 Bytes, the data stored in 1 block of the storage device This is because all data cannot be stored in one block of cache memory.

Furthermore, in general, cache memory often stores data from multiple storage devices, and even if we consider this case, cache control cannot be applied to storage devices with different capacities for one block of cache memory.
It is not possible to perform cache control in an integrated manner on various storage devices.

In view of the above-mentioned problems, the present invention provides a disk that enables high-speed data transfer and ultimately improves processing speed by applying cache control to storage devices that differ in capacity from the access blocks managed by cache memory. The purpose is to provide a cache control method.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

Reference numeral 1 denotes a processing device which, depending on the processing content, sends a cache memory 2b to the control unit 2a, which is provided with information about the ratio of the capacity of the storage device that is the storage source of the data to be accessed and the capacity of the access block of the cache memory 2b. It issues an access command for access. 2a is a control unit that analyzes commands issued from the processing device 1 and accesses the storage devices #0 to #N. 2b is a cache memory, storage device #
Data 0 to #N are stored for each fixed capacity. 2c is a number recognition means, which recognizes the capacity ratio information from the access command issued by the processing device 1, and instructs the access means 2d the value of the capacity ratio as the number of times the access means 2d should access the cache memory 2b. It is something to do. Here, the number of times the access should be made is, for example, if the capacity of the access block of the storage device is twice the capacity of the cache memory, the access means 2d accesses the cache memory 2b twice.
This means that it is equivalent to accessing one access block in the storage device. Reference numeral 2d denotes an access means, which accesses the data in the cache memory 2b by the number of blocks corresponding to the capacity of the access block of the storage device that is the storage source, as described above. #0~#N
is a storage device, and is a so-called external storage device such as a magnetic disk, magnetic drum, or optical disk.

[Effect]

When accessing data in the cache memory 2b, the processing device 1 instructs the control unit 2a to determine how many times the capacity of the access block of the storage device that is the storage source of that data is compared to the capacity of one access block in the cache memory 2b. Issue a command with information on whether the capacity ratio is the same (capacity ratio information).

The control unit 2a analyzes information such as command contents written in this command. On the other hand, the number recognition means 2c notifies the value of the capacity ratio as the number of times the access means 2d should access the cache memory. Upon receiving this notification, the access means 2d accesses the data in the cache memory 2b by the number of blocks corresponding to the capacity of one access block of the storage device that is the storage source. As mentioned earlier, for example, the capacity of one access block of the storage device is twice the capacity of one access block of the cache memory 2b.
If the number is 0, the access means 2d repeatedly accesses the two access blocks of the cache memory 2b, thereby operating as if these two blocks were one block. That is, if the data requested by the processing device I exists in the cache memory 2b, it can be accessed as described above. Furthermore, even if the data requested by the processing device I does not exist in the cache memory 2b, by similarly accessing it (in this case, using a write command), information indicating that the data is the same block in the storage device is written, and subsequent Access is possible.

〔Example〕

FIG. 2 shows an example of a system to which the present invention is applied, and the configuration and operation of the system will be described in detail below.

In the figure, reference numeral 1 denotes a processing device, which includes at least a cache memory 202. It issues commands to access storage devices #0-#N. 2 is Te'isk Canche f#J? It is a wholesaler and performs disk cache control in a macro sense. 201 is an MPU that actually executes disk cache control. A cache memory 202 includes a cache entry RAM 202a and a cache buffer RAM 20.
2b. 2.02a is a cache entry RAM, which is used to retrieve data stored in the cache buffer RAM 202b. 202b
A cache buffer RAM is used to hold data written to the storage device or data read from the storage device. In this embodiment, the capacity of one access block of the cache buffer RAM is 25
It is assumed to be 6 bytes. 203 is a ROM, MP[J2
01 control program is stored therein. A RAM 204 serves as a work area when cache control is executed. Reference numeral 205 denotes a common bus control unit, which exchanges data with the processing device 1 or the main memory 3 via the common bus. 206 is an input/output bus control unit that controls access to various storage devices. 3 is main memory,
It stores data in the cache memory 202 or storage devices #0 to #2.

Furthermore, the processing device 1 accesses this main memory 3 to perform actual processing. #0 to #2 are storage devices, specifically so-called external storage devices such as magnetic disks, magnetic drums, optical disks, etc. In this example, the capacity of one access block of each is as follows. do.

Storage device #0-m--256 Byte Storage device #1----1----512 Byte Storage device #2---1024 Byte In a system configured with or more, Its operation is as follows.

(1) Read control 1) When a read request from a storage device occurs, the processing device 1 issues a command to the disk cache control unit 2.

2) Upon receiving the read command, the disk cache control unit 2 searches the cache entry RAM 202a to see if the MPU 201 has the corresponding data in the cache buffer RAM 202b.

◎When there is a read hit, if the cache buffer RAM 202b has the corresponding data, the MPU 201 transfers the data from the cache buffer RAM 202b to the main memory 3.

◎When a read miss occurs, the MPU 201 accesses the storage devices #0 to #2 via the 10 bus control unit 206, and transfers the corresponding data from the storage device to the main memory 3.

In this case, when transferring data to the main memory 3, the MPU 201 takes in the data to the cache buffer RAM 202b via the 1O-Bus control unit 206, writes an address corresponding to the data in the cache entry RAM 202a, and writes the address corresponding to the data to the cache entry RAM 202a, and then reads 3) The disk cache control unit 2 notifies the processing device 1 via the common bus control unit 205 that the read process has ended, and waits for the next command.

(2) Write control 1) When a write request is issued to the storage device, the processing device 1 issues a write command to the disk cache control unit 2 via the common bus control unit 205.

2) When the disk cache control unit 2 receives a write command, it determines whether the MPU 201 has the corresponding space in the cache buffer RAM 202b.
Search using cache entry RAM 202a.

When the MPU 201 has a corresponding space in the cache buffer RAM 202b, the MPU 201 writes the data read from the main memory 3 into the corresponding space in the device and cache memory 202.

◎If there is no corresponding space in the cache memory 202 at the time of a miss, the MPU 201 takes out a new space in the cache memory 202 using LRU logic, etc., and transfers the data read from the main memory 3 to the storage device and the newly taken out space. Write.

3) The disk cache control unit 2 notifies via the common lotus control unit 205 that the processing device 1 write process has ended, and waits for the next command from the processing device 1.

FIG. 3 is a diagram showing an example of the format of commands used in the present invention.

In the figure, a is a command code, which is information for notifying the control unit 2a of the type of command written in one area within the command. b is a device ID, which is also information for notifying the control unit 2a of the data in the cache memory corresponding to the storage device of the storage source of the data targeted by the command written in one area within the command. .

C is an identification code that characterizes the present invention, and information for making each minimum access block in the cache memory 2b to be accessed correspond to the minimum access plotter in the storage devices #0 to #N is written. For example, in a system where the capacity of one block of the cache buffer RAM 202b is 256 Bytes, the capacity of each minimum access block unit is 256 Bytes.
, 512 Byte, 1024 Byte storage device #0 ~
Consider the case where data #2 is stored. In this case, a 2-bit specific area is provided in one area of the command, and one area of the storage device that is the target of access requests such as read/write is set.
When the number of cache memory blocks corresponding to the data capacity of a block is 256 Bytes, it becomes one block, so 0 → 00 (corresponding to 21.512B・yt
In the case of e, there are two blocks, so 1=01+z+ is made to correspond. When it is 1024 bytes, there are 3 blocks, so 2→10 +z+ is made to correspond. According to this information, the MPU 201 processes each corresponding block number as one block. Alternatively, the MPU 201 secures the corresponding number of blocks and writes this information into each secured entry in the cache end JRAM 202a. d is an access block address code, which indicates the address of the access block from which data is to be read/written.

e is a main memory address code and indicates the address of the main memory 3.

FIG. 4 shows the cache entry RAM 20 in the present invention.
2a and a cache buffer RAM 202b. FIG.

After analyzing the contents of the command, the MPU 201 writes a cache entry RAM 202 in the cache search table in the RAM 204 in order to search from the cache memory 202.
Connect b. And cache entry RAM2
02 An identification code is written in the internal area of the cache buffer RAM 202b to (sector capacity of the storage device where the data in the cache memory is stored)/(capacity of 1 block of the cache buffer RAM 202b) blocks of the cache buffer RAM 202b. is written to enable cache control for subsequent access requests.

FIG. 5 shows a flowchart of an embodiment of the present invention. Below, using the same figure, one entry is 256 Bytes.
12 is a flowchart showing the flow when a data transfer request is issued to the cache memory 202 from the optical 4 disk (storage device #2) with a sector capacity of 1024 bytes to the main memory.

◇3tepl A read request to the cache buffer RAM 202b or optical disk is generated from the processing device 1.

◇5tep2 Since the optical disc is 1024 Bytes/1 sector, the third
Set identification code 2 in the figure to the command.

◇5tep3 In response to the IO start command, the processing device 1 reads the corresponding command from the main memory 3 and transfers it to the MPU 201 via the common bus control unit 205.

◇Step 4 The MPU 201 has the command code shown in FIG.

Analyze device ID, identification code, access protocol address, system memory address, etc.

◇Step 5 The MPU 201 uses the cache entry RAM 202a to store the cache buffer RAM according to the analysis result.
202 Search for corresponding data in b. That is, the fourth
As explained using the diagram, the MPU 201 uses the RAM 204
Cache entry R in the cache search table inside
AM202b is connected to search for the existence of the address of the corresponding data.

◇5step6 As a result of the search, the corresponding data is in cache buffer 20
Determine whether it was in 2b (hit).

◇5tep7 If there is a hit, the data at the corresponding address is DMA transferred from the cache buffer RAM 202b to the main memory 3.

◇5tep8 9 20 When the transfer process is completed, the MPU 201 closes the common lotus control unit 205.

◇5tep9 An interrupt notification is sent to the processing device 1 that the processing has ended.

◇5teplO The processing device 1 checks the status after the processing is completed.

On the other hand, if there is no hit in 5tep6, the flow will be as follows.

◇5tepl 1 Data at the corresponding address is transferred from the optical disk to the main memory 3 by DMA.

The following flow is 5tep8, 5tep9, and 5teplO.

〔Effect of the invention〕

According to the present invention, cache control is possible for a storage device in which the data storage capacity of one block is an integral multiple of the set capacity of one block of the data storage section (cache buffer RAM).

Further, cache control can be performed in an integrated manner on a plurality of storage devices having different data storage capacities for one block.

This makes it easy to expand the cache system,
In the end, the processing speed of the system can be increased.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of one embodiment, Fig. 3 is a diagram showing an example of the format of commands used in the present invention, and Fig. 4 is a cache entry RAM and cache in the present invention. FIG. 5 is a flowchart of an embodiment of the present invention, and FIG. 6 is a diagram showing a conventional technique. In FIG. 1, the reference numerals are as follows. 1 -----------1-- Processing device 2 a-
---------------Control unit 2 b ---
−−−−=−−−−−−−−−−−−Cache memory 1 to 22 2c Number recognition means d Access means #0 to #N Storage device 3

Claims (1)

[Scope of Claims] A plurality of storage devices (#0 to #N) each having a different amount of data in the smallest unit that can be accessed at one time;
A unit storage area of a capacity corresponding to a common divisor of the minimum unit data amount of each of the storage devices (#0 to #N) is provided. ); and control for accessing the cache memory (2b) in response to an access command from the processing device (1) to the storage device (#0 to #N). part (2a), a number recognition means (2c) for recognizing the number of unit storage areas in which unit data is stored from the access command; and the cache according to the number recognized by the number recognition means (2c). Access means (2d) for accessing an area of memory (2b)
and a control unit (2a) having a control unit (2a), the control unit (2a) recognizing an access area according to the storage device specified by the access command and accessing the data held in the cache memory (2b). A cache control method featuring: