JPH03157895A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To perform the high-speed data transfer operation and write/read test operation of a data RAM by adding a function which invalidates the increment operation of an address signal selectively with an external control signal. CONSTITUTION:An AND circuit which performs AND operation with an external terminal AC is added to a pointer input part for an INC signal for controlling the increment operation of a pointer and when the external terminal AC is at low level, the INC signal is inputted to the pointer as it is. When the external terminal AC is at low level, the INC signal is not inputted to the pointer and the increment operation is invalidated selectively while a last value is held. Thus, the automatic stepping operation of the address signal is invalidated selectively by using the external control signal to enable continuous writing and reading to and from the same address of an internal memory circuit. Consequently, the high-speed data transfer operation and write/read test operation of the data RAM are carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit device.
The present invention relates to a technique that is effective for use in devices that include memory circuits to which reading is performed.

[Conventional technology]

° internally generated? There is a semiconductor integrated circuit device that includes a built-in circuit for writing/reading data using an F-response. An example of a semiconductor integrated circuit device incorporating such a memory circuit is disclosed in Japanese Patent Application Laid-Open No. 62-2844.
Publication No. 34, @1” r E published by Tate Seisakusho
l 1'r, Digital Signal Processor (H3P)
Hl) 61810B User Manual J is available.

[Problem to be solved by the invention]

When data is transferred (read/read) from the outside to the built-in memory circuit as described above, the address signal is automatically incremented internally. That amount,
When testing a memory circuit, if you write to a certain address, the address will automatically be incremented. When reading in step 1, it becomes impossible to read whether or not writing has been performed. There,
It is conceivable to write to all addresses consecutively and then read the data from all addresses (-) in succession. However, this method cannot detect multiple write failures. Therefore, the above It is necessary to provide a program for memory access for testing purposes such as .

The second object of the present invention is to provide a semiconductor integrated circuit device equipped with a hollow circuit that enables various types of transfer due to its compact configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of representative inventions disclosed in this application is as follows.

Of course, you can't access the built-in memory circuit)'
A function for selectively disabling the incrementing operation of the address signal is added to the address signal generation circuit 14 using an external control number 111.

[For production]

According to the above-mentioned means, by selectively disabling the automatic increment operation of the address signal using an external control signal, it is possible to continuously write/read data to the same address in the built-in memory circuit. You can make a withdrawal.

〔Example〕

FIG. 3 shows a block diagram of an embodiment of a digital processing processor (hereinafter simply referred to as tISP) to which the present invention is applied.

Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, fi/crystalline silicon using known semiconductor integrated circuit manufacturing techniques.

The output register OR is a 16-bit register.

The contents of this output l/register OR are the external data bus I)
It is output to 0 to I5. The previous data remains unchanged until the data is set by your HSP's Progera J. The contents of the internal RAM (read data) as described later are output through this output register OR.

The input register IR is a 16 bis 1- register.

This manual register IR has an external data bus Do-1.
Data from 5 is set. With this HSP program, the previous data remains unchanged until the data is set.

Through this input register IR, the internal RA
Contents to be written to M (write data) are input.

The serial input register SIR is a shift register for 16-bit serial input. Serial data input from terminal S1 is input to serial input register SIR in synchronization with the timing clock supplied from terminal 5ICK.The input value of each serial input register SIH is determined by the internal instruction. Up to 16 bits!
16 rows of internal lotus l3us;? Multiplication shown in black box via i-.

It is transferred to the accumulator included in the arithmetic and logic unit MULT&ALU. l- Serial input and sister SIR
The maximum number of serial input data hints that can be manually input is 16.
It's up to bits. This serial input register SIR is cleared after data is transferred to the accumulator by the HSP program.

The serial output register SOR is a 16-bit serial output shift register. Internal bus BU of HSP
The data set from S to 16 bits in parallel is sent to terminal S.
In synchronization with the timing clock supplied from the OC,
One bit is output from the upper side of the internal bus BUS from the serial output terminal SO. The number of bits of output data can be arbitrarily selected up to a maximum of 16 bits. The output bit number is determined by the terminal SOC during the active period of the input signal supplied to the serial output enable terminal 5OEN.
It is determined by the number of shift l-clocks supplied from After outputting data externally, serial output register SOR
is cleared.

The instruction 1 register Ir+5tREG is a buffer 1 register for an instruction word consisting of 22 bits read from the program r, Igrano, 1'<OM (read only memory).

The down counter PC is a 9-pin instruction ROM.
It is an Arres counter for. This program counter PC generates program ROM addresses in the range of addresses 0 to 511. Furthermore, addresses from 0 to 255 can be set by external control via an external data bus. In this case, the execution start instruction address is set to the set address 1-1.

The stack register 5TACKO/1 is a stack register for saving a 9-pin 1-program program counter.

When a subroutine jump or an interrupt occurs, the contents of the program counter PC are saved. HS of this example
)), the two stack registers S
Since it has T ACK O/1, nesting of 2 levels is possible.

The repeat counter RC is a down counter consisting of 6 bits. The repeat counter RC is used when executing the same instruction repeatedly or when performing loop processing using a jump instruction. This repeat counter RC
By using , program steps can be shortened when the same instruction is used repeatedly, and processing time can also be shortened.

The data RAM and data ROM are divided into four pages. Therefore, data [28M and data ROM
Data input/output to and from requires specifying the page and address. Data is specified using a page address register, and at 1/s is specified using a pointer.

The page address register X/Y-PAGE is a 3-bit page address buffer register. This content and the pointers ROMPOT and RAM-PO, which will be explained next.
data ROM/RAM in combination with the contents of TA/H.
Generates the execution address of

Pointer ROM-POT is a 5-bit data ROM address pointer. It is combined with the X/Y base address (3) bit in the instruction code to generate the execution address of the data ROM.

Pointer RAM-POTA/B contains 6-bit data R
This is an address pointer of AM (Random Access Memory). It is combined with the X/Y page address (3 bits) in the instruction code to generate the execution address of the data RAM. The l (S I) of this embodiment has two pointers A and B having the same function as described above, and can be selected by an instruction. Pointer RAM-POTA/B 2
By using these, complex number arithmetic programs such as FFT can be constructed more efficiently.

In this embodiment, this pointer RAM-PO'FΔ/B
A function to selectively disable the increment operation is added. The signal for selectively disabling the increment operation is a signal supplied from the external terminal AC.

FIG. 4 shows a schematic block diagram of one embodiment of the pointer.

AND(
An AND) circuit is added, and when the external terminal 7-AC is at a low level, the INC signal is input directly to the pointer. External end? - When AC is at low level, the INC signal is not input to the pointer and the previous value is held. As a result, the increment 1 operation can be selectively disabled.

The data transfer operation for this data RAM with the outside is as follows.
This will be explained in detail later.

General registers GRO-3 are 16-history general-purpose registers and can be used as working registers. This content can only be input and output via Y-BUS.

In addition, the multiplication, arithmetic and logic operation unit MUL i”&
ALTI, X-BUS or internal data bus F (U
Register MINX stores data from S and holds it while multiplication is performed, j/register 0 MINY stores data from Y-BUS and holds it while multiplication is performed, multiplier MOLT (7) output Register M OU "I" which operates as a sister register M OU "I"
”.

Aki j, , A register ACCA/B and status register C
Including CR. The above register M OtJ T is a multiplier M
The output data of tJ I,' is held for 4 cycles per instruction, and consists of a mantissa part of 1[i pi I and a 4-bit exponent part.The above accumulator ACCA/B is
Consisting of 20 units, arithmetic and logic unit A1. , Ll
The output of 6 two accumulators A is set.
/ B Q) Selection is made by command.

The del/er register D RE G is a 16-hino register, and the data output to Y-I3 US is 1
Holds the instruction cycle period. It is used to efficiently change the storage address of a pig in data RAM. Due to the one sample delay function in signal processing, this is effective when shifting the storage address of data on the 6-bit AM by one address at a time.

The status register STR is an 8-hit register that reflects the internal state of )fsP.

Control register (2) is a control register consisting of 5 bits in which the conditions for controlling the operation of the ISP are set, and it is used to control HSP commands and input/output terminals Dθ~15. Set by external control.

Data RAM is 200 watts FX16 Hiso 1-note
It has a large capacity and is divided into 4 pages. Therefore, one page is made up of 50 word F.

The data ROM has a storage capacity of 128 words and 16 bits, and is divided into 4 pages. Therefore, one page consists of 32 words.

The program ROM has a storage capacity of 512 words x 22 words, and during each instruction cycle, 22 pin 1- instructions are simultaneously input to the input I/action register 1nst, REG
is read out.

INST&Q CON is an interrupt control circuit, and FUNC is a function control circuit.

CPG is a clock pulse generation circuit, and In
stCOM&'l''M decodes the instruction JJ-code and generates control signals and timing clocks necessary for its execution.

1 2 FIG. 1 shows a 20-char-1 diagram of an embodiment of a data transfer (write/read) operation performed between the data RAM and the data terminal.

Transfer direction (read/write) from start address 8 and end 7-R/W by data transfer command of data RAM.
is specified.

In step +11'r, a read/write determination is made from the signal input from the terminal R/W.

If it is read mode 1, reading is instructed to the data RAM in step (2). In light mode, jump to step (:().

In step (3), a read/write determination is made that is input from the terminal R/W. If it is the write mode, writing to the data RAM is instructed in step (4). If in read mode, jump to step (5).

In step (5), the address is incremented by +1 I
- Validity/invalidity of the operation is determined. For example, end 7'AC
If is a high 1 novel, the increment operation is valid,
Step (pointer RAM-T by 61) OT (A
/B), address A+1 operation is performed. Terminal A
If C is low level, the increment operation is invalidated,
Jump to step (7).

This creates a pointer 17AM that specifies the data RAM.
-The address indicated by POT (A/B) retains address 8 as it is. In this state, if the process returns to the file and performs a R/W determination, it is possible to continuously perform data R/W on the same address.

It is determined whether the address A is the final address, and if it is not the final address, the process returns to step knob (1) and performs the same operation. If it is the final address, this data transfer mode is ended.

In the normal data transfer mode, since the terminal AC is maintained at a high level, a read or write operation is performed according to the terminal R/W.

At this time, pointer RA MP is used for each read or write.
O1' A or B causes address 8 to be incremented by 4-1. Therefore, when writing data 34, the data input from terminals D0-15 or the input 1.・Pointer RAM PO' through register I R1 internal lotus B LJ S and multiplexer MIX
RAM 0 specified by I゛(Δ or B)
) Address 16. written in succession. Reader-
1, the data read from the address of the data RAM specified by the input RAM-POT (A or B) is transferred to the terminal 1 through the multiplexer MIX, the internal hash [λUS and the output register OR]. ~1
5 are read out one after another.

For example, when writing the initial value 1ζ all bits to logic ``0'' for the data RAMP, the normal mode is specified, and the 7 write mode causes all bits to turn 1 to logic 0. ” is inserted 3 times.

Subsequently, when performing a write/read test on the data RAM, a test mode instruction is given. In this case, although not particularly limited, the terminal R
A write is performed to the data RAM regardless of /W. In the first half of the cycle, the terminal AC
is set to low level.

In other words, in step (11) in FIG. 1, read 1 becomes valid, and in step (2), a read operation is performed for address Ai.As a result, the external terminal 0
~15, if the data RAM is functioning normally, the initial value logic "O" is read out as described above. After 2, the write is enabled in step (3), and the readout L7 is read out. Connect the external terminal D O to the same Ars Ai as
Logic "1" inputted from 15 is predicted.

In step (5), in response to the terminal AC being turned on, the increment operation of (1) is disabled, and the process jumps to step (7) to check whether all addresses have been completed or not. A determination is made. At the intermediate address Ai as described above, the process returns to step (11).

Then, a read operation is performed in step (2) via step (1). As a result, as shown in the memory map diagram of FIG. 2, after the initial value data logic "0" is confirmed by reading (R), the logic "1" is written (W) in the AT female Δi. Reading of step tl) after January 1st
The logic “'1” is confirmed by As a result, it can be confirmed that writing/reading and data storage (h) have been performed normally on Atsys Ai.

After this, 〇 to the terminal is set to high level. Therefore, after the dummy writing (meaningless) in steps (3) and (4), the validity/invalidity of the increment operation is determined in step (5), and the increment I operation is enabled due to the high level of the terminal AC. becomes pointer R A
A1' specified by M P O l' (A or B)
Si・su becomes A i +1. Therefore, the read/write test consisting of the above two cycles is performed on the next address A i +1.

As a result of the above test mode, as shown in the memory map shown in Figure 2, if the data RAM operates normally, the previous 71・l,・S Ai-1, etc. are written with a logic "■", and the subsequent addresses Δ1F1, etc. retain the initial value of logic "'0", and are the addresses where the test is performed. The data of Ai changes from logic "0" to logic "1".

In this embodiment, an operating condition is added to the terminal AC for the data transfer microblock l'1gram, etc.
This makes it possible to perform high-speed data transfer dynamics of the data RAM and write/read test operations.

By making the function of selectively enabling/disabling the address increment operation of the data RAM based on the information from the terminal AC, the user can use the function to selectively enable/disable the address increment operation of the data RAM based on the information from the terminal AC. It may be used as one.

The effects obtained from the above embodiments are as described above. That is, a function is added to the address signal generation circuit for accessing the built-in memory circuit in fl) to selectively disable the increment 1 operation of the address signal using a control signal from fl. As a result, it is possible to perform high-speed data transfer operations and write/read test operations of the data RAM.

(2) J = According to (1), internal data RAM
4. On the other hand, by using the above control signals, it is possible to perform simple operations such as reading data from the same address and then making a certain judgment and writing different data, or checking the data when writing it. In addition to data transfer, it is possible to perform two different types of data transfer operations.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, the circuit C that generates the address of the built-in data RAM may use an address counter or an arithmetic circuit in addition to a pointer.

Of course, any device may be used as long as it performs an increment operation of the address signal. The operation control of such an address generation circuit may be performed by a sequential logic circuit as well as by a microprogram method. In addition, in Figure 1, in order to perform both read and write operations in the test mode, the terminal R/W
In step (11, there may be a high-level read mode, and in step (3), there may be a low-level write mode. For example, if data is output from data terminals DO to 15, in response to it, the terminal R/W If it changes from high level to low level 1!, then step (3)
When , it is possible to specify ``Ly''.

In addition to the above-mentioned HSP, the present invention also provides a RAM whose memory is accessed by an internally generated address signal.
It can be widely used in semiconductor integrated circuit devices including.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by adding a function to selectively disable the increment operation of the address signal using an external control signal to the address signal generation circuit for accessing the built-in memory circuit, the data RAM can be High-speed data transfer operations and write/read test operations can be performed.

[Brief explanation of the drawing]

Figure 1 is a flowchart showing an example of a data transfer operation performed between a built-in data RAM terminal and a terminal, and Figure 2 illustrates an example of data RAM write/read worst. The memory map diagram, Figure 3, for
FIG. 4 is a block diagram showing an embodiment of a digital signal processing processor to which the present invention is applied. FIG. 4 is a schematic block diagram showing an embodiment of the pointer. OR... Output register, IR... Input register, S
IR...serial input register, BUS...internal hash, SOR...serial output register, InstREG
・・Instrument register, [)C・・Program counter, STACKO/1・・Stack register, RC・・Repeat counter, ROM‐POT・・R
OM pointer (address generation circuit), RAM-POT
Δ/[3...RAM pointer (address generation circuit),
X/Y-PAGE...Page address register, C.
RO~3...General register, MULT&.
A l 1... Multiplier. Arithmetic logic unit, DREG
・・Play register, STR・・Status register,
CTR...control register, RAM...data R
AM is ROM...data ROM, INST&QCON
・Interrupt control circuit, F LJN C ・Function control circuit, CPG ・I pulse generation circuit,
I n st. COM&TM...Instruction control circuit. Timing control circuit, INC signal -
RAM-POTA/RAM-POTB increment control signal

Claims (1)

[Claims] 1. A memory circuit that inputs and outputs data using an internally generated address signal, and a function of selectively disabling the incrementing operation of the address signal using an external control signal. A semiconductor integrated circuit device characterized by: 2. The above address signal is generated by an arithmetic unit that increments the address signal according to a program, and the increment operation by the arithmetic unit is selectively disabled by inputting the control signal. A semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the external control signal is used in a test mode for writing/reading with respect to the built-in memory circuit.