JPH03156686A - Z buffer circuit provided with logarithmic converter - Google Patents

Z buffer circuit provided with logarithmic converter

Info

Publication number
JPH03156686A
JPH03156686A JP1294929A JP29492989A JPH03156686A JP H03156686 A JPH03156686 A JP H03156686A JP 1294929 A JP1294929 A JP 1294929A JP 29492989 A JP29492989 A JP 29492989A JP H03156686 A JPH03156686 A JP H03156686A
Authority
JP
Japan
Prior art keywords
value
buffer memory
distance
driver
viewpoint
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1294929A
Other languages
Japanese (ja)
Inventor
Masato Ogata
正人 緒方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Precision Co Ltd
Original Assignee
Mitsubishi Precision Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Precision Co Ltd filed Critical Mitsubishi Precision Co Ltd
Priority to JP1294929A priority Critical patent/JPH03156686A/en
Publication of JPH03156686A publication Critical patent/JPH03156686A/en
Pending legal-status Critical Current

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  • Processing Or Creating Images (AREA)
  • Image Generation (AREA)

Abstract

PURPOSE:To reduce the capacity of a Z buffer memory installed in a Z buffer memory part by changing logarithmically the weighting of every one bit according to distance between the viewpoint of a driver and an objective body in respect of the viewpoint of the driver and a memory value representing the distance (Z value) to the objective body. CONSTITUTION:A logarithmic conversion part 10 calculates beforehand log.2/ZMAX from the maximum value Zmax of the Z value of objective input, and makes the Z value of the input into a logarithm by using it as a conversion parameter. The Z value added to the logarithmic conversion part 10 is given necessary logarithm converting processing, and the output Z' as this result is added to a comparator 21A in the Z buffer memory part 20A. On the other hand, in a reading register 23A, Z'' in the Z buffer memory 24A is read out in response to a necessary address signal, and it is compared with Z' by the comparator 21A, and when Z'< Z'', Z' is written in a memory position shown by the address signal. Thus, the capacity of the Z buffer memory 20A can be curtailed.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、対数変換器付き115171回路に関する
ものであり、特に、CGIにおける隠顕処理が少ないメ
モリ容量をもって行われるようにされている対数変換器
付きZバッファ回路に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a 115171 circuit with a logarithmic converter, and in particular, a logarithmic converter in which concealment processing in CGI is performed with a small memory capacity. The present invention relates to a Z-buffer circuit with an integrated circuit.

[従来の技術1 例えば、乗用車等の車両の運転技術を習得するためには
、初めから実車による練習を行うことなく、いわゆるシ
ミュレータ装置によって模擬的な運転の練習をしてから
、実際の車両を用いて練習をすることが実際的であり、
また、練習を受ける者の安全を確保するためにも好適な
ことである。
[Conventional technology 1] For example, in order to learn driving techniques for a vehicle such as a passenger car, one does not practice using an actual vehicle from the beginning, but first practices driving in a simulated manner using a so-called simulator device, and then practices driving an actual vehicle. It is practical to practice using
This is also suitable for ensuring the safety of those undergoing training.

ところで、このようなシミュレータ装置による模擬的な
運転の練習をする際には、模擬的な車両の運転席前方の
風景を刻々と変化させて、車両を運転しているときの臨
場感を練習者に持たせることが必要である。そこで、各
種の模擬映像表示装置が開発されて、適当に使用されて
いるのが現状である。
By the way, when practicing simulated driving using such a simulator device, the scenery in front of the driver's seat of the simulated vehicle changes every moment to give the trainee a sense of reality while driving the vehicle. It is necessary to have it. Therefore, various types of simulated video display devices have been developed and are currently being used appropriately.

第2図は、前記の模擬映像表示装置において使用される
ような、従来のZバッファ回路を示す概略構成図である
。この第2図において、(21)は比較器、(22)は
書き込みレジスタ、(23)は読み出しレジスタ、(2
4)はZバッファメモリであって、これらによって従来
のZバッファメモリ部(20)が構成されている。
FIG. 2 is a schematic configuration diagram showing a conventional Z buffer circuit as used in the above-mentioned simulated video display device. In this Figure 2, (21) is a comparator, (22) is a write register, (23) is a read register, (2
4) is a Z buffer memory, which constitutes a conventional Z buffer memory section (20).

[発明が解決しようとする課題] 上記された従来の2バッファメモリ部によれば、運転者
の視点と対象物への距離(Z値)を表すメモリ値が、そ
の遠近のいかんを問わず1ビツト毎の重み付けが一定で
あり、それだけZバッファメモリ部内に設けられている
Zバッファメモリの容量が大きくなってしまうという問
題点があった。
[Problems to be Solved by the Invention] According to the conventional two-buffer memory unit described above, the memory value representing the distance (Z value) between the driver's viewpoint and the object is 1 regardless of its distance. There is a problem in that the weighting for each bit is constant, which increases the capacity of the Z buffer memory provided in the Z buffer memory section.

この発明は上記された問題点を解決するためになされた
ものであり、運転者の視点と対象物への距離(Z値)を
表すメモリ値について、その遠近のいかんに応じて1ビ
ツト毎の重み付けを対数的に変化させ、Zバッファメモ
リ部内に設けられているZバッファメモリの容量を節減
することができるようにされた対数変換器付きZバッフ
ァ回路を得ることを目的とする。
This invention was made in order to solve the above-mentioned problems, and the memory value representing the distance (Z value) between the driver's viewpoint and the object is divided into bits according to the distance of the object. An object of the present invention is to obtain a Z-buffer circuit with a logarithmic converter that can logarithmically change weighting and save the capacity of a Z-buffer memory provided in a Z-buffer memory section.

[課題を解決するための手段] この発明に係る対数変換器付きZバッファ回路は: 運転者の視点から対象物までの距離としてのZ値に対応
する映像情報を記憶するZバッファメモリ部;および、 前記Z値について対数的な変換演算処理をする対数変換
部; からなることを特徴とするものである。
[Means for Solving the Problems] A Z buffer circuit with a logarithmic converter according to the present invention includes: a Z buffer memory section that stores video information corresponding to a Z value as a distance from a driver's viewpoint to an object; and , a logarithmic conversion unit that performs logarithmic conversion calculation processing on the Z value;

[作用] この発明によれば、運転者の視点と対象物への距離(Z
値)を表すメモリ値について、その遠近のいかんに応じ
て1ビツト毎の重み付けを対数的に変化させ、Zバッフ
ァメモリ部内に設けられているZバッファメモリの容量
を節減することができるようにされる。
[Operation] According to this invention, the distance between the driver's viewpoint and the object (Z
The weighting of each bit is logarithmically changed depending on the distance of the memory value representing the value (value), so that the capacity of the Z-buffer memory provided in the Z-buffer memory section can be reduced. Ru.

[実施例1 第1図は、この発明の一実施例である対数変換器付きZ
バッファ回路を示す概略構成図である。
[Embodiment 1] Fig. 1 shows a Z with a logarithmic converter which is an embodiment of the present invention.
FIG. 2 is a schematic configuration diagram showing a buffer circuit.

この第1図において、(11)は#1乗算器、(12)
は加算器、(13)は#2加算器であり、これらによっ
てこの発明の実施例における対数変換部(10)が構成
されている。また、(21A)は比較器、(22A)は
書き込みレジスタ、(23A)は読み出しレジスタ、(
24A)はZバッファメモリであって、これらによって
上記実施例におけるZバッファメモリ部(20A)が構
成されている。
In this Figure 1, (11) is the #1 multiplier, (12)
is an adder, and (13) is a #2 adder, which constitute the logarithmic conversion unit (10) in the embodiment of the present invention. In addition, (21A) is a comparator, (22A) is a write register, (23A) is a read register, (
24A) is a Z buffer memory, which constitutes the Z buffer memory section (20A) in the above embodiment.

上記第1図の対数変換部(10)によれば、対象入力で
あるZ値の最大値(Z 、AX)より予め(log−2
/Zwax)を計算しておき、これを変換パラメータと
して前記入力であるZ値を対数化する。
According to the logarithmic conversion unit (10) in FIG.
/Zwax) is calculated in advance, and the input Z value is logarithmized using this as a conversion parameter.

また、上記のZバッファメモリ(24A>の容量は画面
に対応しており(例えば、1024 X 1280)、
所要の深さ(例えば12ビツト)を有するものである。
Also, the capacity of the above Z buffer memory (24A>) corresponds to the screen (for example, 1024 x 1280),
It has the required depth (for example, 12 bits).

対数変換部(10)に加えられたZ値は、所要の対数変
換処理がなされ、その結果としての出力Z°はZバッフ
ァメモリ部(2OA)内の比較器(21A)に加えられ
る。一方、読み出しレジスタ(23A)においては、所
要のアドレス信号に応じて、Zバッファメモリ<24A
)G、:おけるz”を読み出し、前記の比較器(21A
)によりZoとの比較をする。
The Z value applied to the logarithmic conversion unit (10) is subjected to necessary logarithmic conversion processing, and the resulting output Z° is applied to the comparator (21A) in the Z buffer memory unit (2OA). On the other hand, in the read register (23A), Z buffer memory <24A
)G, :z'' in the comparator (21A
) to compare with Zo.

ここで、z’<z”であるときには、アドレス信号で示
されるメモリ位置にZoの書き込みをする。これに対し
て、Z゛≧Z′°であるときには、前記の書き込みは行
わない。
Here, when z'<z'', Zo is written to the memory location indicated by the address signal.On the other hand, when Z'≧Z'°, the above writing is not performed.

なお、」ユ記された実施例において用いられるZ値は正
数であり、このZ値が小さければ小さい程に高い精度が
必要になるという性質がある。そこで、このZ値を対数
的に変換させて保持しておくことにより、上記Zバッフ
ァメモリ部(2OA)内のZバッファメモリ(24A)
の容量を小さくすることができる。
It should be noted that the Z value used in the embodiments marked with "Y" is a positive number, and there is a property that the smaller the Z value, the higher the accuracy is required. Therefore, by logarithmically converting and retaining this Z value, the Z buffer memory (24A) in the Z buffer memory section (2OA) is
capacity can be reduced.

いま、前記のZ値の範囲が0〜Z IIIAKであると
すると、この範囲を1〜2に対応させる変換は式%式% (1) この式(1)の対数をとると、次の式(2)のようにな
る。
Now, assuming that the range of Z values mentioned above is 0 to Z IIIAK, the conversion to make this range correspond to 1 to 2 is the formula % Formula % (1) Taking the logarithm of this formula (1), the following formula (2) becomes as follows.

1ogz(1+(Z/Z、、x))    + H+ 
(2)次に、上記の式(2)をテーラ展開することによ
り、近似的な式(3)のようになる。
1ogz(1+(Z/Z,,x)) + H+
(2) Next, by performing Taylor expansion on the above equation (2), an approximate equation (3) is obtained.

Iogt (1+ (Z / Z PIAg))ζ(l
og、2/Z、AX)iZ  (Z2/2)l  ・・
(3)この発明の実施例においては、上記式(3)を用
いてZ値の対数変換処理がなされることになる。
Iogt (1+ (Z / Z PIAg))ζ(l
og, 2/Z, AX)iZ (Z2/2)l ・・
(3) In the embodiment of the present invention, the logarithmic transformation process of the Z value is performed using the above equation (3).

[発明の効果1 以上説明されたように、この発明に係る対数変換器付き
2バッファ回路は、 運転者の視点から対象物までの距離としてのZ値に対応
する映像情報を記憶するZバッファメモリ部;および、 前記Z値について対数的な変換演算処理をする対数変換
部; からなることを特徴とするものであり、運転者の視点と
対象物への距離(Z値)を表すメモリ値について、その
遠近のいかんに応じて1ビツト毎の重み付けを対数的に
変化させ、Zバッファメモリ部内に設けられているZバ
ッファメモリの4駄を節減することができるという効果
が奏せられることになる。
[Effect of the Invention 1] As explained above, the two-buffer circuit with a logarithmic converter according to the present invention has the following advantages: and a logarithmic conversion unit that performs logarithmic conversion calculation processing on the Z value. , the weighting of each bit is changed logarithmically depending on its distance, and it is possible to save 40% of the Z-buffer memory provided in the Z-buffer memory section. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例である対数変換器付きZ
バッファ回路を示す概略構成図、第2図は、従来のZバ
ッファ回路を示す概略構成図である。 (10)は対数変換部、 (11は#1乗算器、 (12は加算器、 (13は#2乗算器、 (20、(2OA>はZバッファメモリ部、(21、(
21A)は比較器、 (22122A)は書き込みレジスタ、(23、(23
A)は読み出しレジスタ。
FIG. 1 shows a Z
Schematic block diagram showing a buffer circuit. FIG. 2 is a schematic block diagram showing a conventional Z buffer circuit. (10) is the logarithmic conversion unit, (11 is the #1 multiplier, (12 is the adder, (13 is the #2 multiplier, (20, (2OA> is the Z buffer memory unit, (21, (
21A) is a comparator, (22122A) is a write register, (23, (23
A) is a read register.

Claims (1)

【特許請求の範囲】[Claims] (1)運転者の視点から対象物までの距離としてのZ値
に対応する映像情報を記憶するZバッファメモリ部;お
よび、 前記Z値について対数的な変換演算処理 をする対数変換部; からなることを特徴とする対数変換器付 きZバッファ回路。
(1) A Z buffer memory unit that stores video information corresponding to the Z value as the distance from the driver's viewpoint to the object; and a logarithmic conversion unit that performs logarithmic conversion calculation processing on the Z value. A Z-buffer circuit with a logarithmic converter.
JP1294929A 1989-11-15 1989-11-15 Z buffer circuit provided with logarithmic converter Pending JPH03156686A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1294929A JPH03156686A (en) 1989-11-15 1989-11-15 Z buffer circuit provided with logarithmic converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1294929A JPH03156686A (en) 1989-11-15 1989-11-15 Z buffer circuit provided with logarithmic converter

Publications (1)

Publication Number Publication Date
JPH03156686A true JPH03156686A (en) 1991-07-04

Family

ID=17814094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1294929A Pending JPH03156686A (en) 1989-11-15 1989-11-15 Z buffer circuit provided with logarithmic converter

Country Status (1)

Country Link
JP (1) JPH03156686A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923332A (en) * 1995-07-10 1999-07-13 Ricoh Company, Ltd. Image processing device
WO2013105157A1 (en) * 2012-01-13 2013-07-18 パナソニック株式会社 Image generating device, image generating method, image generating program, and integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5442946A (en) * 1977-09-10 1979-04-05 Japan Radio Co Ltd Log converter circuit
JPS6366765A (en) * 1986-09-08 1988-03-25 Victor Co Of Japan Ltd Digital information signal recording and reproducing system
JPS63247868A (en) * 1987-04-02 1988-10-14 Hitachi Ltd Display device for 3-dimensional pattern

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5442946A (en) * 1977-09-10 1979-04-05 Japan Radio Co Ltd Log converter circuit
JPS6366765A (en) * 1986-09-08 1988-03-25 Victor Co Of Japan Ltd Digital information signal recording and reproducing system
JPS63247868A (en) * 1987-04-02 1988-10-14 Hitachi Ltd Display device for 3-dimensional pattern

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923332A (en) * 1995-07-10 1999-07-13 Ricoh Company, Ltd. Image processing device
WO2013105157A1 (en) * 2012-01-13 2013-07-18 パナソニック株式会社 Image generating device, image generating method, image generating program, and integrated circuit
US9165400B2 (en) 2012-01-13 2015-10-20 Panasonic Intellectual Property Management Co., Ltd. Image generation apparatus, image generation method, image generation program, and integrated circuit for rendering a target pixel in a target scene by using Z-buffering

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