JPH03156683A - Wiring order determination system - Google Patents

Wiring order determination system

Info

Publication number
JPH03156683A
JPH03156683A JP1296757A JP29675789A JPH03156683A JP H03156683 A JPH03156683 A JP H03156683A JP 1296757 A JP1296757 A JP 1296757A JP 29675789 A JP29675789 A JP 29675789A JP H03156683 A JPH03156683 A JP H03156683A
Authority
JP
Japan
Prior art keywords
wiring
wiring section
combination
pins
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1296757A
Other languages
Japanese (ja)
Inventor
Norio Kuwabara
教雄 桑原
Satoshi Takada
聡 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Solution Innovators Ltd
Original Assignee
NEC Corp
NEC Software Hokuriku Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Software Hokuriku Ltd filed Critical NEC Corp
Priority to JP1296757A priority Critical patent/JPH03156683A/en
Publication of JPH03156683A publication Critical patent/JPH03156683A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To preferentially wire the wiring section of small degree of freedom by determining wiring order by the combination of the existing layers of pins to be the beginning point and the ending point of the wiring section, and making the wiring order of the wiring section including the pin existing in only the front face layer or the rear layer of a both-side packaged printed board earlier. CONSTITUTION:An input means 2 inputs wiring section information to show the wiring section, and an existing layer deciding means 3 decides the respective existing layers of the pins to be the beginning point and the ending point of the wiring section, and a combination deciding means 5 decides the combination of the existing layers of the pins to be the beginning point and the ending point of the wiring section, and sets cost corresponding to a decided result. Then, a storing means 6 stores the cost set by the combination deciding means 5 and the wiring section information in a storage means 7 as coordinating them with each other. Thus, the wiring section of the small degree of freedom of the input/output of a pattern to the pin can be wired preferentially, and wirability can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は両面実装プリント基板の配線設計に於ける配線
順序決定方式に関し、特に、両面実装プリント基板の表
面のみに部品ピンを有する部品と、裏面のみに部品ピン
を有する部品と、貫通ピンを有する部品とが混在する場
合に於ける配線順序決定方式に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for determining the wiring order in the wiring design of a double-sided printed circuit board, and is particularly applicable to components having component pins only on the surface of the double-sided printed circuit board. The present invention relates to a wiring order determination method when components having component pins only on the back side and components having through pins coexist.

〔従来の技術〕[Conventional technology]

両面実装プリント基板の配線設計に於いて配線順序を決
定する場合、従来は、一般に、配線長。
When determining the wiring order in the wiring design of a double-sided printed circuit board, conventionally, the wiring length was generally used.

配線密度、配線区間の始点と終点とのX座標の差分或い
はY座標の差分等に基づいて配線順序を決定するように
しており、配線区間の始点、終点となる部品ピンが両面
実装プリント基板の一方の面に存在する部品ピンなのか
、両面に存在する貫通ピンなのかを全く考慮していなか
った。
The wiring order is determined based on the wiring density, the difference in the X coordinate or the difference in the Y coordinate between the starting point and the ending point of the wiring section, and the component pins that are the starting and ending points of the wiring section are on the double-sided printed circuit board. No consideration was given to whether it was a component pin on one side or a through pin on both sides.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来は上述したように、配線長、配線密度、配線区間の
始点と終点とのX座標の差分或いはY座標の一差分等に
基づいて配線順序を決定するようにしており、配線区間
に含まれている部品ピンの存在層を全く考慮していなか
ったため、両面実装プリント基板の表面或いは裏面のみ
に存在する部品ピンを含む配線区間の配線順位が低位に
位置され、既に配線された配線区間の配線経路によって
上記部品ピンが囲まれてしまう場合があり、このような
場合、貫通ピンのように他の配線層からパターンを引き
出すことができないので、配線不能となり、配線性が低
下するという問題がある。
Conventionally, as mentioned above, the wiring order is determined based on the wiring length, wiring density, the difference in the X coordinate or the difference in the Y coordinate between the starting point and the ending point of the wiring section, and Since no consideration was given to the layers in which component pins exist, the wiring sections that include component pins that exist only on the front or back side of the double-sided printed circuit board are placed in a lower wiring order, and the wiring of already routed wiring sections is The component pins may be surrounded by the route, and in such a case, the pattern cannot be drawn out from other wiring layers like through-pins, making it impossible to route and resulting in poor wiring performance. .

本発明の目的は両面実装プリント基板の配線設計に於け
る配線性を向上させることにある。
An object of the present invention is to improve the wiring performance in wiring design of a double-sided printed circuit board.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は上記目的を達成するため、 両面実装プリント基板の配線設計に於ける配線順序決定
方式に於いて、 配線区間を示す配線区間情報を入力する入力手段と、 該入力手段が入力した配線区間情報が示す配線区間の始
点及び終点となるピンの存在層を判定する存在層判定手
段と、 該存在層判定手段の判定結果に基づいて前記配線区間の
始点及び終点となるピンの存在層の組合わせを判定し、
判定結果に対応したコストを設定する組合わせ判定手段
と、 該組合わせ判定手段が設定したコスト上前記配線区間情
報とを対応させて記憶手段に格納する格納手段とを設け
たものである。
In order to achieve the above object, the present invention provides a wiring order determination method for wiring design of a double-sided printed circuit board, which includes an input means for inputting wiring section information indicating a wiring section, and a wiring section inputted by the input means. Existence layer determination means for determining the existence layers of pins that are the start and end points of the wiring section indicated by the information; and a set of existence layers of the pins that are the start and end points of the wiring section based on the determination result of the existence layer determination means. Determine the alignment,
The present invention is provided with a combination determining means for setting a cost corresponding to the determination result, and a storing means for storing in a storage means the cost set by the combination determining means and the wiring section information in association with each other.

〔作 用〕[For production]

入力手段が配線区間を示す配線区間情報を入力し、存在
層判定手段が配線区間の始点及び終点となるピンそれぞ
れの存在層を判定し、組合わせ判定手段が配線区間の始
点及び終点となるピンの存在層の組合わせを判定して判
定結果に対応したコストを設定し、格納手段が組合わせ
判定手段によって設定されたコストと配線区間情報とを
対応させて記憶手段に格納する。
The input means inputs wiring section information indicating a wiring section, the existing layer determining means determines the existing layer of each pin that is the starting point and ending point of the wiring section, and the combination determining means determines the existing layer of each pin that is the starting point and ending point of the wiring section. The storage means stores the cost set by the combination determination means in correspondence with the wiring section information in the storage means.

〔実施例〕〔Example〕

次に本発明の実施例について図面を参照して詳細に説明
する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.

第1図は本発明の実施例のブロック図であり、論理接続
情報記憶手段lと、入力手段2と、存在層判定手段3と
、部品情報記憶手段4と、組合わせ判定手段5と、格納
手段6と、メモリテーブル7と、ソート手段8と、出力
手段9と、配線順序記憶手段10とを含んでいる。
FIG. 1 is a block diagram of an embodiment of the present invention, in which logical connection information storage means 1, input means 2, existing layer determination means 3, parts information storage means 4, combination determination means 5, storage It includes a means 6, a memory table 7, a sorting means 8, an output means 9, and a wiring order storage means 10.

第2図は第1図の処理例を示す流れ図であり、以下各図
を参照して本実施例の動作を説明する。
FIG. 2 is a flowchart showing the processing example of FIG. 1, and the operation of this embodiment will be explained below with reference to each figure.

入力手段2は論理接続情報記憶手段1に配線順序決定処
理を行なっていない配線区間を示す配線区間情報が存在
するか否かを判定しくボックスB1)、存在すると判定
した場合は配線順序決定処理を行なっていない配線区間
情報の内の1つを取出して存在層判定手段3に渡す(ボ
ックスB2)。
The input means 2 determines whether or not there is wiring section information in the logical connection information storage means 1 indicating a wiring section for which wiring order determination processing has not been performed (box B1), and if it is determined that there is, the wiring order determination processing is performed. One of the unprocessed wiring section information is extracted and passed to the existing layer determining means 3 (box B2).

存在層判定手段3は入力手段2から渡された配線区間情
報によって示される配線区間の始点となる部品ピン及び
終点となる部品ピンのそれぞれについて、その存在層が
両面実装プリント基板の表面層のみなのか、裏面層のみ
なのか、或いは両面(部品ピンが貫通ピンの場合)なの
かを判定する(ボックスB3)、この判定は、両面実装
プリント基板に実装する各部品のX、Y座標値1部品ピ
ンの部品に対する相対位置1部品ビンの存在層等が格納
された部品情報記憶手段4を参照して行なう。
Existence layer determination means 3 determines whether the existing layer is only the surface layer of the double-sided printed circuit board for each of the component pins that are the starting point and the component pin that is the end point of the wiring section indicated by the wiring section information passed from the input means 2. (box B3). This determination is based on the X and Y coordinate values of each component mounted on a double-sided printed circuit board. This is done by referring to the component information storage means 4 in which the relative position of the pin with respect to the component, the existence layer of one component bin, etc. are stored.

組合わせ判定手段5は存在層判定手段3の判定結果に基
づいて、配線区間の始点と終点となる部品ピンの存在層
の組合わせを判定する(ボックスB4)。そして、始点
及び終点となる部品ピンの存在層が共に両面であると判
定した場合(始点終点となる部品ピンが共に貫通ピンで
ある場合)は変数Kにコストとして4を代入しくボック
スB5)、始点、終点となる部品ピンの存在層の内の一
方が両面であると判定した場合(始点、終点となる部品
ピンの内の一方が貫通ピンである場合)は変数Kにコス
トとして3を代入しくボックスB6)、始点、終点とな
る部品ピンの存在層が共に両面実装プリント基板の表面
層のみであるか、或いは共に裏面層のみであると判定し
た場合は変数Kにコストとして2を代入しくボックスB
7)、始点、終点となる部品ピンの存在層が両面実装プ
リント基板の表面層と裏面層との組合わせであると判定
した場合は変数Kにコストとして1を代入する (ボッ
クスB8)。
The combination determining means 5 determines the combination of existing layers of component pins that are the starting point and ending point of the wiring section based on the determination result of the existing layer determining means 3 (box B4). Then, if it is determined that the existing layers of the component pins serving as the starting point and the ending point are both double-sided (if the component pins serving as the starting point and the ending point are both through pins), substitute 4 as the cost to the variable K (box B5). If it is determined that one of the existing layers of the component pins that are the starting point and the end point is double-sided (if one of the component pins that are the starting point and the end point is a through pin), substitute 3 as the cost to the variable K. If it is determined that the starting and ending component pins exist only on the surface layer of a double-sided printed circuit board, or only on the back layer, substitute 2 as the cost for the variable K. Box B
7) If it is determined that the layer in which the component pins serving as the starting point and end point exist is a combination of the front layer and back layer of a double-sided printed circuit board, 1 is assigned as the cost to the variable K (box B8).

格納手段6は現在配線順序決定処理を行なっている配線
区間の区間情報と、組合わせ判定手段5が変数Kに代入
したコストとを対応させてメモリテーブル7に格納し、
その後、入力手段2に制御を戻す(ボックスB9)。
The storage means 6 associates the section information of the wiring section for which the wiring order determination process is currently being performed with the cost assigned to the variable K by the combination determination means 5, and stores them in the memory table 7.
Thereafter, control is returned to input means 2 (box B9).

上述した処理を全ての配線区間情報に対して行ない、ボ
ックスB1の判断結果がNoとなると、入力手段2はソ
ート手段8を起動する。これにより、ソート手段8はメ
モリテーブル7に格納されている配線区間情報を、それ
と対応して格納されているコストをキーとして昇順にソ
ートし、ソートが完了すると、出力手段9を起動する(
ボックスBIO) 、出力手段9は起動をかけられると
、メモリテーブル7に格納されているソート済みの配線
区間情報を配線順序記憶手段10に出力する(ボックス
B11) 、そして、実際の配線は配線順序記憶手段1
0に記憶されている順番で行なわれる。
The above-described processing is performed on all wiring section information, and when the determination result in box B1 is No, the input means 2 activates the sorting means 8. As a result, the sorting means 8 sorts the wiring section information stored in the memory table 7 in ascending order using the cost stored in correspondence as a key, and when the sorting is completed, the output means 9 is activated (
When the output means 9 is activated, it outputs the sorted wiring section information stored in the memory table 7 to the wiring order storage means 10 (box B11), and the actual wiring is performed in the wiring order. Storage means 1
They are performed in the order stored in 0.

尚、上述した実施例に於いてはメモリテーブル7にコス
トと対応して格納されている配線区間情報を、コストを
キーとしてソートし、ソートした順番に従って配線を行
なうようにしたが、ソートを行なわず、メモリテーブル
7に格納されている配線区間情報とコストとに基づいて
、コストの小さな配線区間から配線を行なうようにして
も良いことは勿論である。
In the above-described embodiment, the wiring section information stored in the memory table 7 corresponding to the cost is sorted using the cost as a key, and wiring is performed in accordance with the sorted order. Of course, based on the wiring section information and cost stored in the memory table 7, wiring may be performed starting from the wiring section with the lowest cost.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、配線区間の始点及び終
点となるピンの存在層の組合わせによって配線順序を決
定するようにしたものであり、両面実装プリント基板の
表面層或いは裏面層のみに存在するピンを含む配線区間
の配線順序を上位にすることにより、ピンへのパターン
の出入りの自由度の小さい配線区間を優先的に配線する
ことが可能となるので、配線性を向上させることができ
る効果がある。
As explained above, the present invention determines the wiring order based on the combination of the layers in which pins, which are the starting point and the ending point of the wiring section, are present, and only the surface layer or the back layer of a double-sided printed circuit board is used. By placing the wiring sections that include existing pins higher in the wiring order, it becomes possible to preferentially route the wiring sections that have a small degree of freedom in entering and exiting patterns to the pins, thereby improving wiring performance. There is an effect that can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例のブロック図及び、第2図は第
1図の処理例を示す流れ図である。 図に於いて、l・・・論理接続情報記憶手段、2・・・
入力手段、3・・・存在層判定手段、4・・・部品情報
記憶手段、5・・・組合わせ判定手段、6・・・格納手
段、7・・・メモリテーブル、8・・・ソート手段、9
・・・出力手段、lO・・・配線順序記憶手段。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart showing the processing example of FIG. 1. In the figure, l... logical connection information storage means, 2...
Input means, 3. Existence layer determination means, 4. Parts information storage means, 5. Combination determination means, 6. Storage means, 7. Memory table, 8. Sorting means. , 9
. . . Output means, lO . . . Wiring order storage means.

Claims (1)

【特許請求の範囲】 両面実装プリント基板の配線設計に於ける配線順序決定
方式に於いて、 配線区間を示す配線区間情報を入力する入力手段と、 該入力手段が入力した配線区間情報が示す配線区間の始
点及び終点となるピンの存在層を判定する存在層判定手
段と、 該存在層判定手段の判定結果に基づいて前記配線区間の
始点及び終点となるピンの存在層の組合わせを判定し、
判定結果に対応したコストを設定する組合わせ判定手段
と、 該組合わせ判定手段が設定したコストと前記配線区間情
報とを対応させて記憶手段に格納する格納手段とを含む
ことを特徴とする配線順序決定方式。
[Scope of Claims] In a wiring order determination method in wiring design of a double-sided printed circuit board, there is provided an input means for inputting wiring section information indicating a wiring section, and a wiring indicated by the wiring section information inputted by the input means. Existence layer determination means for determining the existence layer of pins serving as the start point and end point of the section; and Existence layer determination means for determining the combination of existence layers of the pins serving as the start point and end point of the wiring section based on the determination results of the existence layer determination means. ,
A wiring characterized in that it includes a combination determining means for setting a cost corresponding to a determination result, and a storing means for storing the cost set by the combination determining means in correspondence with the wiring section information in a storage means. Ordering method.
JP1296757A 1989-11-15 1989-11-15 Wiring order determination system Pending JPH03156683A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1296757A JPH03156683A (en) 1989-11-15 1989-11-15 Wiring order determination system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1296757A JPH03156683A (en) 1989-11-15 1989-11-15 Wiring order determination system

Publications (1)

Publication Number Publication Date
JPH03156683A true JPH03156683A (en) 1991-07-04

Family

ID=17837726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1296757A Pending JPH03156683A (en) 1989-11-15 1989-11-15 Wiring order determination system

Country Status (1)

Country Link
JP (1) JPH03156683A (en)

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