JPH03155679A - Vertical mosfet - Google Patents
Vertical mosfetInfo
- Publication number
- JPH03155679A JPH03155679A JP1295932A JP29593289A JPH03155679A JP H03155679 A JPH03155679 A JP H03155679A JP 1295932 A JP1295932 A JP 1295932A JP 29593289 A JP29593289 A JP 29593289A JP H03155679 A JPH03155679 A JP H03155679A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion region
- source
- trench
- type diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 230000006378 damage Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はアバランシェ降伏による破壊耐量を増大した縦
型ＭＯＳ Ｆ ＥＴに関するゆ（ロ）従来の技術
縦型ＭＯＳＦＥＴは、第４図に示すように、底部に高濃
度Ｎ＋型層（１）を有するＮ−型シリコン基板（２）を
ドレインとして、その表面上に所定の間隔でゲート電極
（ポリＳｉゲート） （３）が配置され、このゲート電
極（３）の下にチャンネル部を作るように基体り２）表
面にＰ型拡散領域（４）とＮ＋型ソース領域（５）を形
成したもので、ゲートへの電圧印加によってゲート下の
Ｐ型拡散領域（４）（チャンネル部）を通るドレイン電
流ＸＤ％を制御するようにＭＯＳＦＥＴを動作させるも
のである（例えば、特開昭６３−２６０１７６号公報）
、＜６）は、１電極、（７）はガードリングである。Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to a vertical MOSFET with increased breakdown resistance due to avalanche breakdown. An N- type silicon substrate (2) having a high concentration N+ type layer (1) at the bottom is used as a drain, and gate electrodes (poly-Si gates) (3) are arranged at predetermined intervals on the surface of the substrate. A P-type diffusion region (4) and an N+-type source region (5) are formed on the surface of the substrate so as to form a channel section under the electrode (3). The MOSFET is operated to control the drain current XD% passing through the type diffusion region (4) (channel part) (for example, Japanese Patent Laid-Open No. 63-260176).
, <6) is one electrode, and (7) is a guard ring.
斯る縦型ＭＯ３ＦＥＴは、大電流高速スイッチングが可
能なので、モータ制御、スイッチングレギュレータ、Ｃ
ＲＴ偏向用として多用されている。Such a vertical MO3FET is capable of high-speed high-current switching, so it can be used in motor control, switching regulators, and C
It is widely used for RT deflection.
（ハ〉発明が解決しようとする課題
しかしながら、第５図のようにリアクトル負荷（８〉を
ＭＯＳトランジスタ（９）でスイッチングする場合、コ
イル負荷り８）を遮断した瞬間に高い電流変化率ｄｉ／
ｄｔで大きなサージ電圧（１０）が発生し、このような
サージ電圧がＭＯＳトランジスタ（９）ノソース・ドレ
イン間に印加されることによりＭＯＳトランジスタ（９
）は容易にアバランシェ領域まで印加される。(C) Problems to be Solved by the Invention However, when the reactor load (8) is switched by a MOS transistor (9) as shown in Fig. 5, the current change rate di/
A large surge voltage (10) is generated at dt, and this surge voltage is applied between the source and drain of the MOS transistor (9).
) is easily applied up to the avalanche region.
アバランシェ領域まで印加されたＭＯＳトランジスタ（
９）は、第６図に示すように主にＰ型拡散領域（４）と
Ｎ−型基板（２）とが形成する接合ダイオード（１１）
がなだれ降伏することにより電流を吸収しようとする。MOS transistor applied up to the avalanche region (
9) is a junction diode (11) mainly formed by a P-type diffusion region (4) and an N-type substrate (2), as shown in FIG.
tries to absorb the current by avalanche breakdown.
ところが、ＭＯＳトランジスタ（９）はＮ２ソース領域
（５）をエミッタ、Ｐ型拡散領域（４）をベース、Ｎ−
型基体（２）をフレフタとする寄生トランジスタ（１２
）が不可避的に形成されてしまい、また Ｎ ＋ソース
領域（５）の底部はピンチ構造となるため、ソース領域
（５）とＰ型拡散領域（４）とのＰＮ接合はピンチ抵抗
（１３）により順バイアスされる電位差に賽易に達して
寄生トランジスタ（１２）が導通してしまう。−旦寄生
トランリスタク１２）が導通すると、ＭＯＳトランジス
タの阻止耐圧は寄生トランジスタフ１２）の■。。まで
低下するので、アバランシェ電流が制御がきかない状態
で能動化したセルを流れ、結果的に素子が破壊されてし
まう現象がある。However, the MOS transistor (9) uses the N2 source region (5) as the emitter, the P type diffusion region (4) as the base, and the N-
A parasitic transistor (12
) is inevitably formed, and the bottom of the N + source region (5) has a pinch structure, so the PN junction between the source region (5) and the P-type diffusion region (4) has a pinch resistance (13). The parasitic transistor (12) easily reaches a potential difference that is forward biased by the parasitic transistor (12). - Once the parasitic transistor transistor 12) becomes conductive, the blocking voltage of the MOS transistor is the same as that of the parasitic transistor transistor 12). . As a result, avalanche current flows uncontrollably through the activated cell, resulting in destruction of the device.
このように、従来の縦型ＭＯＳＦＥＴはアバランシェ降
伏に対して無防備であり、破壊に至り易い欠点があった
。As described above, conventional vertical MOSFETs are vulnerable to avalanche breakdown and have the disadvantage of being easily destroyed.
（ニ）課題をＳ決するための手段
本発明は上記従来の欠点に鑑み成されたもので、ＭＯＳ
セル能動領域を囲むＰ型拡散領域（２４）に少なくとも
ＮＩ型ソース領域（２８）よりは深くトレンチ（３３）
を形成し、ドレンチク３３）内にソース電極（３２）を
コンタクトさせることによりアバランシェ降伏時の素子
破壊を防止し得る縦型ＭＯＳＦＥＴを提供するものであ
る。(d) Means for solving the problem The present invention has been made in view of the above-mentioned drawbacks of the conventional technology.
A trench (33) is formed in the P-type diffusion region (24) surrounding the cell active region at least deeper than the NI-type source region (28).
The present invention provides a vertical MOSFET that can prevent device destruction during avalanche breakdown by forming a source electrode (32) in the trench 33).
（＊）作用
本発明によれば、アバランシェ降伏は空乏層（３４）の
内部電界が、高いガードリング（２５）に近い部分で発
生し易いから、その降伏電流ｉはＰ型拡散領域（２４）
のうち最外周のＰ型拡散領域（２４）に流れる。その際
、トレンチ（３３）の溝部にまでソース電極〈３２〉が
コンタクトしているので、降伏電流１はソース電極（３
２）へ流れて最外周のＰ型拡散領域（２４）の寄生トラ
ンジスタ（１２）を導通させることができない、従って
、素子を寄生トランジスタ効果による破壊から保護する
ことが出来る。(*) Effect According to the present invention, since avalanche breakdown is likely to occur in the portion where the internal electric field of the depletion layer (34) is close to the high guard ring (25), the breakdown current i is
It flows into the outermost P-type diffusion region (24). At this time, since the source electrode <32> is in contact with the groove part of the trench (33), the breakdown current 1 is
2) and cannot make the parasitic transistor (12) in the outermost P-type diffusion region (24) conductive. Therefore, the device can be protected from destruction due to the parasitic transistor effect.
〈へ）実施例
以下に本発明の一実施例を図面を参照しながら詳細に説
明する。第１図と第２図は本発明の縦型ＭＯ３ＦＥＴを
示す断面図と拡大断面図、第３図は平面図である。<Example> An example of the present invention will be described below in detail with reference to the drawings. 1 and 2 are a sectional view and an enlarged sectional view showing a vertical MO3FET of the present invention, and FIG. 3 is a plan view.
共通ドレインとなるシリコン半導体基体（２１〉は、裏
面電極形成用のＮ１型半導体層（２２）と、Ｎ−型半導
体層（２３）との２層構造から成る。Ｎ−型半導体層（
２３）の表面には、第３図の如くＰ型拡散領域（２４）
が格子状に形成され、その周囲には、Ｐ型拡散領域（２
４）を囲むようにＰ型のガードリング（２５）が幾重に
も形成されている。（２６）はＮ“型チヘ・ンネルスト
ッパ、（２７）はフィールド電極である。The silicon semiconductor substrate (21), which becomes the common drain, has a two-layer structure of an N1 type semiconductor layer (22) for forming a back electrode and an N-type semiconductor layer (23).
23), there is a P-type diffusion region (24) as shown in Figure 3.
is formed in a lattice shape, and around it is a P-type diffusion region (2
P-type guard rings (25) are formed in multiple layers so as to surround 4). (26) is an N" type chihe/nnel stopper, and (27) is a field electrode.
Ｐ型拡散領域（２４）の表面には、格子パターンの格子
を夫々囲むようにし′″ｃＮ“型ソース領域（２８）が
形成され、ソース領域（２８）とＮ−型半導体層（２３
）表面で挾まれたＰ型拡散領域（２４）の表面をチャン
ネル部（２９）とする。チャンネル部（２９）上には、
シリコン酸化膜から成るゲート絶縁膜（３０）を介して
ポリシリコンのゲート電極（３１）が格子状パターンの
各網目の上を覆うようにして配置されている。個々に独
立したゲートを極（３１）は、櫛歯状のアルミ電極によ
って共通接続され外部接続用の図示せぬポンディングパ
ッドに接続されている。Ｐ型拡散領域（２４）の表面に
は、Ｐ型拡散領域（２４）とＮ＋ソース領域（２８）の
両方にフンタクトするＡ、ｉ！、ＡＮ−５ｉ等のソース
電極〈３２）が櫛歯状に形成されて図示せぬソースポン
ディングパッドに接続されている。'cN' type source regions (28) are formed on the surface of the P type diffusion region (24) so as to surround each of the gratings of the lattice pattern, and the source region (28) and the N- type semiconductor layer (23)
) The surface of the P-type diffusion region (24) sandwiched between the surfaces is defined as a channel portion (29). On the channel part (29),
A polysilicon gate electrode (31) is arranged to cover each mesh of the lattice pattern with a gate insulating film (30) made of a silicon oxide film interposed therebetween. The individual gate poles (31) are commonly connected by a comb-shaped aluminum electrode and connected to a not-shown bonding pad for external connection. The surface of the P-type diffusion region (24) has A, i! which contacts both the P-type diffusion region (24) and the N+ source region (28). , AN-5i, etc., is formed into a comb-like shape and connected to a source bonding pad (not shown).
格子状パターンの最外周のＰ型拡散領域（２４）には、
ソース領域（２８）の外側に格子状パターンを囲むよう
にして素面から数μｍ掘り下げられたトレンチ（３３）
が形成され、ソース１極（３２）はこの溝内にもフンタ
クトするようにトレンチ（３３）内に埋め込まれる。In the outermost P-type diffusion region (24) of the grid pattern,
A trench (33) dug several μm from the bare surface so as to surround a grid pattern outside the source region (28)
is formed, and the source 1 pole (32) is buried in the trench (33) so as to be in contact with this trench.
斯る構成の縦型ＭＯＳＦＥＴにおいて、ソース・ドレイ
ン間にリアクトル負荷の逆起電圧によってアバランシェ
領域を超える逆方向電圧が印加された場合、その降伏電
流ｉは、空乏層（３４〉の内部電界が高い部分つまりガ
ードリング（２５）に近い部分で特に生じ易く、そのた
め降伏電流ｌはＰ聖域欣領域（２４）のうち最外周のも
のに流れる。最外周のＰ型拡散領域（２４）にはトレン
チ〈３３〉とソース電極（３２）が設けられているので
、Ｐ聖域牧領域（２４）内の抵抗分は激減されており、
そのため降伏電流ｉはソース領域（２８）とＰ型拡散領
域（２４）とのＰＮ接合を順バイアスすること無くソー
ス電極（３２）によって外部に流出する。従って、最外
周部分で寄生トランジスタが導通するはずも無く、また
トレンチ（３３）によって降伏電流ｉを積極的に流出さ
せるので、セル内部が寄生トランジスタ効果に陥ること
も無い。In a vertical MOSFET with such a configuration, when a reverse voltage exceeding the avalanche region is applied between the source and drain due to the back electromotive force of the reactor load, the breakdown current i is caused by the high internal electric field of the depletion layer (34). The breakdown current l flows to the outermost P-type diffusion region (24), and the breakdown current l flows to the outermost P-type diffusion region (24). 33> and the source electrode (32), the resistance within the P sanctuary area (24) is drastically reduced.
Therefore, the breakdown current i flows out through the source electrode (32) without forward biasing the PN junction between the source region (28) and the P-type diffusion region (24). Therefore, there is no possibility that the parasitic transistor becomes conductive at the outermost peripheral portion, and since the breakdown current i is actively drained by the trench (33), the inside of the cell will not suffer from parasitic transistor effect.
尚、Ｐ型拡散領域（２４）は電極形成用の高濃度で深い
部分（３５）とチャンネル形成用のやや低濃度で浅い部
分（３６）との２重構造になっており、トレンチ＜３３
）はソース領域（２８）下部の抵抗分を低減するのが目
的であるから、トレンチ（３３〉の深さは少なくともソ
ース領域（２８）よりは深く、望ましくは浅い部分（３
６）より深い方が抵抗分減少となる。また、Ｎゝソース
領域＜２８）と１・１／ンチ（３３）とが接していても
良い。The P-type diffusion region (24) has a double structure of a deep, high concentration portion (35) for forming an electrode and a shallow portion (36) with a slightly lower concentration for forming a channel.
) is intended to reduce the resistance below the source region (28), so the depth of the trench (33) is at least deeper than the source region (28), and preferably the shallower part (33) is deeper than the source region (28).
6) The resistance decreases as the depth increases. Further, the N source region <28) and the 1.1/inch (33) may be in contact with each other.
（ト）発明の効果
以上に説明した通り、本発明によればトレンチ（３３）
とソースｔａｉ （３２）によりアバランシェ降伏電流
ｉを積極的に流出させることができるので、Ｐ型拡散領
域（２４）の外周部分およびセル内部で寄生トランジス
タを導通させずに済み、素子を破壊から保護することが
できる。従って回路設計が容易になり機器を簡素化でき
る。(g) Effects of the invention As explained above, according to the invention, the trench (33)
Since the avalanche breakdown current i can be actively caused to flow out by the source tai (32) and the source tai (32), there is no need to conduct the parasitic transistor in the outer periphery of the P-type diffusion region (24) and inside the cell, thereby protecting the device from destruction. can do. Therefore, circuit design becomes easy and equipment can be simplified.
第１図〜第３図は夫々本発明を説明するための断面図、
拡大断面図、および平面図、第４図〜第６図は夫々従来
例を説明するための断面図、回路図および拡大断面図で
ある。
第１図
第２図1 to 3 are sectional views for explaining the present invention, respectively;
An enlarged sectional view, a plan view, and FIGS. 4 to 6 are a sectional view, a circuit diagram, and an enlarged sectional view, respectively, for explaining a conventional example. Figure 1 Figure 2
Claims (3)
、 前記逆導電型拡散領域の一部を構成しＭＯＳセル能動領
域を囲む最外周の拡散領域と、 前記逆導電型の拡散領域の表面に形成した一導電型のソ
ース領域と、 前記ソース領域と前記基体の表面にはさまれたチャンネ
ル部上に絶縁膜を介して配置したゲート電極と、 前記ソース領域と前記逆導電型拡散領域との両方にコン
タクトするソース電極とを具備する縦型ＭＯＳＦＥＴに
おいて、 前記最外周の拡散領域に前記ＭＯＳセル能動領域を囲む
ように少なくとも前記ソース領域よりは深くトレンチを
形成し、このトレンチ内にも前記ソース電極をコンタク
トさせたことを特徴とする縦型ＭＯＳＦＥＴ。(1) A semiconductor substrate of one conductivity type serving as a common drain, a diffusion region of an opposite conductivity type formed on the surface of the semiconductor substrate, and a diffusion region of the opposite conductivity type forming a part of the diffusion region of the opposite conductivity type and surrounding the MOS cell active region. a diffusion region at the outer periphery, a source region of one conductivity type formed on the surface of the diffusion region of the opposite conductivity type, and a source region disposed via an insulating film on a channel portion sandwiched between the source region and the surface of the base body. In a vertical MOSFET comprising a gate electrode and a source electrode in contact with both the source region and the reverse conductivity type diffusion region, at least the source is arranged in the outermost diffusion region so as to surround the MOS cell active region. A vertical MOSFET characterized in that a trench is formed deeper than the region, and the source electrode is also in contact with the inside of the trench.
する請求項第１項に記載の縦型ＭＯＳＦＥＴ。(2) The vertical MOSFET according to claim 1, wherein the source electrode is an aluminum electrode.
有することを特徴とする請求項第１項に記載の縦型ＭＯ
ＳＦＥＴ。(3) The vertical MO according to claim 1, wherein the diffusion region of opposite conductivity type has a lattice pattern.
SFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1295932A JPH03155679A (en) | 1989-11-14 | 1989-11-14 | Vertical mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1295932A JPH03155679A (en) | 1989-11-14 | 1989-11-14 | Vertical mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03155679A true JPH03155679A (en) | 1991-07-03 |
Family
ID=17826987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1295932A Pending JPH03155679A (en) | 1989-11-14 | 1989-11-14 | Vertical mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03155679A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310380B1 (en) * | 2000-03-06 | 2001-10-30 | Chartered Semiconductor Manufacturing, Inc. | Electrostatic discharge protection transistor structure with a trench extending through the source or drain silicide layers |
-
1989
- 1989-11-14 JP JP1295932A patent/JPH03155679A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6310380B1 (en) * | 2000-03-06 | 2001-10-30 | Chartered Semiconductor Manufacturing, Inc. | Electrostatic discharge protection transistor structure with a trench extending through the source or drain silicide layers |
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