JPH03155369A - Peak current controlled converter - Google Patents

Abstract

PURPOSE:To operate a converter stably even for a larger resistive load by controlling a peak current controlled converter at a part other than a predetermined start-up part of a detected peak current. CONSTITUTION:An output voltage Vo is compared with a reference voltage Vr in a comparator/amplifier E/A output therefrom is then inputted to one input of a comparing means COM. A clock signal CLK sets an FF1 which produces an output for every clock signal. On the other hand, a peak voltage Vsense induced from an input current is ORed with a signal obtained by delaying 3 the clock and inputted to the other input of the COM, output therefrom then resets the FF1. At the rising of the voltage Vsense, a pulse signal from which a pulsating part due to the reverse recovery current of rectifying diodes D1, D2 is removed is produced from the FF1 and employed for turning a transistor Q1 ON/OFF. By such arrangement, noise due to a large resistive load or unstable factor due to recovery current of the diodes D1, D2 are removed resulting in a stabilized operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a peak current control type converter such as a switching regulator.

(Prior Art) FIG. 5 shows a basic circuit diagram of a peak current control type converter according to a conventional example.

In the figure, 1 is a main power supply, T is a transformer, Ql is a field effect transistor which is a switching means, F/F is a flip-flop which is a drive means for driving the field effect transistor Q1, 2 is an input terminal for a clock signal, and R1 is the resistor for Q1 peak current detection, R2 is the resistor, C1 is the capacitor, COM is the comparison means, E/A is the comparison amplification means, V
r is a reference voltage power supply, Dl and D2 are rectifier diodes, C
2 is a capacitor, L is an inductance, and RL is a load.

Here, a control loop for driving the field effect transistor Q1 is constituted by a flip-flop F/F, a detection resistor R1, a resistor R2, a capacitor C1, a comparison means C○M, a comparison amplification means E/A, and a reference voltage power supply vr. are doing.

In this circuit, the clock signal is sent to the flip-flop F
/F is input to the set input terminal S of F/F, and the output of the flip-flop F/F becomes ○N for each clock signal, and the field effect transistor Q1 is driven. flip flop F
The reset terminal R of /F is the output terminal V on the secondary winding side of the transformer.

Comparing means C compares the voltage of the amplified output Ver with the voltage of the reference voltage power supply Vr and the peak current detection output Vs e n se of the field effect transistor Q1, and outputs the voltage when both become the same voltage. , OM are connected, and when the comparator COM outputs an output, the output of the flip-flop F/F is turned OFF and the field effect transistor Q1 is not driven.

The operating waveform in such a normal state is as shown in FIG. 6(a). As can be seen from the above operation, the peak current of the field effect transistor Q1 is incorporated into the control loop, and the field effect transistor Q
1 is controlled, this type of converter has the advantage that it is difficult to cause damage. In addition, since the equivalent circuit viewed from the output terminal Vo on the secondary winding side of the transformer can be considered as a constant current power supply, there is no phase rotation caused by inductance L and capacitor 〇, and it has the advantage of being stable in principle.

However, when this peak current control is applied to each forward type converter as shown in Fig. 5, the reverse recovery current due to the rectifier diode D2 flows through the rectifier diode D1 when the field effect transistor Q1 is driven.
), a rising pulse-like waveform (the part indicated by P in the figure) is generated. This is larger as the performance of the rectifier diodes Di and D2 is inferior, and when this rising pulse reaches the above output Ver, at this point the flip-flop F
The /F output turns OFF, resulting in an abnormal operating waveform as shown in FIG. 6(b). As a result, the operation becomes unstable and disturbances are likely to occur, and in the worst case, the field effect transistor Q1 may be damaged.

In order to solve this problem, a method has been adopted in which the peak current detection output Vsense is passed through an integrating circuit consisting of a resistor R2 and a capacitor C1 to attenuate the rising pulse.

(Problem to be Solved by the Invention) However, in this method, the peak current detection output vsens
This was not a perfect solution, as e itself was attenuated, and if the detection resistor R1 was increased in consideration of attenuation, the efficiency would decrease.

In particular, when the load resistance RL is large, the peak current detection output V s ert se decreases, but the current flowing through the rectifier diodes Di and D2 on the secondary side does not decrease, so the above phenomenon is remarkable, and the peak current This has become an important technical issue when adopting control.

The present invention has been made based on this background, and eliminates the causes of instability caused by pulses caused by the reverse recovery current of the secondary side rectifier diode and noise when the load resistance is large, and improves the forward converter. The purpose of this invention is to provide a peak current control type converter that operates stably even in the case of a building.

(Means for Solving the Problems) To achieve the above object, the present invention provides a peak current detection output Vsens in a peak current control type converter.
This is characterized in that e is used for control except for a certain part of its rising edge.

(Function) Since the peak current detection output Vsense is used for control, excluding the rising pulse-like output portion caused by the reverse recovery current of the rectifier diode, the operation is stable.
No disturbance occurs.

(Example) Hereinafter, an example of the present invention will be described based on FIGS. 1 to 4.

FIG. 1 is a circuit diagram of a peak current control type converter according to a first embodiment of the present invention. The difference from the conventional example is that instead of inputting the peak current detection output Vsense to the comparison means COM through an integrating circuit consisting of a resistor R2 and a capacitor C1, a clock signal inputted to the set terminal of the flip-flop F/F is inputted. A delayed pulse generating means 3 is added, and its output and the peak current detection output V s e n se of the field effect transistor Q1 are input to the OR means 4, and the OR output is input to the comparison means COM. This is the point.

In this circuit, the clock signal is sent to the flip-flop F
The output of the flip-flop F/F is turned on every time this clock signal is input, and the field effect transistor Q1 is driven. The clock signal is also input to the delayed pulse generating means 3, which outputs a delayed pulse delayed by the time At as shown in FIG. This Δt is set to a time during which a pulse (P in FIG. 6) generated due to the reverse recovery current of the secondary side rectifier diodes Di and D2 is sufficiently received. As shown in FIG. 2, the output of the OR means 4 to which this delayed pulse and the peak current detection output V s e n se of the field effect transistor Q1 are input is the peak current detection output V
At the rise of s e n se , the pulse portion generated due to the reverse recovery current of the secondary side rectifier diodes Di and D2 is removed, so that it operates without being affected by switching noise. Can be done.

Specific circuits of such delayed pulse generation means include a one-shot multivibrator 5 as shown in FIG. 3(a), and a delay circuit 6 and a flip-flop 7 as shown in FIG. 4(a). A circuit that combines these can be used. Note that FIG. 3(b) and FIG. 4(b) show the respective output waveforms.

Although the above embodiments were applied to a forward type, they can be similarly applied to a flyback type.

(Effects of the Invention) As explained above, according to the present invention, the causes of instability caused by pulses caused by the reverse recovery current of the secondary side rectifier diode and noise when the load resistance is small are eliminated, and the forward converter It is possible to obtain a peak current control type converter that operates stably even in the case of .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a peak current control type converter according to an embodiment of the present invention, FIG. 2 is an operating waveform diagram in the circuit of FIG. 1, and FIG. 3 is a delay that can be applied to the embodiment according to FIG. 1. Circuit diagram of pulse generating means (a) and its operating waveform diagram (b)
, FIG. 4 is a circuit diagram (a) of another delayed pulse generating means that can be applied to the embodiment according to FIG. 1, and its operation waveform diagram (b).
, FIG. 5 is a circuit diagram of a peak current control type converter according to a conventional example, and FIG. 6 shows an operating waveform diagram (,) in a normal state and an operating waveform diagram (b) in an abnormal state in the circuit of FIG. 1. . Ql...Field effect transistor F/F...Flip-flop, 3...Delay pulse generating means, 4
...Order means, COM...Comparison means. Figure 2 (a) (b) Q-car "-1- Figure (b)

Claims (2)

[Claims] (1) A peak current control type converter characterized in that the peak current detection output is used for control except for a certain part of its rising edge. (2) a switching means connected to the primary winding of the transformer; a comparing means for comparing the peak current detection output of the switching means with a reference voltage output from the secondary winding of the transformer; and a clock signal. and a drive means for the switching means which is set by the output of the comparison means and reset by the output of the comparison means, further comprising delay pulse generation means to which the clock signal is input, the output of which and the current of the switching means. A peak current control type converter characterized in that an OR output with a detection output is inputted to the comparison means as a peak current detection output.