JPH03154909A - Logic circuit device - Google Patents

Abstract

PURPOSE:To effectively perform the logical verification by producing a reset signal only at reception of the first system reset signal and resetting a register. CONSTITUTION:A register 1 to which a system resetting operation is impossible is reset only when the first system reset signal is applied to the register 1 from a reset signal generating circuit 3. Thus it is possible to effectively prevent such a case where the output of the register 1 is unstabilized before the data are set to the register 1. Then the output of the register 1 can be kept stable with the set data after the data are set to the register 1 regardless of a fact whether the system resetting operation is applied again or not. Thus, a logical circuit 2 can be totally stabilized and then undergoes the effective logical verifi cation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a logic circuit device that can effectively verify the function of a logic circuit including registers that cannot be subjected to a system reset.

(Prior Art) Recently, various ASIC circuits have been developed and designed using CAD technology. This type of ASIC circuit uses gate array technology, sea of gate technology, etc. to construct a circuit according to user specifications, and turns this into a dedicated circuit.

By the way, registers and the like included in general logic circuits are configured so that they can be initialized by, for example, a system reset operation, in order to ensure their versatility. However, since the above-mentioned ASIC circuit is designed as a dedicated circuit to eliminate unnecessary circuitry, it is often configured to include a register that cannot be subjected to a system reset.

Therefore, when attempting to verify the logical function of such an ASIC circuit on CAD, it is necessary to set initial data in the above-mentioned register on test data each time. In addition, since the register is in an undefined state before test data is set in the register, there is a problem in that the operation of the next stage circuit that receives the output from the register is adversely affected. Specifically, since the register is in an undefined state, the operation of subsequent circuits becomes unstable, and the problem arises that its logic cannot be verified.

(Problem to be Solved by the Invention) Conventionally, when trying to verify the logic on CAD of a logic circuit that includes registers that cannot be reset, it is difficult to test the registers. It is necessary to write data each time, and the contents of the register are in an undefined state, especially during the period until the first data is written to the register, which adversely affects the operation of the next stage circuit. There was a problem in that it was not possible to perform logic verification on subsequent circuits.

The present invention was made in consideration of these circumstances, and its purpose is to efficiently and stably verify the logic of registers that cannot be reset without leaving them undefined. The object of the present invention is to provide a logic circuit device that can perform the following functions.

[Structure of the Invention] (Means for Solving the Problems) The present invention relates to a logic circuit device including a register to which a system reset cannot be applied. The present invention is characterized in that a reset signal generation circuit is provided for generating a reset signal and resetting the register only when a reset signal is received.

Further, the second invention provides a mask signal generation circuit that continuously generates and outputs a mask signal from the time when a latch signal for latching data is first input to the register, and generates and outputs a mask signal for a predetermined period of time. By delaying and applying the mask signal to the gate circuit, transmission of the output of the register to the next stage circuit is prevented for a period until the delayed mask signal is applied. It is.

(Function) According to the first invention configured as described above, a register that cannot be subjected to a system reset is reset only when a system reset signal is first applied by the reset signal generation circuit. Therefore, it is possible to effectively prevent the output of the register from becoming undefined during the period after the system reset is applied until data is set in the register. After the data is set in the register,
Regardless of whether the system reset is applied again or not, the output of the above register can be stabilized by the set data, so the undefined state of the register will spread to the next stage circuit and the entire circuit will become unstable. Things will go away.

According to the second invention, after the first data is latched in the register and its output is stabilized, the mask signal applied to the gate circuit allows the output of the register to be transmitted to the next stage circuit. The output of the register, which is in an undefined state, is not transmitted to the next stage circuit until the first data is latched in the register and the output is stabilized.

As a result, an undefined state from a register that cannot be reset by a system will not be inadvertently transmitted to the next stage circuit, so it is possible to stabilize the entire logic circuit and efficiently verify its logic. becomes possible.

(Example) Hereinafter, a logic circuit device according to an example of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a logic circuit device showing a first embodiment, where l is a register to which a system reset cannot be applied, and 2 is a logic circuit main body which is the next stage circuit.

Note that in some cases, only one register l, which cannot be reset by the system, is provided for the logic circuit device (logic circuit main body 2) that is subject to logic verification by CAD, but in general, multiple registers are provided. provided.

Thus, the register l receives input data DI applied to its data input terminal by a latch signal and latches it, for example, at the rising edge of the latch signal. Then, the latch data Do is transferred to the logic circuit main body 2 which is the next stage circuit.
It plays a role in

Here, the feature of this embodiment device is that it has a function of generating the reset signal RES only once upon receiving the system reset signal R5 first applied to the logic circuit main body 2 to reset the register 1. The point is that a reset signal generating circuit 3 is provided to provide a reset signal. That is, this reset signal generation circuit 3 takes in the system reset signal R3 only once and continuously outputs the reset signal RES at the [H] level. The register 1 is reset at the rising edge of the reset signal RES. Then, the reset signal generating circuit 3 receives a subsequent system reset signal R8 by the reset signal RES of the [H] level.
It is configured to prevent the uptake of I.

As a result, the reset signal generating circuit 3 generates the reset signal RE in response to the first applied system reset signal R8.
S is issued and the register l is reset only once. Even if the system reset signal R8 is given again after that, since the reset signal RES at the [H] level mentioned above is output, it is ignored and the data latched in register l is left unchanged. It is intended to be retained.

Note that the reset signal generation circuit 3 exhibiting such a function may be provided, for example, for a logic circuit device that is subject to logic verification by CAD, or may be provided for a logic circuit device that is subject to logic verification using CAD. It is also possible to provide one corresponding to each of a plurality of registers l that cannot be reset.

FIG. 2 is a timing chart schematically showing the operation mode of the embodiment device configured as described above. The characteristic operation of the embodiment device will be explained according to this operation timing diagram. First, the embodiment device operates according to a timing clock (system clock signals SYS, CLK) having a predetermined cycle.

As shown in Figure 2, the register cannot be directly reset by a system reset, so its output Do is undefined until, for example, when the power is turned on and logic verification processing is started, and data is latched there. state. Conventionally, the output Do of the register 1 in an undefined state was transmitted to the logic circuit main body 2 as is.

On the other hand, in this embodiment device, when a system reset is applied when starting the logic verification on CAD, the system reset signal R8 is detected and the reset signal generation circuit 3 outputs the [H] level reset signal. R.E.
S is output. This reset signal RES resets the register l, which has been in an undefined state, and stabilizes its output DO, for example, to [L].

Thereafter, in order to set predetermined data in the register 1, data DI is applied from the data input terminal, and a latch signal is applied during the data input period.The rise of the latch signal is detected and the input data DI is input. is latched into register l. The output DO of register 1 is then stabilized by the latch data.

After latching the data in register 1 in this way, in order to set the next data in register 1 again, data DI is applied from the data input terminal and a latch signal is added during the data input period. Output D of register l
O simply becomes newly latched data, and there is no equivalent change in its stable state.

As a result, the output DO (reset data or latch data) 0 of register l, which is always in a stable state, is transmitted to the logic circuit main body 2, which is the next stage circuit of register l, after the above-mentioned system reset is applied. This prevents data in the register 1 in an undefined state from being inadvertently transmitted to the logic circuit main body 2 as in the conventional case.

Therefore, the logic circuit main body 2 has a register l whose state is clear.
It becomes possible to carry out logic verification operation by taking in the output Do of , and it becomes possible to stabilize the operation and perform logic verification accurately. Furthermore, since the register l can be automatically reset, there is an effect that there is no need to pay special consideration to how to provide the verification test data in order to avoid the undefined state of the register l.

Furthermore, according to the above-mentioned configuration, once the output Do of register (2) has been stabilized, even if a system reset is applied again, register (1) will not be reset, so that it will not be latched into register (1). Logic verification can proceed stably while maintaining the data as is. Therefore, the register l is not reset inadvertently, so there is no need to latch the same data in the register l every time the system is reset, and it is also possible to improve the efficiency of logic verification.

Next, a second embodiment of the present invention will be described.

In this embodiment, as shown in the schematic configuration in FIG. 3, a latch signal for setting data in register 1 is used to control the transmission of the output DO of register 1 to logic circuit main body 2. This feature is characterized in that a mask signal Qx is generated for the purpose.

That is, as shown in FIG. 4, the mask signal generation circuit 4 inputs a latch signal for setting data DI in the register 1, and generates a mask signal Qx at the [H] level at the rising timing. Generates and outputs. This mask signal Qx is applied to a gate circuit 6 after being delayed via a delay circuit 5 over a period of time that allows for the latching operation period of the input data DI to the register I. This gate circuit 6 receives the [H] level mask signal Q delayed via the delay circuit 5.
The output D of the register l is output only during the period when Y is being input.
0 to the logic circuit main body 2. In other words, the gate circuit 6 inputs the output DO of the register I to the logic circuit main body 2 when the mask signal Q at the level [HE11] is not input, that is, when the signal at the [L] level is applied. This serves as an obstacle to transmission.

According to the embodiment device configured in this manner, the mask signal generating circuit 4 receives the latch signal when the data is first latched into the register I, and thereafter continuously generates the mask signal Qx at the [H] level. This allows the transmission of the output DO of the register l to the logic circuit main body 2 via the gate circuit 6, so that the output Do of the register 1 which was in an undefined state before that is transmitted to the logic circuit main body 2.
transmission can be effectively prevented. In other words, it is possible to effectively prevent involuntary data transmission to the logic circuit main body 2 during the period from when the first data is latched in the register 1 until the output Do becomes stable.

As a result, after setting the data necessary for logic verification in register 1, the logic circuit main body 2 of the set data is
3. Therefore, data in an undefined state in register l will not be inadvertently given to the logic circuit main body 2 as in the conventional case, and the logic verification can proceed stably. It becomes possible.

Therefore, the same effect as the previous embodiment device can be achieved.

Note that the present invention is not limited to the above-described embodiments. For example, in the embodiment shown in FIG. 5, if the data latching operation to the register 1 is fast and the output of the mask signal Qx is slightly delayed, the delay circuit 5 can be omitted. Further, the mask signal generation circuit 4 may be of any type as long as it generates the mask signal Qx in response only to the first input latch signal. Therefore, it can be easily realized using a retriggerable multivibrator or the like. Furthermore, by changing the inputs of the reset signal generation circuit 30 shown in the previous embodiment, it is also possible to use this circuit as it is as the mask signal generation circuit 4. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, a logic circuit including a register that cannot be subjected to a system reset can be CA
When verifying logic on D, the output of the register does not remain undefined until the data is latched into the register, and can be stabilized for the next stage circuit. This has a great practical effect of stabilizing it and making it possible to effectively proceed with logical verification.

[Brief explanation of the drawing]

The figure shows a logic circuit device according to an embodiment of the present invention, and FIG. 1 is a schematic diagram of the main part of the device of the first embodiment;
FIG. 2 is a diagram schematically showing the operation timing and effects of the device of the first embodiment, FIG. 3 is a schematic diagram of the main part of the device of the second embodiment, and FIG. 4 is a diagram of the device of the second embodiment. FIG. 2 is a diagram schematically showing the operation timing and its effect. ■... 5 registers that cannot be reset by the system, 2... Logic circuit main body (next stage circuit), 3...
...Reset signal generation circuit, 4...Mask signal generation circuit, 5...Delay circuit, 6...Gate circuit.

Claims (2)

[Claims] (1) In a logic circuit device that includes registers that cannot be subjected to system reset, a reset signal generation circuit is provided that generates a reset signal upon receiving the first system reset signal, and this reset signal is used to register the A logic circuit device characterized by resetting. (2) In a logic circuit device that includes registers that cannot be reset, a mask signal is continuously generated and output from the time when a latch signal for latching data is first input to the register. a mask signal generation circuit; a delay circuit that delays the mask signal for a predetermined time; and a delay circuit that prevents the output of the register from being transmitted to the next stage circuit until the delayed mask signal is applied. 1. A logic circuit device comprising a gate circuit.